1
Outline
• Digital circuits –
• Flip-flops (sequential logic) – timing diagrams
– S-R flip-flop
– J-K flip flop
– Counters
Flip-Flop – Sequential logic
Q
A
Q’
B
• Make the truth table of this circuit.
A
B
Q
Q’
comment
Low
Low
High
High
Not used normally
Low
High
High
Low
High
Low
Low
High
High
High
either
opposite of Q
= previous level
• This works as a memory – which of A or B was low previously?
• Also works as “debouncer.” See H&H p. 506
• Call S-R (or S’-R’ to be more precise) flip-flop.
• A = S’ since low in A set Q to be 1
• B = R’
General flip-flop usage
• Memory
• Part of counter
General flip-flop control
• Set-reset (more commonly S’ and R’) inputs, which force the output Q to
be 1 or zero.
• Clock, which determines when certain action takes place in the output
• Data input(s), which determine what happens to Q on clock.
• Clocked SR FF
2
S
Q
S’
Q’
R
R’
Clock
Cl
Low
S
X
High
R
X
High
S’
R’
Q
High High Q prev
Low Low High
Q’
Q’ prev
High
comment
Not used
normally
High
High Low Low High High
Low
Low High High Low Low
High
Low Low High High Q prev
Q’ prev
• Even though this type FF remembers when the clock goes low what the
inputs were while the clock was still high (latching the input info),
• While the clock is high and inputs change, their effect immediately appear
at the output – transparent latch.
• D FF has additional mechanism so that input change gets transferred only
at the clock transition. Two of the possible circuits are:
S
S’
Q’
R
R’
Clock
Q
=
S
Q
R
Q’
3
D
S1
Q1
S2
Q2
R1
Q1 ’
R2
Q2 ’
Clock
Clock
1
0
S1
D
D
R1
D’
D’
Q1 = R2
D
Previous
Q1 ’= S2
D’
Previous
Q2
Previous
D
Q2’
Previous
D’
• Another D trigger (edge trigger)
Q
A
Q’
B
=
S’
Q
R’
Q’
Using
S1’
Q1
R1 ’
Q1 ’
Clock
S2’
Q2
R2 ’
Q2 ’
D
S3’
Q3
R3 ’
Q3 ’
4
• Rising edge trigger D FF
D=0
Clock 0
R1 ’ = Cl
Q1’
S2 ’=Q1 ’·Cl
R2 ’=D
Q2
Q2’
S1 ’= Q2 ’
D=1
Clock 1
R1 ’ = Cl
Q1’
S2 ’=Q1 ’·Cl
R2 ’=D
Q2
Q2’
S1 ’= Q2 ’
S3 ’= Q1 ’
R3 ’= Q2
Q3
Q3’
S3 ’= Q1 ’
R3 ’= Q2
Q3
Q3’
Clock 0
R1 ’ = Cl
Q1’
S2 ’=Q1 ’·Cl
R2 ’=D
Q2
Q2’
S1 ’= Q2 ’
S3 ’= Q1 ’
R3 ’= Q2
Q3
Q3’
Clock 1
R1 ’ = Cl
Q1’
S2 ’=Q1 ’·Cl
R2 ’=D
Q2
Q2’
S1 ’= Q2 ’
S3 ’= Q1 ’
R3 ’= Q2
Q3
Q3’
• What happens if D changes from 0 to 1, or vice versa while the clock level
stays at 1? What happens when the clock level is 0?
J-K flip flop
• The truth table of the J-K FF (74LS73, 74LS107, 74LS112 – all negative
edge triggered; 109 is positive edge triggered) is:
J
0
0
1
1
K
0
1
0
1
Q
Prev
0
1
Opposite of previous (toggle)
• When the clock comes in (edge or whatever type), if J=K=0, then the
output stays the same as what they were before the clock, and if J=K=1,
the output toggles (if it was zero before the clock, then it would change to
1, and if it was 1, it would change to 0). The latter is a typical usage of JK FF. If J and K and different, they the output follows J.
• Leaving J=K=1 (open if OK for TTL!), square pulses into the clock input,
what will happens to the output?
• What is the frequency of the output.
• What will happen if you get 10 JK FF (J=K=1 for all) and output of one is
fed to the next, what happens to the outputs?
• This is an asynchronous counter!