e x a m p l e 2. 20 a n N - r e s i s t o r c u r r e n t d i v i d e r Now consider the more general current divider having N resistors, as shown in Figure 2.38. It can be analyzed in the same manner as the two-resistor current divider. To begin, the element laws are i0 = −I (2.101) vn = Rn in , 1 ≤ n ≤ N. (2.102) Next, the application of KCL to either node yields i0 + i1 + · · · iN = 0 (2.103) and the application of KVL to the N − 1 internal loops yields vn = vn−1 , 1 ≤ n ≤ N. (2.104) Finally, Equations 2.101 through 2.104 can be solved to yield i0 = −I Gn in = G1 + G2 + · · · GN vn = 1 G1 + G2 + · · · GN (2.105) I, 1≤n≤N (2.106) I, 0≤n≤N (2.107) where Gn ≡ 1/Rn . This completes the analysis. As was the case for the two-resistor current divider, the preceding analysis shows that parallel resistors divide current in proportion to their conductances. This follows from the Gn in the numerator of the right-hand side of Equation 2.106. Additionally, the analysis again shows that parallel conductances add. To see this, let GP be the equivalent conductance of the N parallel resistors. Then, from Equation 2.107 we see that GP = I vn = G1 + G2 + · · · GN (2.108) from which it also follows that 1 RP = 1 R1 + 1 R2 + ··· 1 RN (2.109) where RP ≡ 1/GP is the equivalent resistance of the N parallel resistors. The latter result is summarized in Figure 2.40. 83a .. . F I G U R E 2.40 The equivalence of parallel resistors; for N = 2, RP = R1 R2 /(R1 + R2 ). R1 RN R2 1- –1 1- + ----1- + ... + -----Rp = ----RN R 1 R2 .. . Finally, the two current-divider examples illustrate an important point, namely that parallel elements all have the same voltage across their terminals because their terminals are connected directly across one another. This results in the KVL seen in Equations 2.80, 2.81, and 2.104, which state the equivalence of the terminal voltages. 83b e x a m p l e 2. 28 b a s i c c i r c u i t a n a l y s i s m e t h o d Solve the circuit in Figure 2.58 using the basic method. Step 1 is to assign the branch variables. Figure 2.59 shows the circuit with the variables properly assigned. In Step 2, we write the constituent relations: vS = −V (2.153) v1 = i1 R1 (2.154) v2 = i2 R2 (2.155) v3 = i3 R3 (2.156) v4 = i4 R4 (2.157) v5 = i5 R5 . (2.158) In Step 3, we write the KVL and KCL equations. The KVL equations with respect to the loop choice shown in Figure 2.60, are vS + v1 + v2 + v4 = 0 (2.159) −v2 + v3 = 0 (2.160) −v4 + v5 = 0 (2.161) R1 R2 R3 + F I G U R E 2.58 Circuit example. V - R4 R5 97a v i1 R1 v1 R2 + F I G U R E 2.59 Circuit with properly assigned variables. + vS + v2 - i3 i2 R3 + v3 - V + - i4 R4 iS + - v4 i5 R5 - v5 + (a) L1 L2 F I G U R E 2.60 Loop and node choice. + (b) V - L3 (d) 97b (c) At node (a), the KCL equation is i1 − i2 − i3 = 0. (2.162) Notice that nodes (b) and (c) are connected by a wire, so they yield only one KCL equation i2 + i3 − i4 − i5 = 0. (2.163) i4 + i5 − iS = 0. (2.164) Lastly, at node (d), we have Combining the constituent relations with KVL equations, we obtain −V + i1 R1 + i2 R2 + i4 R4 = 0 (2.165) −i2 R2 + i3 R3 = 0 (2.166) −i4 R4 + i5 R5 = 0. (2.167) By adding Equations 2.162 2.164, we have iS = i1 . (2.168) Eliminating i2 and i4 and substituting back into Equations 2.166 2.167 gives us i3 = iS i5 = iS R2 (2.169) R2 + R3 R4 (2.170) R4 + R5 V = iS R1 + R2 + R4 − = iS R1 + R2 R3 R2 + R3 + R22 R2 + R3 R4 R5 R4 + R5 R24 − R4 + R5 . (2.171) (2.172) As a quick sanity check of the solution, one might notice that the equivalent resistance of the network around the voltage source is R1 + R2 R3 + R4 R5 , which is correctly shown by Equation 2.172. 97c e x a m p l e 2.33 v o l t a g e - c o n t r o l l e d r e s i s t o r Thus far we have dealt with resistors that have a fixed resistance. However, like dependent sources, we can also have resistors whose values depend on other parameters. As an example, Figure 2.71 depicts a voltage-controlled resistor whose resistance RX is a function of vI . Let us suppose we are interested in determining vO as a function of vI for RX = f (vI ) = Ro vI where Ro is some known constant. Let Ro = 5 k/V. First, R1 and R2 form a simple voltage divider, and since R1 = R2 , we have vI = V/2. Second, RL and RX also form a voltage divider. Therefore, vO = V =V =V =V =V = RX RL + RX Ro vI RL + Ro vI 5 k/vI 10 k + 5 k/vI vI 2 + vI V 2 2+ V2 4+V V 2 . Substituting V = 5 V, we find that vO = 25/9 V. R1 = 100 k Ω F I G U R E 2.71 Circuit with voltage-dependent resistor. V + 5 V - vI R2 = 100 k Ω 107a RL = 10 kΩ vO RX = f(vI) 2.7 A F O R M U L A T I O N S U I T A B L E F O R A COMPUTER SOLUTION * Thus far we have seen several circuit examples that we solved by writing a set of equations based on the constituent relations for the elements, KVL, and KCL. There were as many independent equations as unknown variables, which allowed us to solve for any variable by simple algebra. The same set of equations can be written in matrix form so that they are amenable to a computer solution. For example, the circuit in Figure 2.1 analyzed using the basic method in Section 2.3.5 resulted in ten equations and ten unknowns. These ten equations are summarized as follows: v1 = i1 R1 (2.202) v2 = i2 R2 (2.203) v3 = i3 R3 (2.204) v4 = i4 R4 (2.205) v5 = V (2.206) −v5 + v1 − v2 = 0 (2.207) +v2 + v3 + v4 = 0 (2.208) −i5 − i1 = 0 (2.209) +i1 + i2 − i3 = 0 (2.210) i3 − i4 = 0. (2.211) The ten unknowns are v1 , v2 , v3 , v4 , v5 , i1 , i2 , i3 , i4 , and i5 . The equations can be rewritten so that constant voltages and currents appear on the left-hand side of the equation. 0 = v1 − i1 R1 (2.212) 0 = v2 − i2 R2 (2.213) 0 = v3 − i3 R3 (2.214) 0 = v4 − i4 R4 (2.215) V = v5 (2.216) 0 = v1 − v2 − v5 (2.217) 0 = v2 + v3 + v4 (2.218) 0 = −i5 − i1 (2.219) 0 = i1 + i2 − i3 (2.220) 0 = i3 − i4 . (2.221) 107b This set of equations can be written in matrix form as follows: 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 V 0 0 0 = 0 1 −1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 −R1 0 0 0 0 0 0 1 0 0 0 1 0 0 −1 0 1 0 0 0 0 −1 0 0 1 0 0 0 0 −R2 0 0 0 0 0 0 1 0 0 0 −R3 0 0 0 0 0 −1 1 0 0 0 −R4 0 0 0 0 0 −1 0 v1 v2 0 0 v3 0 v4 0 v5 0 i1 0 i2 −1 i3 0 i4 0 i5 (2.222) This matrix equation is in the form b = Ax where x is a column vector of unknowns and b is the column vector of drive voltages and currents. This vector of unknowns can be solved by a computer using standard linear algebraic techniques such as Cramer’s rule. In fact, the well known SPICE software package uses methods such as these to solve circuits.5 5. The examples in this chapter focused on linear circuits, which result in a set of linear simultaneous equations. However, the fundamental method of solving circuits based on KVL, KCL, and constituent relations applies equally well to nonlinear circuits. A nonlinear circuit might contain nonlinear circuit elements with constituent relations such as v = i3 R, or, i = K(ev/VT − 1). The resulting set of equations that arise will be nonlinear. Computer solution of such circuits makes use of another technique called linearization, which is discussed in Chapter 4. Further discussions of linearity are in Chapter 3, and a further treatment of nonlinear circuits is in Chapter 4. 107c e x a m p l e 3.9 e v e n m o r e o n t h e n o d e m e t h o d As we discussed earlier, it is often inefficient to use only Kirchhoff’s laws to analyze complicated circuits. For example, if we simply modify the example we saw on page 192 to the circuit shown in Figure 3.18, Kirchhoff’s laws alone will not be able to solve it easily. We will use the node method to solve the problem and the node assignment in Figure 3.19. With respect to the node assignment in Figure 3.19, we have the following equations: V − e1 e2 − e1 + R1 0 − e2 R2 e1 − e2 + R4 e1 − e3 R3 R2 + e2 − e3 R6 e3 − e1 + R3 e3 − e2 + R6 0 − e3 + R5 =0 (3.29) =0 (3.30) = 0. (3.31) We can rearrange the terms and express the equations in matrix form: 1 R1 + 1 R2 + 1 R3 − R1 2 − R1 2 1 R2 1 R4 + − R1 + 1 R6 − R1 3 6 V e1 3 R1 e2 = 0 − R1 6 1 1 +R +R e3 0 5 6 − R1 1 R3 i1 R1 v1 R2 + + i2 + V - i3 + v2 - - v3 - R3 i6 R4 iS + v 6 i4 + - R6 - v4 R5 - F I G U R E 3.18 Circuit with appropriate branch variables. i5 v5 + 135a e1 R1 + v2 - R 2 v1 + - + v3 F I G U R E 3.19 Node assignments of the circuit. - R3 + e2 V - + v 6 R4 + - - R6 v4 R5 - e3 v5 + Standard matrix techniques can be used to solve for the unknowns. Let us assign the following values to the resistors and voltage source: V=5V R1 = 50 R2 = 100 R3 = 100 R4 = 75 R5 = 75 R6 = 150 . Then we have: 1 25 −1 100 −1 100 −1 100 3 100 −1 150 −1 e1 100 −1 e 150 2 3 e3 100 1 10 =0 0 Solving for e1 , e2 , and e3 , we have e1 = 35/11 V, e2 = 15/11 V, and e3 = 15/11 V. Notice that e2 = e3 , that is, there is no current going through resistor R6 . Since R2 = R3 and R4 = R5 , the symmetry of the network between node e1 and ground splits the current going into node e1 evenly, thus causing the same voltage drop. 135b e x a m p l e 3 . 12 a m o r e c o m p l e x d e p e n d e n t - c u r r e n t s o u r c e p r o b l e m As a more complex example of the node analysis of a circuit containing dependent sources, consider the analysis of the circuit shown in Figure 3.28. This circuit has two dependent sources: one VCCS and one CCVS. In addition, its resistors are labeled with their conductances for convenience. To analyze the circuit in Figure 3.28, we redraw it as shown in Figure 3.29. Here, the VCCS is replaced by an independent current source having value Ĩ, and the CCVS is replaced by an independent voltage source having value Ṽ. Note that the new independent voltage source is not a floating voltage source because it is connected to ground through the known voltage V. The circuit in Figure 3.29 can be analyzed by the node method presented earlier. Since ground is already defined in the figure at Node 5, Step 1 is already complete. To complete Step 2, the node voltages are labeled as shown. The voltages at Nodes 1 and 2 are the unknown node voltages e1 and e2 . The voltage at Node 3 is set by the original independent voltage source, and is labeled accordingly. The voltage at Node 4 is also known since the new voltage source is an independent source, and it is labeled as such. Next, we perform Step 3, writing KCL for Nodes 1 and 2 in the process. This yields G1 (e1 − V − Ṽ) + G2 (e1 − e2 ) − I = 0 Node 4 - v + (3.64) Node 1 e1 G1 ri G2 + I Node 2 V i Node 3 + V F I G U R E 3.28 A circuit with two dependent sources. e2 G3 G4 gv - Node 5 145a Node 4 v - Node 1 + e1 V + V˜ G1 + V˜ G2 I Node 2 F I G U R E 3.29 The circuit from Figure 3.28 redrawn with independent sources. V i Node 3 e2 G3 + V I˜ G4 - Node 5 for Node 1, and G2 (e2 − e1 ) + G3 (e2 − V ) + G4 e2 + I − Ĩ = 0 (3.65) for Node 2. Equations 3.64 and 3.65 can be restated as G1 + G2 −G2 1 −G2 e1 = G2 + G3 + G4 e2 −1 G1 0 G1 G3 1 0 I V . Ĩ Ṽ (3.66) Following Step 4, Equation 3.66 is solved for e1 and e2 . This yields 1 G2 +G3 +G4 e1 = e2 G2 = G2 G1 +G2 1 G1 0 G1 −1 G3 1 0 I V Ĩ Ṽ 1 (G3 +G4 )I+(G1 (G2 +G3 +G4 )+G2 G3 )V+G2 Ĩ+G1 (G2 +G3 +G4 )Ṽ −G1 I+(G1 G2 +G1 G3 +G2 G3 )V+(G1 +G2 )Ĩ+G1 G2 Ṽ (3.67) 145b where = (G1 + G2 )(G2 + G3 + G4 ) − G22 . (3.68) Finally, we use Equations 3.67 and 3.68 to solve for i and v, the branch variables that control the CCVS and the VCCS, respectively. This yields i = Ĩ − G4 e2 1 = G1 G4 I − (G1 G2 + G1 G3 + G2 G3 )(G4 V − Ĩ ) − G1 G2 G4 Ṽ (3.69) v = e1 − V − Ṽ 1 (G3 + G4 )I − G2 G4 V + G2 Ĩ − G2 (G3 + G4 )Ṽ , = (3.70) which completes the node analysis of the circuit in Figure 3.29. Note that KCL was used at Node 5 to derive the first equality in Equation 3.69. To find the actual values for Ĩ and Ṽ, we now substitute Equations 3.69 and 3.70 into the element laws for the CCVS and the VCCS, respectively. This yields r Ṽ = ri = G1 G4 I − (G1 G2 + G1 G3 + G2 G3 )(G4 V − Ĩ ) − G1 G2 G4 Ṽ (3.71) for the CCVS, and Ĩ = gv = (G3 + G4 )I − G2 G4 V + G2 Ĩ − G2 (G3 + G4 )Ṽ g (3.72) for the VCCS. Finally, Equations 3.71 and 3.72 are jointly written as − gG2 gG2 (G3 + G4 ) Ĩ −r(G1 G2 + G1 G3 + G2 G3 ) + rG1 G2 G4 Ṽ g(G3 + G4 ) I −gG2 G4 = rG1 G4 −rG4 (G1 G2 + G1 G3 + G2 G3 ) (3.73) V and then solved simultaneously to yield Ĩ Ṽ = g(G3 + G4 ) −gG2 G4 (1 − rG3 ) r(G1 G4 + gG3 ) rG4 (G1 G2 + G1 G3 + G2 G3 ) + rG1 G2 G4 − gG2 (1 − rG3 ) I V . (3.74) The actual values of the dependent sources are now known. Finally, to complete the node analysis, at least to the point of determining e1 and e2 , Equation 3.74 is substituted 145c into Equation 3.67 to yield e1 = e2 G3 (1 + rg) + G4 (1 + rG1 ) g − G1 I G1 G2 + G1 G3 + G2 G3 − gG2 (1 − rG3 ) V − G2 G4 − rG1 G3 G4 − gG2 (1 − rG3 ) + rG1 G2 G4 − gG2 (1 − rG3 ) (3.75) Now, with Equations 3.74 and 3.75, all node voltages are known and so all branch variables may be computed explicitly. As was the case for the circuit in Figure 3.26, it is also possible to apply the simple node analysis described in Subsection 3.3 to the circuit in Figure 3.28. However, for the latter circuit, the savings in time is not as great because some effort and thought is needed to express i and v explicitly in terms of e1 and e2 . Furthermore, since these expressions can be obtained in several different ways, the simple analysis becomes somewhat ad hoc when applied to the circuit in Figure 3.28. To begin the simple node analysis of the circuit in Figure 3.28, we express i and v explicitly in terms of e1 and e2 . The ability to do so will be needed to carry out the spirit of Step 3. From the definition of v in Figure 3.28, it is apparent that v = e1 − V − ri. (3.76) Thus, v can easily be expressed explicitly in terms of e1 and e2 once i is so expressed. One relatively convenient way to express i explicitly in terms of e1 and e2 is to combine KCL applied at Nodes 1, 3, and 4. This results in i = I + G2 (e2 − e1 ) + G3 (e2 − V). (3.77) The first term on the right-hand side of Equation 3.77 is the current through the independent current source, and the second term on the right-hand side is the current through the resistor labeled G2 . These two currents combine at Node 1, and their sum exits Node 1 through the resistor labeled G1 . Finally, the combined current passes through Node 4 and the CCVS, before entering Node 3. At Node 3, the combined current also combines with the current through the resistor labeled G3 , and together they exit Node 3 as i. The last term on the right-hand side of Equation 3.77 is the current through the resistor labeled G3 . Thus, Equation 3.77 does express KCL applied to Nodes 1, 3, and 4. Finally, the substitution of Equation 3.77 into Equation 3.76 yields v = e1 − V − r (I + G2 (e2 − e1 ) + G3 (e2 − V)), (3.78) which expresses v explicitly in terms of e1 and e2 . Next, we apply the simple node method, beginning with Step 3, yielding 0 = G1 v + G2 (e1 − e2 ) − I, 145d (3.79) . for Node 1 and 0 = I + G2 (e2 − e1 ) + G3 (e2 − V ) + G4 e2 − g v (3.80) for Node 2. At this point Equations 3.79 and 3.80 still contain v. However, upon substitution of Equation 3.78, they can be rewritten as e1 G4 + (1 + rg)(G2 + G3 ) e2 −G2 − g − rgG2 G1 (1 − rG3 ) 1 + rG1 I . = V −1 − rg G3 (1 + rg) − g G1 + G2 + rG1 G2 −G2 − rG1 (G2 + G3 ) (3.81) Finally, following Step 4, Equation 3.81 can be solved to yield e1 = e2 G3 (1 + rg) + G4 (1 + rG1 ) g − G1 I G1 G2 + G1 G3 + G2 G3 − gG2 (1 − rG3 ) V − G2 G4 − rG1 G3 G4 − gG2 (1 − rG3 ) + rG1 G2 G4 − gG2 (1 − rG3 ) , (3.82) which is identical to Equation 3.75, as it should be. The main point here is that while the application of the simple node analysis described in Section 3.3 to circuits containing dependent sources can result in less work, it also generally becomes less structured. This is because, as part of the analysis, it is necessary to determine the variables that control the dependent sources explicitly in terms of the unknown node voltages before the node analysis is actually completed. It may not always be obvious how to do this in a simple way. For this reason, when it is necessary to carry out a well-structured node analysis, such as when the analysis is to be computerized, then the node analysis presented in this subsection is preferred. 145e 3.3.4 T H E C O N D U C T A N C E A N D S O U R C E M A T R I C E S * As we saw earlier in Equation 3.27, when a resistive circuit is linear (that is, when its resistors and dependent sources are all linear), the equations resulting from Step 3 of a node analysis can be formulated as a matrix equation, which takes the form Ḡ ē = S̄ s̄. (3.83) Here, ē is a vector of the unknown node voltages, s̄ is a vector of the known independent source amplitudes, and Ḡ and S̄ are known matrices, referred to here as the conductance and source matrices, respectively. Examples of such equations can be seen in Equations 3.27 and 3.66. As previewed in the discussion following Equation 3.27, the matrices Ḡ and S̄ have a very special structure. This structure allows us to skip the details of Step 3 of a node analysis, and derive the two matrices directly from the topology of the circuit. This also facilitates the computerization of a node analysis. Alternatively, the special structure of the two matrices can be used to check our work during Step 3. For simplicity, in this subsection we will examine the structure of Ḡ and S̄ that arises from circuits that contain neither floating voltage sources nor dependent sources. However, it is possible to extend our observations to accommodate these sources as well. The special structure of Ḡ and S̄ can be exposed by studying the partial circuit shown in Figure 3.30. By the end of Step 3 of a node analysis, one expression of KCL has been derived in terms of the unknown node voltages for each node having an unknown node voltage. In the case of the partial circuit in Node 1 e1 G1 I e2 e3 G2 F I G U R E 3.30 A partial circuit. Node 3 Node 2 G3 V + V - 145f Figure 3.30, the corresponding expression of KCL for Node 3 is G1 (e3 − e1 ) + G2 (e3 − e2 ) + G3 (e3 − V ) − I = 0. (3.84) In writing Equation 3.84, KCL has been taken to state that the sum of the currents exiting a node must vanish. Next, we rearrange Equation 3.84 as −G1 e1 − G2 e2 + (G1 + G2 + G3 )e3 = G3 V + I. (3.85) By writing KCL as in Equation 3.85, the special structure of the expression becomes apparent. For example, the conductance of each resistor connected to Node 3 contributes positively to the coefficient of e3 , and negatively to the coefficient of the node voltage at the other end of the resistor. This is because e3 acts to drive currents out from Node 3, while the other node voltages act to drive currents in to Node 3. The same observation holds for the coefficient of the grounded independent voltage source, except for a change in sign due to the fact that the corresponding term is moved to the opposite side of the equal sign. We also see that the current source enters positively into Equation 3.85, once its term is moved to the opposite side of the equal sign, since it sources current into Node 3. Now consider assembling Equation 3.85, and its counterparts from the other nodes in the circuit, in the form of Equation 3.83. Each expression of KCL becomes a row within Equation 3.83. For the sake of discussion, let us assume that these rows are ordered according to the number of the node for which they are written, and further that the node voltages in ē are listed in order of their corresponding node numbers. In this case, Equation 3.85 enters into Equation 3.83 as . . . −G1 . . . −G2 G1 + G 2 + G 3 0 e1 . e2 . e3 . · · · e4 = 1 G3 . . . . . . I V · · · . . . . (3.86) Thus, we see that Ḡ is a matrix of conductances. A diagonal element at the position [m, m] in Ḡ is the sum of the conductances connected Node m. An off-diagonal element at the position [m, n] in Ḡ, m = n, is the negative of the conductance connecting Nodes m and n. This is true even for the zero elements within Ḡ since a zero conductance indicates the absence of a resistor, 145g or no connection. As a consequence of this structure, Ḡ is symmetric about its main diagonal, at least in the absence of dependent sources. Similarly, the matrix S̄ contains the coefficients of the sources. For each independent current source, there will be a +1 in its column in S̄ at Row m if the source enters Node m, a −1 if the source exits Node m, and a 0 otherwise. For each grounded independent voltage source, the conductance connecting it to Node m will appear in Row m of its column in S̄, including zeros to indicate the absence of a connecting resistor. Again, the structure of Ḡ and S̄ can be seen in Equations 3.27 and 3.66. Consider, for example, the matrices in Equation 3.27. The [1,1] element of Ḡ is G1 + G2 + G3 because the resistors labeled G1 , G2 , and G3 are all connected to Node 1. Similarly, the [2,2] element in Ḡ is G3 +G4 because the resistors labeled G3 and G4 are both connected to Node 2. The [1,2] and [2,1] elements in Ḡ are both −G3 since G3 connects Nodes 1 and 2. Since the voltage source connects to Node 1 through the resistor labeled G1 , but does not connect to Node 2, the [1,1] element of S̄ is G1 and the [2,1] element is zero. Similarly, since the current source enters Node 2, but does not connect to Node 1, the [2,2] element of S̄ is +1 and the [1,2] element is zero. Thus, the matrices in Equation 3.27 could have been derived by inspection of the circuit topology only. 145h 3.4 L O O P M E T H O D * We have already seen several examples of a complementary relationship between voltage and current, so it should come as no surprise that there is a simplified analysis method based on an astute choice of current variables that closely parallels the method in the preceding section. Here we choose current variables that flow in loops, that is, in closed paths. By this definition, the current flowing into any node will always be identically equal to the current flowing out, so KCL is identically satisfied. As in Chapter 2, we continue to define loop currents until every element is traversed by at least one loop current. To illustrate, let us define a set of current loops for the circuit we previously analyzed, as in Figure 3.31. KCL at Node 1 gives (i1 + i2 ) − i1 − i2 = 0 (3.87) which is identically zero for all values of i. Thus because KCL is automatically satisfied for this choice of current variables, we have to write only KVL and the constituent relations. Combining these in one step, we obtain −V + (i1 + i2 )R1 + i1 R2 = 0 (3.88) −i1 R2 + i2 R3 + (i2 + I )R4 = 0. (3.89) Now rewrite to place the source terms on the left: V = i1 (R1 + R2 ) + i2 R1 (3.90) IR4 = i1 R2 − i2 (R3 + R4 ). (3.91) i2 R1 + V - R3 Node 1 R2 Node 2 R4 I I F I G U R E 3.31 Loop currents. i1 145i By Cramer’s Rule, i1 = V(R3 + R4 ) + IR4 R1 (R1 + R2 )(R3 + R4 ) + R1 R2 . (3.92) The voltage across R2 can now be found from Equation 3.92 and e1 = i1 R2 . (3.93) Equations 3.92 and 3.93 can be reduced to Equation 3.8 by simple algebra. 145j e x a m p l e 3 . 13 l o o p m e t h o d Let us use the loop method to analyze the circuit depicted in Figure 3.18 in our previous example. Figure 3.32 shows our choice of the loops for this circuit. The corresponding loop equations are −V + i1 R1 + (i1 − i2 )R2 + (i1 − i3 )R4 = 0 (3.94) (i2 − i1 )R2 + i2 R3 + (i2 − i3 )R6 = 0 (3.95) (i3 − i1 )R4 + (i3 − i2 )R6 + i3 R5 = 0. (3.96) By rearranging the terms into matrix form, we obtain R1 + R2 + R4 −R2 −R4 i1 V −R4 −R6 i2 = 0 . 0 R4 + R5 + R6 i3 −R2 R2 + R3 + R6 −R6 Assigning the same values to the voltage source and resistors, V=5V R1 = 50 (a) R1 R2 i2 i1 R3 F I G U R E 3.32 Circuit with properly assigned current loops. + (b) V - R4 R6 i3 (c) (d) R5 145k R2 = 100 R3 = 100 R4 = 75 R5 = 75 R6 = 150 we obtain 225 −100 −75 −100 350 −150 i1 5 −75 −150 i2 = 0 . 0 300 i3 Solving, we have i1 = 2/55 A, i2 = 1/55 A, and i3 = 1/55 A. As a sanity check, the current flowing through R6 is i2 − i3 = 0, as desired. 145l e x a m p l e 3 . 17 s u p e r p o s i t i o n a p p l i e d t o a b e e h i v e n e t w o r k Superposition and a bit of creativity can also be used to solve more complicated resistive networks. Figure 3.45 shows a resistive network containing an infinite plane of resistors in a beehive shape. Each of the resistors have a resistance value R. What is the equivalent resistance Reqv when looking into port A-B? One of the key ideas of this problem is to properly choose a reference node or a ground node for measuring voltages of the internal nodes in the network. Referring to Figure 3.46, we take ground at infinity. Then, we introduce a current IP into node A using a current source, and draw IP out of node B using another current source. If we can compute the resulting voltage VP between nodes A and B, then we can obtain the effective resistance between A and B as Reqv = VP IP . Our circuit has two sources, one injecting a current IP into the network, and the other drawing a current IP out of the network. We will determine the voltage VP using superposition by adding the voltages across A and B resulting from each of the current sources acting alone. Figure 3.47 shows the circuit with the current source at B A B F I G U R E 3.45 An infinite plane resistive network. Each resistor has a resistance value R. 153a IP A + VP - F I G U R E 3.46 Introducing ground into the network. B IP IP i3 F I G U R E 3.47 The circuit with only the current source at A being applied. 153b i2 A i1 + VP1 - B A i5 i4 + VP2 - F I G U R E 3.48 The circuit with only the current source at B being applied. B i6 IP turned off, and Figure 3.48 shows the circuit with the current source at A turned off. Let VP1 be the voltage across A and B when the current source at A acts alone, and let VP2 be the voltage across A and B when the current source at B acts alone. By superposition, we know that VP = VP1 + VP2 . Referring to Figure 3.47, the current IP injected into node A will split evenly into three currents, i1 , i2 , and i3 . We know that i1 = i2 = i3 because the injected current faces a symmetric situation in each of the three directions. Since, by KCL, IP = i1 + i2 + i3 , we can write i1 = i2 = i3 = IP 3 . 153c Since the current through the resistor connecting nodes A and B is i1 = IP /3 and since the resistance value of the resistor is R, we can write VP1 = Ri1 = R IP . 3 Similarly, referring to Figure 3.48, the current IP drawn out of node B comprises three components i4 , i5 , and i6 , where i4 = i5 = i6 . Since, by KCL, IP = i4 + i5 + i6 , we can write IP i4 = i5 = i6 = . 3 And in like manner, since the current through the resistor connecting nodes A and B is i4 = IP /3, and since the resistance value of the resistor is R, we can write VP2 = Ri4 = R IP . 3 Composing the expressions for VP1 and VP2 we get VP = VP1 + VP2 = 2IP 3 Therefore, Reqv = 153d VP IP = 2 3 R. R. e x a m p l e 4. 5 n o d e m e t h o d This example uses the device shown in Figure 4.5. Recall that this device is characterized by the following device equation: iD = 0.1vD2 for vD ≥ 0, (4.17) + V - iD + v1 D1 + v2 iD is given to be 0 for vD < 0. Referring to the series connected nonlinear devices in Figure 4.14, determine iD , v1 , and v2 , given that V = 2 V. We will use the node method to solve this problem. We first select a ground node and label node voltages as shown in Figure 4.15. We have one unknown node voltage v2 . D2 F I G U R E 4.14 Nonlinear devices connected in series. Next, we write KCL for the node with the unknown node voltage. Recall that the KCL equations in the node method are written directly in terms of the node voltages. Accordingly, 0.1v22 = 0.1(V − v2 ) 2 . The term on the left-hand side is the current through device D2. Similarly, the term on the right-hand side is the current through device D1. Solving, we get v2 = V 2 . Given that V = 2V, we get v2 = 1V. We now obtain the remaining voltages and currents by applying KVL and the relevant device laws. Thus, V iD + V - D1 v2 D2 v1 = V − v2 = 1 V F I G U R E 4.15 Circuit with node voltages labeled. and iD = 0.1v22 = 0.1 A. Notice that we could have also solved the circuit intuitively by realizing that the same current flows through two identical nonlinear devices. Thus, the same voltage must drop across both. In other words, v1 = v2 . Furthermore, by KVL 2 V = v1 + v2 . Or, v1 = v2 = 1 V. 201a e x a m p l e 4.8 making simplifying assumptions Sometimes, there are a few special cases of interest that can be solved analytically by making appropriate simplifying assumptions. The circuit in Figure 4.19 is one such example. Here for variety, we will solve the circuit by a direct application of KVL and KCL. KVL around the path containing the voltage sources and the diodes yields −2E + vD1 − vD2 = 0 (4.28) and KCL at the junction of the two diodes gives iD1 + iD2 = IA . (4.29) These two equations, together with the equations for the diodes of the form of Equation 4.1, can be solved for the diode currents, assuming identical diodes. Now, if we assume that the diode voltages are always positive enough to make the −1 term in the diode equation negligible (for Equation 4.1, true within less than one percent for all vD larger than 125 mV), then iD1 becomes iD1 = IA −2E/V TH 1+e . (4.30) We can obtain this equation by following these steps. First, substitute in Equation 4.28 expressions for vD1 and vD2 in terms of iD1 and iD2 derived from the diode equations (neglecting the −1 term). Second, obtain iD2 in terms of iD1 from this equation, substitute in Equation 4.29, and simplify to get Equation 4.30. The diode current is thus a hyperbolic tangent function of the voltage E, except for an offset of IA /2. iD1 + + E - vD1 IA - F I G U R E 4.19 Hyperbolic tangent generator. + E - vD2 + iD2 203a e x a m p l e 4. 9 voltage-controlled nonlinear r e s i s t o r Let us now determine vO as a function of vI for the circuit in Figure 2.71 when RX = f (vI ) = Ro vI − 1 V . where Ro = 10 kV. We have, vO = V =V =V RX RL + RX Ro v vI −1 Ro RL + v −1 v I Ro RL (vI − 1 V ) + Ro . Substituting, Ro = 10 kV and RL = 10 k, vO = V = 10 kV 10 k(vI − 1 V ) + 10 kV V vI V = V 2 = 2 V. 203b e x a m p l e 4.13 half-wave rectifier re-examined As another example of piecewise linear analysis, we re-examine the half-wave rectifier circuit for a sinusoidal input previously analyzed using graphical analysis in Section 4.10. This time around, we will use a piecewise linear model for the diode, but use the same graphical approach of Section 4.10. Thus we start with the same circuit topology as in Figure 4.21a, except that the diode is modeled using its piecewise linear approximation, the ideal diode, as shown in Figure 4.32a. Assuming as before a ten-volt sinusoidal input voltage, as might be typical in power supplies, we draw a succession of load lines on the piecewise linear characteristics, Figure 4.32b, for representative values of the input wave, and plot the output voltage point by point. The desired output voltage is vR , which in the graph is the horizontal E = E o cos ( ωt ) + - R + vR - (a) iD Slope = -1/R F I G U R E 4.32 Half-wave rectifier: ideal diode piecewise linear analysis. vR (b) E vD vR (c) t 214a distance from the operation point intersection to the input voltage. The resulting output wave is shown in Figure 4.32c. Comparison with the previous analysis, Section 4.10 and Figure 4.21, indicates that at least for this problem, the simple ‘‘ideal diode’’ approximation yields a reasonably accurate answer. As one would expect, the error mainly derives from the neglect of the 0.6-V drop across the diode. Clearly, the error would be more objectionable if the input sinusoid had been of one volt peak rather than 10 volts. 214b 4.4.1 I M P R O V E D P I E C E W I S E L I N E A R M O D E L S FOR NONLINEAR ELEMENTS * The accuracy of the results of a piecewise liner analysis depends on the accuracy of the model used. In this section, we will discuss the process of creating more precise models of nonlinear elements when increased accuracy is desired. To illustrate the process, let us use the diode as an example of a nonlinear element. Thus far, we used the simple, ideal diode model. It is obvious from the preceding example that the major effect in the model is when the voltage vD across the diode is positive, and above about 0.6 V. Substantial improvement can be made by adding a 0.6-V source in series with the ideal diode, as shown in Figure 4.33a. The corresponding i v characteristic for the improved piecewise linear model is shown in Figure 4.33b. Let us work a simple example using this piecewise linear model. + iD iD vD vD + 0.6 V 0.6 V (b) (a) F I G U R E 4.33 Improved piecewise linear diode models. + iD iD Slope + vD 0.6 V - vD 0.6 V Rd (c) 214c (d) 1 = ----Rd e x a m p l e 4. 14 a n o t h e r e x a m p l e u s i n g p i e c e w i s e l i n e a r m o d e l i n g Let us rework the example containing a voltage source, resistor, and diode in Figure 4.16 using the piecewise linear model for the diode from Figure 4.33b. The behavior of this model, comprising an ideal diode in series with a voltage source, can also be summarized in two statements: Diode ON (vertical segment): vD = 0.6 V for iD > 0 Diode OFF (horizontal segment): iD = 0 for vD < 0.6 V (4.47) Let us determine iD for E = 3 V and E = −5 V, given that R = 500 . According to the piecewise linear method, we will focus on one straight-line segment at a time, using linear analysis within each segment. Vertical segment When iD and vD are in the vertical segment of their characteristic, the circuit shown in Figure 4.34b results, and we can write iD = E − 0.6 V R . (4.48) Horizontal segment Figure 4.34c shows the corresponding circuit when the diode is operating as an open circuit. In this segment, iD = 0. (4.49) Combining the results Intuition tells us that the vertical segment applies when E > 0.6 V (the diode turns on) and the horizontal segment applies otherwise (diode is off). Thus, when E = 3 V, Equation 4.48 applies, and iD = E − 0.6 V R = 3 − 0.6 500 = 4.8 mA. Comparing to Equation 4.40, notice that the value of iD predicted by this improved model is slightly lower than that predicted by the ideal diode model. The ideal diode model did not account for the 0.6-V drop across the diode, and so overestimated the current. Equation 4.49 applies when E = −5 V, so iD = 0. 214d + vR iD R + + E - vD 0.6 V - (a) Complete model vR + iD R F I G U R E 4.34 Piecewise linear analysis in the vertical and horizontal straight-line segments using the diode model containing a voltage source. + E - + vD 0.6 V (b) Vertical segment + vR iD R + E - + 0.6 V vD - (c) Horizontal segment Further improvement in accuracy can be realized by adding a series resistor Rd of suitable value to the ideal diode and voltage source, as shown in Figure 4.33c. The specific choice of resistor value depends on the application; one should strive to make the characteristic match over the range of diode current expected in the specific circuit (see Figure 4.35). We will illustrate the use of this model in an example. More examples using these and other more complicated piecewise models will appear throughout the book, and specifically in Chapters 7 and 16. 214e t h e d i o d e r e s i s t a n c e Choose values for Rd for the piecewise linear diode model in Figure 4.33c assuming that the resistance must provide a reasonable match for currents up to 0.4 A and 1 A. Assume VTH = 0.025 V and Is = 10−12 A. e x a m p l e 4. 15 iD (A) Figure 4.35 plots the v i characteristics for the diode. The figure shows that the resistance value Rd1 = 0.1 provides a good match for the diode v i characteristics up to 1 A, while the resistance value Rd2 = 0.2 provides a better match in the smaller current range from zero to 0.4 A. 1.0 0.9 0.8 Slope = 10, Rd1 = 0.1 Ω 0.7 0.6 0.5 0.4 Slope = 5, Rd2 = 0.2 Ω 0.3 F I G U R E 4.35 Choosing a value of the resistance in the piecewise linear diode model. 0.2 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 vD (V) 214f e x a m p l e 4.16 a more complicated piecewise l i n e a r m o d e l Let us further rework the previous example using the piecewise linear model for the diode from Figure 4.33c. The behavior of this model, comprising an ideal diode in series with a voltage source and a resistor, can be summarized in two statements: Diode ON (vertical segment): vD = 0.6 V + iD Rd for iD > 0. Diode OFF (horizontal segment): iD = 0 for vD < 0.6 V. (4.50) Again, let us determine iD for E = 3 V and E = −5 V, given that R = 500 and Rd = 10 . Vertical segment When iD and vD are in the vertical segment of their characteristic, the circuit shown in Figure 4.36b results, and we can write iD = E − 0.6 V R + Rd . (4.51) Horizontal segment Figure 4.24c shows the corresponding circuit when the diode is operating as an open circuit. In this segment, iD = 0. (4.52) Combining the results For E = 3 V, Equation 4.51 applies, and so iD = E − 0.6 V R + Rd = 3 − 0.6 V 500 + 10 = 4.7 mA. Equation 4.52 applies when E = −5 V, so iD = 0. As illustrated using the diode, increasingly better fits to an actual nonlinear device characteristic can be obtained by introducing more and more ideal elements. For example, for the diode, increasingly better fits to the actual diode characteristic can be obtained by introducing more and more ideal diodes, batteries, and resistors. But again a price is paid; increased accuracy of the model brings increased complexity. The proper compromise between simplicity and accuracy is not always obvious. Start with the simplest model, then add complexity to see if the solution changes in major ways. 214g + vR iD R + E - + vD 0.6 V Rd - (a) Complete model vR + iD R + E - + vD 0.6 V Rd - F I G U R E 4.36 Piecewise linear analysis in the vertical and horizontal straight-line segments using the diode model containing a voltage source and a resistor. (b) Vertical segment + vR iD R + E - + vD 0.6 V Rd (c) Horizontal segment 214h e x a m p l e 4.21 d i o d e r e g u l a t o r To further illustrate the use of incremental analysis, we examine the diode circuit shown in Figure 4.45, another crude form of voltage regulator that is slightly better than our previous regulator. As before, we assume that the supposedly DC source supplying the circuit in reality has 5 volts of DC with 50 millivolts of AC superimposed. The regulator is designed to reduce this unwanted AC component relative to the DC. To understand how the circuit operates, first draw the DC subcircuit to determine ID and VO , the operating point variables of the circuit. We will use the piecewise linear analysis method (based on the piecewise linear model of the diode shown in Figure 4.33c) to determine the operating point variables. Accordingly, Figure 4.45b shows the DC subcircuit in which each diode has been replaced with its piecewise linear model comprising an ideal diode, a 0.6-V voltage source and a resistor of value Rd . By inspection From Figure 4.45b, ID = 5V − 1.8V R + 3Rd . (4.84) For R = 1000 and Rd = 10 , a reasonable value for diode currents in the 1- to 10-mA range, ID = 3.2 = 3.1 mA. (4.85) 1030 Next, draw the incremental subcircuit, as shown in Figure 4.45c. Here we will use the accurate v i relation for the diode from Equation 4.1 to compute the value of R + Total source + 50 mV AC vO + - 5 V DC R (a) + + - F I G U R E 4.45 Diode regulator. 50 mV AC + 0 + - 5 V DC (b) DC subcircuit 228a + - 1.8 V VO 3 Rd - ∆vo 3 rd R 0 - (c) Incremental AC subcircuit the incremental diode resistance rd . This incremental resistance can be derived using Equation 4.75, in which f is the diode v i relation. We have also seen that the application of Equation 4.75 for the diode v i relation results in Equation 4.74, which directly yields the value of rd as rd = 25 mV 3.1 mA 8.1 . (4.86) Now, from Figure 4.45c, we can write an expression for the small signal AC output vo = 50 3rd 3rd + R = 50 24.3 24.3 + 1000 = 1.19 mV AC. (4.87) (From Equation 4.66, with vo equal to 1.19 mV we expect an error of about 2% in the neglect of higher-order terms in the incremental analysis.) The total DC output voltage of the regular can be found from the DC subcircuit, Figure 4.45b, VO = 1.8 + 3ID Rd (4.88) = 1.8 + 3 × 3.1 × 10 −3 × 10 = 1.89 V. (4.89) The fractional ripple at the input, fractional ripple = 50 × 10−3 5 = 10−2 (4.90) and at the output, fractional ripple = 1.19 × 10−3 1.89 10−3 (4.91) so the ripple has been reduced relative to the DC by a factor of 10. 228b e x a m p l e 4.22 s m a l l signal analysis using a p i e c e w i s e l i n e a r d i o d e m o d e l In the diode regulator example, we used the piecewise linear model for the diode when conducting the DC operating point analysis, but reverted to the accurate diode equation when computing the small signal resistance. This example will illustrate that small signal analysis of nonlinear devices can also be carried out by using their piecewise linear models for both the DC operating point analysis and in computing the small signal device resistance. Of course, the accuracy of the results will depend on the fidelity of the piecewise linear model used for the nonlinear device. The example will be based on the simple diode-resistor circuit shown in Figure 4.46. Let us suppose we are interested in the small signal values of the output voltage and the diode current for a 50-mV incremental input. As promised, throughout this example, we will use the piecewise linear model for the diode illustrated in Figures 4.33a and 4.33b. We start by drawing the DC subcircuit to determine the operating point variables ID , VO as shown in Figure 4.46b. By inspection, we can write ID = 5 − 0.6 R . For R = 1000 , ID = 4.4 mA and VO = 0.6 V. R + - + iD 50 mV vO + - 5V R F I G U R E 4.46 A simple diode-resistor circuit. (a) Total circuit id + - rd = 0 R ID 0 + - + VO 5V 0.6 V (b) DC subcircuit 228c + 50 mV 0 (c) Incremental subcircuit vO - Next, we draw the incremental subcircuit for the operating point given by ID = 4.4 mA and VO = 0.6 V. Since we chose to use the piecewise linear model for the diode throughout our analysis, we must derive rd based on this model. Since ID > 0, notice that the diode is operating in the vertical segment of the piecewise linear v i curve shown in Figure 4.33b. Since the reciprocal of the slope of this curve segment is zero, rd is also zero. In other words, the ideal diode looks like a short circuit for incremental changes in the current. Figure 4.46c shows the corresponding incremental subcircuit. From Figure 4.46c, it is easy to see that the incremental change in the output voltage for the 50-mV change in the input voltage is simply vo = 0. Similarly, the incremental change in the current is given by id = 50 mV R = 50 µA. 228d e x a m p l e 5 .14 simplifying another logic e x p r e s s i o n (a) Find the minimum sum-of-products representation for the boolean expression in Equation 5.8, namely Output = A B C D + A B C D + A B C D. (5.30) (b) Further, show that the expression in Equation 5.30 is equivalent to the logic expression in the caption of Table 5.7, namely AB + C + D. As directed in part (a), we will simplify the expression in Equation 5.30 as follows: Output = A B C D + A B C D + A B C D =ABCD+ABCD+ABCD+ABCD = (A B C D + A B C D) + (A B C D + A B C D) = A C D(B + B) + B C D (A + A) =ACD·1+BCD·1 = A C D + B C D. (5.31) To answer part (b), recall that we have previously shown that AB + C + D can be simplified to A C D + B C D (see Equation 5.29). Since the expressions in Equations 5.29 and 5.31 are identical, it follows that AB + C + D and A B C D + A B C D + A B C D are equivalent. 267a e x a m p l e 5 . 16 y e t a n o t h e r i m p l e m e n t a t i o n u s i n g n o r s Let us derive an implementation based on two-input NOR gates for the function AB + C + D. Assume that both the true and complement version of each of the inputs is available: AB + C + D = A B + (C + D) (5.35) =A+B+C+D+C+D (5.36) = ((A + B) + ((C + D) + C + D)). (5.37) Implementing each of the expressions within parentheses using two-input NOR gates, we get the circuit shown in Figure 5.24. Notice that the algebraic simplification process was quite cumbersome. We can actually perform the same transformation directly on a gate-level circuit with greater ease. Figure 5.25 shows how the original circuit for AB + C + D from one of the implementations in Figure 5.18 can be transformed into a two-input NOR implementation. The transformations exploit the fact that two inverters (or circles) in series cancel each other. A B F I G U R E 5.24 NOR implementation of AB + C + D. C D A B A B C D C D F I G U R E 5.25 NOR transformations for AB + C + D. A B A B C D C D 267b 6.11 A C T I V E P U L L U P S Large valued resistors are difficult to fabricate in VLSI technology. For example, R2 is usually on the order of a few tens of ohms for polysilicon, few hundreds of ohms for diffusion, and few hundredths of an ohm for metal. Fabricating a 10-k resistor using polysilicon would require an area hundreds of times larger than that of a minimum sized transistor. Fortunately, MOSFETs themselves make good high-valued resistors for the same area, the resistance RON of a minimum sized MOSFET is significantly higher than that of a resistance made out of other materials, such as polysilicon. Figure 6.55 shows an inverter constructed out of MOSFETs with Mpu serving as an active pullup. The pullup MOSFET has its drain tied to the power supply connection, and thus the drain has a voltage VS applied with respect to ground. To keep the pullup MOSFET permanently in its ON state, its gate is connected to a second voltage VA , where VA is at least one threshold voltage higher that the supply voltage. In other words, VA > VS + VT . VS VA Mpu W ----- L pu vOUT Mpd vIN F I G U R E 6.55 Logic gate with active pullup. In the circuit, VA > VS + VT , so that the pullup MOSFET is always in its ON state. W ----- L pd VS VS RONpu RONpu vOUT vOUT vIN = High 321a RONpd vIN = Low Let the W/L ratios of the pullup and the pulldown MOSFETs be (W/L)pu and (W/L)pd , respectively. Let the corresponding ON-state resistances (according to the SR model) be RONpu and RONpd . We also know that RON ∝ L W where the constant of proportionality is Rn .25 Let us now choose the respective (W/L) ratios so that the inverter satisfies the relationship derived in Equation 6.6, and repeated below for convenience: VS RON RON + RL < VT This relationship between the output low voltage of the inverter and the threshold voltage of a MOSFET is necessary for the inverter to be able to drive the MOSFET in another inverter into its OFF state. In the preceding equation, RL is the resistance of the pullup device, and RON is the resistance of the pulldown device. With both an active pullup and an active pulldown, 1 VT > VS 1+ > VS RL RON 1 (L/W)pu 1+ (L/W)pd (6.12) (6.13) where we have substituted the L/W ratios in place of the resistance values. 25. As mentioned earlier, the MOSFET displays resistive behavior between its drain and its source only when the drain voltage is much smaller than the gate voltage (specifically, vDS vGS − VT ). Furthermore, the resistance Rn , and therefore RON , depends on the value of the applied gate voltage. We will see more appropriate models for MOSFETs in other regions of operation in later chapters. But for now, let us go ahead and use the SR model with a single value for Rn to analyze the active pullup. 321b For our typical parameters: VS = 5 V and VT = 1 V. Therefore, we get 5 1 <1 (L/W)pu 1+ (L/W)pd (6.14) 5<1+ 4< L W L W L W L W pu pu . (6.15) pd (6.16) pd In other words, we can choose the size of the pullup so its (L/W) ratio is four times that of the pulldown. 321c For a 5-V supply voltage, suppose our static discipline prescribes a VOL = 0.5 V. How do we size the pullup MOSFET in Figure 6.56 relative to the pulldown MOSFET to meet the valid output low threshold? VS e x a m p l e 6. 9 s i z i n g p u l l u p d e v i c e s VA When the pulldown device is on, we know that the output voltage is given by vOUT = VS RONpd RONpd + RONpu vOUT vIN . To satisfy the static discipline, we must have VOL > vOUT when the input is high. Recall that the on-state resistance is proportional to the ratio of the device gate length L and its width W. Thus we have, VOL > vOUT L RONpd ∝ ----- W pd F I G U R E 6.56 An inverter with an active pullup. (6.17) RONpd > VS RONpd + RONpu L/W pd > VS L/W pd + L/W pu >5 L RONpu ∝ ----- W pu 1 . L/W pu 1+ L/W pd (6.18) (6.19) (6.20) (L/W)pu > 9 we will satisfy the static (L/W)pd discipline. In other words, if both devices are of the same width W, the pullup device must be sized so its length is nine times that of the pulldown device. For VOL = 0.5 V, it is easy to see that if we choose 321d e x a m p l e 6.10 c o m b i n a t i o n a l l o g i c u s i n g m o s f e t s w i t c h e s Let us now rework some of our previous examples using all-MOSFET designs and the SR model. Assume that we need to design our gates such that they satisfy a static discipline with the low output voltage threshold VOL = VT− V, where VT is given to be 1 V. Let us design all-MOSFET circuits and let us attempt to make them as small as possible. Assume that the area of the circuit is proportional to the area of the gates (W × L) of the individual MOSFETs. Let us also compute the power dissipated by the circuits. Assume that Rn for the MOSFETs is 1 k. Let us first consider the expression: AB + C + D. Figure 6.57 shows a compound gate comprising only MOSFETs that implements this expression. This gate design replaces the load resistor in Figure 6.23 with an active pullup. Our task is to determine the sizes of both the pulldown and the pullup MOSFETs so this gate satisfies the static discipline for VOL = 1− V. Note that the gate must satisfy the static discipline for any combination of inputs. As we have seen before, the key issue in designing a NMOS logic gate is to choose the relative values of the pullup and the pulldown resistances so that even the highest value for the gate’s output low voltage satisfies the VOL constraint. Since we are asked to design the circuit that occupies the least area, and there are more pulldown transistors than pullups, let us start by choosing minimum-sized transistors ((L/W )pd = 1) for the pulldown circuit. Therefore the on resistance of an individual pulldown MOSFET is RONpd = Rn L W = Rn . pd The highest value for the output low voltage occurs when the pulldown circuit has its highest resistance. Notice that the pulldown circuit has its largest on-state resistance for an output low when A and B are on, and C and D are off. This largest pulldown resistance is given by the sum of the on-state resistances of the MOSFETs with the A VS W - ---L pu VA F I G U R E 6.57 Transistor-level implementation of AB + C + D using an active pullup. In the circuit, VA > VS + VT , so that the active pullup is in its ON state at all times. 321e OUT A B C D W - ---L pd and B inputs. That is, Rpdmax = 2RONpd = 2Rn . To satisfy the static discipline, the output voltage of the gate for a logical 0 must be less than VOL for any combination of inputs that can result in a logical 0 at the gate’s output. In other words, the highest value for the low output voltage of the gate must be less than VOL , which is given to be VT− . Since the output voltage of the gate is given by VS RONpd RONpu + RONpd , We can write the following constraint so that the gate satisfies the static discipline for VOL = VT− : VT > VS > VS RONpd RONpu + RONpd 2Rn RONpu + 2Rn > VS Rn > VS L W 2Rn L + 2Rn W pu 2 . +2 pu For VS = 5 V and VT = 1 V, the previous constraint simplifies to L > 8. W pu In other words, the L/W ratio of the pullup must be chosen to be greater than 8. Thus the resistance of the pullup is 8Rn . Let us now compute the power dissipated by the circuit. The maximum amount of power is dissipated when the resistance of the pulldown circuit is a minimum. This happens when A = 1, B = 1, C = 1, and D = 1. Recalling that the resistances of each of the pulldowns is Rn and that of the pullup is 8Rn , Pmax = V2S 8Rn + 2Rn Rn Rn = 3 × 10−3 W. 321f We can also design a circuit for the expression (A + B)CD in like manner as depicted in Figure 6.58. In this design, the maximum on-state resistance of the pulldown circuit for an output low is achieved when both C and D is high and only one of A and B is high. The corresponding maximum on-state resistance of the pulldown (assuming minimum sized transistors) is 3Rn . VS W ---- L pu VA Out A B W ---- L pd C As before, the pullup must be designed to have four times the resistance of the pulldown. Since the pulldown circuit has resistance 3Rn , the L/W ratio of the pullup transistor must be chosen as (L/W )pu = 4 × (L/W )pd = 4 × 3 = 12. We can also calculate the maximum power dissipated by computing the minimum resistance in the current path. The minimum resistance occurs when all inputs are high. Thus the total resistance in the current path is given by Rpu + Rpd = 12Rn + 2Rn + (Rn Rn ) = 14.5Rn . D The corresponding power dissipation is26 F I G U R E 6.58 Transistor-level implementation of (A + B)CD using an active pullup. In the circuit, VA > VS + VT . Pmax = V2s 14.5Rn = 1.7 × 10−3 W. 26. We note that a milliwatt of power per gate would cause today’s million-gate circuits on a VLSI chip to dissipate a thousand watts of power! Because VLSI chips cannot dissipate more than few tens of watts without esoteric packaging technologies, modern VLSI chips use another form of logic called CMOS involving both n-channel and the complementary p-channel MOSFETs. We will study this technology in Chapter 11. 321g e x a m p l e 7. 18 b e t t e r b j t m o d e l s Since the base-emitter junction of a BJT functions like a diode, we can build more accurate models for the BJT by using more sophisticated models for the BJT’s base-to-emitter diode. Figure 7.61 shows a pair of models for the BJT that provide better accuracy than the ideal-diodevoltage-source model shown in Figure 7.49c. Notice that we are ignoring the presence of the base-to-collector diode (shown in a faint outline form in Figures 7.61b and 7.61c) by assuming that the BJTs are constrained to operate in their active region (that is, we assume vCE > vBE −0.4). In this example, we will use each of these two models to compute vBE , iC , and iE for the BJT in the circuit shown in Figure 7.53. Assume RD = 10 , VTH = 0.025 V, and Is = 10−12 A. First, let us compute the parameters based on the model in Figure 7.61b. We will start by making our calculations assuming that the BJT is operating in its active region, and then verify that the results satisfy the conditions for active region operation. Under active-region operation, we can obtain iC directly from the value of iB as iC = βiB = 1 mA. The emitter current is the sum of the base and collector currents. Thus iE = iC + iB = 1.01 mA. We can now determine vBE by summing the source voltage and the voltage drop across RD as vBE = 0.6 + iE RD = 0.6101 V. This completes our calculations based on the model in Figure 7.61b. To verify that the BJT is operating in its active region, we need to check that the following two conditions are met: iB > 0 and vCE > vBE − 0.4 V. Substituting iB = 0.01 mA, vCE = 5 V, and vBE = 0.6101 V, we can see that both conditions are indeed met. Next, let us compute the parameters based on the model in Figure 7.61c. As with the previous model, we will start by making our calculations assuming that the BJT is operating in its active region, and then verify that the results satisfy the conditions for active region operation. Under active-region operation, we can obtain iC from the value of iB as iC = βiB = 1 mA. The emitter current is the sum of the base and collector currents. Thus iE = iC + iB = 1.01 mA. 381a C C + C iC B iB + B vCE + vBE - iE E - βiB iB + + 0.6 V - vBE - RD iE vCE v BE --------V TH –1 iE - - Otherwise, iC = 0 F I G U R E 7.61 More accurate models for a bipolar junction transistor. iE = I s e vBE E v > v For CE BE – 0.4 V, iC = βiB (a) βiB iB B vCE + + iC iC E - For v CE > v BE – 0.4 V, iC = βiB Otherwise, iC = 0 (c) (b) We can now determine vBE from vBE iE = Is e VTH − 1 . Solving by trial and error, we find that iE = 1.01 mA results in vBE ≈ 0.52 V. This completes our calculations based on the model in Figure 7.61c. The computed values once again confirm that the BJT is operating in its active region. 381b 9.4.1 S I N U S O I D A L I N P U T S * Sinusoidal signals are an important class of inputs to electronic circuits. So, as a first example of specific inputs to the circuits shown in Figures 9.31 through 9.34, consider the special cases of 0 t≤0 I◦ sin(ωt) t > 0 I(t) = V(t) = 0 V◦ sin(ωt) (9.67) t≤0 (9.68) t > 0. Note that both sources are zero for t ≤ 0, but nonzero for t > 0, so that they effectively turn on at t = 0. A sketch of I(t) is shown in Figure 9.35a. To complete the analysis of the circuits, we substitute the corresponding source function from either Equation 9.67 or 9.68 into Equations 9.63 through 9.66 and carry out the indicated integration or differentiation. This results in t≤0 0 v(t) = (9.69) I◦ 1 − cos(ωt) t > 0 ωC I(t) v(t) 2Io -------(b) ωC Io (a) π--ω -Io 2π ---ω-t π--ω 2π ---ω-t v(t)I(t) ωE (t) (c) π--ω F I G U R E 9.35 The current I, the voltage v, the power vI, and the energy wE stored in the capacitor, for the circuit shown in Figure 9.31 given the sinusoidal source current from Equation 9.67. 2I2o ---------2 (d) ω C 2π ---ω-t π--ω 2π ---ω-t 482a for the capacitor circuit shown in Figure 9.31, 0 t≤0 ωCV◦ cos(ωt) t > 0 i(t) = (9.70) for the capacitor circuit shown in Figure 9.32, i(t) = 0 t≤0 V ◦ 1 − cos(ωt) ωL t>0 (9.71) for the inductor circuit shown in Figure 9.33, and v(t) = 0 ωLI◦ cos(ωt) t≤0 (9.72) t>0 for the inductor circuit shown in Figure 9.34. Note that for these equations to make sense, the units of ωC must be conductance and the units of ωL must be resistance; they are. We will encounter these products again in future chapters. A comparison of the circuit inputs given in Equations 9.67 and 9.68 to the circuit responses given in Equations 9.69 through 9.72 shows that the sinusoidal components of the current and voltage in each circuit are π /2 radians out of phase with each other. This is in keeping with the observation that the circuits perform integration or differentiation from current to voltage or voltage to current. In the case of the capacitor circuits, the current leads the voltage because the current must be present first to build up the charge to which voltage is proportional. In the case of the inductor circuits, the voltage leads the current because the voltage must be present first to build up the flux linkage to which the current is proportional. The operation of the circuits in Figures 9.31 through 9.34 demonstrates that inductors and capacitors are capable of reversible energy storage. To see this, let us examine the circuit shown in Figure 9.31 in detail; an examination of the three remaining circuits would yield identical observations. For this circuit, the power delivered by the source to the capacitor is given by v(t)I(t) = 482b 0 t≤0 2 I◦ sin(ωt) 1 − cos(ωt) t > 0. ωC (9.73) Integration of this power, or rate of energy delivery to the capacitor, yields wE (t) = 0 I2 ◦ ω2 C t≤0 3 1 − cos(ωt) + cos(2ωt) 4 4 t>0 (9.74) as the energy stored in the capacitor. The current I, the voltage v, the power vI into the capacitor, and the energy wE stored in the capacitor are all shown in Figure 9.35. From the figure we see that the power can be both positive and negative indicating that energy can be delivered to and retrieved from the capacitor. In fact, during odd intervals of π /ω in time, energy is delivered to the capacitor. It is then retrieved without loss during the following even interval of π/ω in time. Thus, ideal capacitors are lossless energy reservoirs. The same is true for inductors. 482c 9.4.4 R O L E R E V E R S A L * In each example in this section, a single capacitor or inductor was driven by a source. When that element was driven by a current source its branch current was imposed, and its branch voltage evolved in response. Alternatively, when the element was driven by a voltage source, its branch voltage was imposed, and its branch current evolved in response. However, because the branch variables of a capacitor are self-consistently related by Equations 9.9 and 9.12, their roles as the sourced and the responding branch variable may be reversed. Similarly, because the branch variables of an inductor are related by Equations 9.28 and 9.30, their roles may also be reversed. This allows us to use one circuit response to derive its converse. Specifically, we will derive the circuit responses to impulse inputs using the role reversal argument. As an example of role reversal consider the circuit shown in Figure 9.32 with the source voltage V given by Equation 9.80. The current i that circulates through its source and capacitor in response to the step in source voltage is the current impulse given by Equation 9.86. Now suppose instead that it is the current i in Equation 9.86 that is imposed by a source, as in Figure 9.31 with I ≡ i. What would be the voltage response v across the source and capacitor? The answer is that it would be V from Equation 9.80 so that v = V. This can be verified by substituting i in Equation 9.86 for I in Equation 9.63 and carrying out the indicated integration with the help of Equation 9.82 to derive v. Thus the current and voltage in Equations 9.86 and 9.80 are a self-consistent pair of branch variables for a capacitor. They can be either the source and response, or the response and the source. In this way we are able to find the circuit response to a current impulse from the circuit response to a voltage step. In the same way, we can use Equations 9.90 and 9.91, which apply to the circuit shown in Figure 9.34, to determine i in Figure 9.33 for the case in which V is an impulse. For example, suppose that the voltage v in Equation 9.91 is imposed by the source in Figure 9.33 with V ≡ v. What would be the current response i through the source and inductor? The answer is that it would be I from Equation 9.90 so that i = I. This can be verified by substituting v in Equation 9.91 for V in Equation 9.65 and carrying out the indicated integration with the help of Equation 9.82 to derive i. Thus the current and voltage in Equations 9.90 and 9.91 are a self-consistent pair of branch variables for an inductor. They can be either the source and response, or the response and the source. In this way we are able to find the circuit response to a voltage impulse from the circuit response to a current step. 489a 10.5.4 S O L U T I O N B Y I N T E G R A T I N G F A C T O R S * Another approach to solution of first-order differential equations is via integrating factors. To illustrate, we return to the simple RC circuit driven by a current source, Figure 10.2a. The corresponding differential equation, slightly rewritten from Equation 10.2 is dvC dt + vC = τ 1 i(t). C (10.103) We now assume i(t) is some arbitrary input waveform, and that there is an initial charge on the capacitor: vC (t = 0− ) = Vo . (10.104) To solve Equation 10.103, we look for an integrating factor f such that the left-hand side of the equation becomes the derivative of a product; f dvC dt + fvC τ = d (fvC ) dt df dvC + vC . =f dt dt (10.105) (10.106) Equating corresponding terms we find f τ = df (10.107) dt f = et/τ . (10.108) After multiplying both sides of Equation 10.103 by this factor, we obtain d dt (vC et/τ ) = 1 C et/τ i(t). (10.109) Now integrate from zero to t, and use corresponding limits on both sides of the equation: vC (t)et/τ 1 t t /τ t/τ e i(t )dt d(vC e ) = (10.110) C 0 vC (0)e0/τ where t is a dummy variable of the integration. Performing the integration on the left, and evaluating, we obtain vC (t)e t/τ − V0 = 1 C t et /τ i(t )dt . (10.111) 0 544a Hence we find an explicit closed form solution for vC (t): vC (t) = V0 e−t/τ + e−t/τ C t et /τ i(t )dt . (10.112) 0 Because the first term on the right depends only on the initial voltage on the capacitor, this term must be the zero-input response. Similarly, the second term is the zero-state response. Thus Equation 10.112 validates our initial assumption (Section 10.5.3) that the total response is the sum of the ZIR and ZSR. Equation 10.112 can be applied to any first-order linear system with arbitrary input waveform. Examples will be presented in the next section. Unfortunately, the extension to second- and higher-order systems is beyond the scope of this text, so we will continue to rely on the homogeneous solution-particular solution approach in dealing with such systems. 544b e x a m p l e 10 . 3 solution by integrating factors We can also solve Equation 10.114 by integrating factors. To do so, we note that the Norton equivalent source is vI /R. Then the ZSR, from Equation 10.112, is vC = e−t/τ t C et /τ 0 S t 1 R dt . (10.131) A helpful integral at this point is xex dx = xex − ex . So equating x to t /τ , so that dx = dt /τ we find vC = S1 τ e−t/τ = S1 τ e−t/τ t τ t τ et /τ − et /τ t (10.132) 0 et/τ − et/τ + 1 = S1 (t − RC) + S1 RCe−t/RC . (10.133) (10.134) This function is identical to that in Equation 10.124 and is plotted in Figure 10.33e. 550a 10.6.6 R C R E S P O N S E T O D E C A Y I N G E X P O N E N T I A L * To illustrate the application of Equation 10.148, suppose we now apply a short decaying exponential pulse to the RC circuit, as in Figure 10.47. Specifically we assume that the input driving signal is vI = Ae−t/τ1 t > 0. (10.155) If the ‘‘short pulse’’ concept is correct, and τ1 is much less that the circuit time constant RC = τ2 , then the output response to this exponential pulse should (a) R vI + Ae –t⁄ τ1 vI + - C - t (b) vC Aτ1 ------------------ e–t⁄RC RC – τ1 F I G U R E 10.47 Response to decaying exponential pulse. t –Aτ1 –t⁄ τ1 -----------------e RC – τ1 (c) vC t 558a vC be proportional to its area. The pulse area is Area = ∞ Ae−t/τ1 dt (10.156) 0 ∞ = −Aτ1 e−t/τ1 (10.157) = Aτ1 . (10.158) 0 Hence the zero-state response of the circuit should be, from Equation 10.148, vC Aτ1 τ2 e−t/RC . (10.159) To check this answer, we solve for the ZSR by using integrating factors. The differential equation describing the circuit is vI = RC dvC dt + vC . (10.160) From Equation 10.112, assuming an exponential drive as given by Equation 10.155, the ZSR is vC = e−t/τ2 τ2 t et /τ2 A e−t /τ1 dt . (10.161) 0 The solution has two distinct forms, depending on the relative size of the two time constants τ1 and τ2 . We first assume that the drive pulse does not have the same time constant as the circuit. Then, from Equation 10.161, −t/τ2 Ae vC = τ2 = A 1 − τ2 /τ1 1 1 τ2 − 1 τ1 e t −t τ2 τ1 e−t/τ1 − e−t/τ2 . 1 (10.162) 0 (10.163) The first term of Equation 10.163 is the forced response to the exponential input, with a time dependence the same as the input, but scaled in magnitude by a factor related to the circuit time constant. The second term is the natural response, (the homogeneous solution) with a time dependence characteristic of the circuit rather than the drive. This solution is completely general (except τ1 = RC). To match the ‘‘short pulse’’ solution, we must assume that τ1 is much smaller than τ2 = RC. For this 558b case, the two terms are shown in Figure 10.47b, and the complete response is shown in 10.47c. If we make the pulse drive very short, then τ1 becomes negligible compared to τ2 , the first transient becomes shorter and shorter, and except very near t = 0 the capacitor voltage becomes vC Aτ1 RC e−t/RC (10.164) as we found from the area calculation. The results of this discussion can be generalized to state that whenever the characteristic time of the input pulse is much shorter than the time constants of a linear circuit, the capacitor voltages and inductor currents in the circuit respond to the area of the input pulse, and are almost independent of the shape of the pulse. In solving Equation 10.161, we set aside a special case which is of some interest in a broader context. The question is, does the circuit behave in some bizarre fashion if the drive pulse has the same time constant as the circuit? One might be led to think so from Equation 10.163, because for τ1 = RC, the denominator goes to zero. To find the correct answer, assume τ2 = τ1 = τ in Equation 10.161 and solve: vC = e−t/τ =A τ t Adt te−t/τ τ . This waveform looks much like that shown in Figure 10.47c. 558c (10.165) 0 (10.166) e x a m p l e 12. 5 g r a p h i c a l i n t e r p r e t√a t i o n This example studies an interesting graphical interpretation of ωo = 1/ LC and the characteristic impedance L/C. √ Figure 12.13 shows contours of constant ω◦ ≡ 1/ LC and constant L/C in the L C plane over practical ranges for L and C. These contours are straight lines in the figure owing to the logarithmic scales of the figure. This figure is particularly useful for finding ω◦ and L/C for a given L and C, and vice versa, for example. ... 1 -----------LC L ---C ... ... rad rad rad rad rad rad 107 -------- 7 106 ---------- 6 105 ---------- 5 104 ---------- 4 103 ---------102 ---------s 10 Ω s 10 Ω s 10 Ω s 10 Ω s 1000 Ω s 100 Ω 108 ... 1H rad -------s 10 Ω 1Ω 1 mH rad 1010 -------s 0.1 Ω L 1 mH rad 1011 -------s 0.01 Ω 10–3 Ω 1 nH rad 1013 -------s 1 pH 1 fF 10–4 Ω 1 pF 1 nF C 1 mF 1 mF √ F I G U R E 12.13 Contours of constant ω◦ ≡ 1/ LC and constant L/C in the L–C plane. 640a 12.4 U N D R I V E N , P A R A L L E L R L C C I R C U I T * v i + vC C R L L - F I G U R E 12.24 The parallel second-order RLC circuit shown in Figure 2.14a. We will now analyze the undriven parallel RLC circuit shown in Figure 12.24, which is copied from Figure 2.14a. To analyze the behavior of this circuit we can again employ the node method, and this analysis closely parallels that of Section 12.1. As in Figure 12.6, a ground node is already selected in Figure 12.24, and the unknown node voltage v is already labeled. So, we may again proceed immediately to Step 3 of the node method. Here, we write KCL in terms of v for the node at which v is defined. This yields C dv(t) + dt 1 R v(t) + 1 L t −∞ v(t̃)dt̃ = 0. (12.81) The first term in Equation 12.81 is the capacitor current, the second term is the resistor current, and the third term is the inductor current. Because the circuit contains an inductor, Equation 12.81 contains a time integral. To remove this integral, we differentiate Equation 12.81 with respect to time, and also divide by C, to obtain d2 v(t) dt2 + 1 dv(t) RC dt + 1 LC v(t) = 0, (12.82) which is easier to work with. To complete the node analysis, we complete Steps 4 and 5 by solving Equation 12.82 for v. Then, we use v to determine the other branch variables of interest, for example, iL and vC . Like Equation 12.4, Equation 12.82 is an ordinary second-order linear differential equation with constant coefficients. Since the circuit does not have a drive, its homogeneous solution is also the complete solution. Therefore, as with Equation 12.4, we expect its solution to be a superposition of two terms of the form Ae st . The substitution of this candidate term into Equation 12.82 yields 1 1 s+ e st = 0 A s2 + RC LC (12.83) from which it follows that s2 + 1 RC s+ 1 LC = 0. (12.84) Equation 12.84 is the characteristic equation of the circuit. To simplify Equation 12.84, and to put it in a form that is more standard for the characteristic 654a equation in second-order circuits, we write it as s 2 + 2αs + ω◦2 = 0 (12.85) where α≡ ω◦ ≡ 1 (12.86) 2RC 1 LC ; (12.87) note that Equation 12.87 is the same as Equation 12.9. Equation 12.85 is a quadratic equation having two roots. Those roots are ! s1 = −α + α 2 − ω◦2 ! s2 = −α − α 2 − ω◦2 . (12.88) (12.89) Therefore, the solution for v is a linear combination of the two functions e s1 t and e s2 t , and takes the form v(t) = A1 e s1 t + A2 e s2 t (12.90) where A1 and A2 are as yet unknown constants that are equivalent to the two constants of integration encountered when integrating Equation 12.82 twice to find v. To complete the solution to Equation 12.82 we must again determine A1 and A2 from initial conditions vC and iL specified at t = 0, To do so, note that vC (t) = v(t). (12.91) Further, from KCL applied to either node, that is, from Equation 12.81, dv 1 iL (t) = − v(t) − C . R dt (12.92) Equations 12.91 and 12.92 can be solved to determine v and dv/dt in terms of iL and vC . Doing so, and evaluating the result at t = 0, then yields v(0) = vC (0) (12.93) 1 1 (0) = − iL (0) − vC (0). dt C RC (12.94) dv 654b Now, to find A1 and A2 , we evaluate Equation 12.90 and its derivative at t = 0, and set the results equal to Equations 12.93 and 12.94, respectively. This results in v(0) = A1 + A2 = vC (0) (12.95) dv (0) = s1 A1 + s2 A2 dt 1 1 vC (0). = − iL (0) − C RC (12.96) Equations 12.95 and 12.96 can be jointly solved for A1 and A2 to obtain A1 = A2 = (1 + RCs2 )vC (0) + RiL (0) RC(s2 − s1 ) (1 + RCs1 )vC (0) + RiL (0) RC(s1 − s2 ) = = s1 vC (0) − iL (0)/C (s1 − s2 ) s2 vC (0) − iL (0)/C (s2 − s1 ) (12.97) (12.98) where we have used the fact that both s1 and s2 satisfy Equation 12.84, and the fact that LCs1 s2 = 1, to obtain the second equalities. Finally, Equations 12.97 and 12.98 can now be substituted into Equation 12.90 to obtain v(t) = s1 vC (0) − iL (0)/C (s1 − s2 ) e s1 t + s2 vC (0) − iL (0)/C (s2 − s1 ) e s2 t . (12.99) Further, the substitution of Equation 12.99 into Equations 12.91 and 12.92 yields vC (t) = s1 vC (0) − iL (0)/C (s1 − s2 ) iL (t) = − − = 1 + RCs1 R 1 + RCs2 s2 vC (0) − iL (0)/C (s2 − s1 ) s1 vC (0) − iL (0)/C (s1 − s2 ) s2 vC (0) − iL (0)/C R vC (0)/L − s2 iL (0) (s1 − s2 ) e s1 t + (s2 − s1 ) e s1 t + e s2 t (12.100) e s2 t (12.101) e s1 t e s2 t vC (0)/L − s1 iL (0) (s2 − s1 ) as the states of the parallel circuit. To obtain the second equality in Equation 12.101 we have again used the fact that both s1 and s2 satisfy 654c Equation 12.84, and the fact that LCs1 s2 = 1. This completes the formal node analysis of the circuit shown in Figure 12.24. We will now close this subsection by examining the dynamic behavior of vC and iL for the same three cases defined in Section 12.2. Those are the cases of under-damped, critically-damped, and over-damped dynamics. As we shall see, the dynamics of the series circuit are essentially identical to those of the parallel circuit for all three cases, except for the details of the role of R. In the series circuit, small R caused light damping while large R caused heavy damping. This role reverses for the parallel circuit because it is in the limit of large R that Figure 12.24 reduces to Figure 12.6. 12.4.1 U N D E R - D A M P E D D Y N A M I C S The case of under-damped dynamics is characterized by α < ω◦ or, after substitution of Equations 12.86 and 12.87, by 2R > L/C. As R becomes large, the corresponding resistor approaches an open circuit, and so the circuit shown in Figure 12.24 approaches the LC circuit shown in Figure 12.6. Therefore, we should expect the under-damped dynamics to be oscillatory in nature. As we shall see shortly, this is indeed the case. With α < ω◦ , the quantity inside the radicals in Equations 12.88 and 12.89 is negative, and so the natural frequencies s1 and s2 are complex numbers. To simplify matters, let us again define ωd according to ωd ≡ ! ωo2 − α 2 . (12.102) With this definition, s1 and s2 from Equations 12.88 and 12.89 can be written as s1 = −α + jωd (12.103) s2 = −α − jωd . (12.104) The real and imaginary parts of s1 and s2 are now more apparent. Since s1 and s2 are now complex, the exponentials in Equations 12.100 and 12.101 are also complex. Thus, iL and vC will exhibit both oscillatory and decaying behavior. To see this, we substitute Equations 12.103 and 12.104 into 654d Equations 12.100 and 12.101, and use the Euler relation to obtain vC (t) = vC (0)e−αt cos(ωd t) − αCvC (0) + iL (0) Cωd αCvC (0) + iL (0) 2 −αt e = vC2 (0) + Cωd αCvC (0) + iL (0) × cos ωd t + tan−1 Cωd vC (0) vC (0) + αLiL (0) (12.105) e−αt sin(ωd t) Lωd vC (0) + αLiL (0) 2 −αt e = iL2 (0) + Lωd Lωd iL (0) . (12.106) × sin ωd t + tan−1 vC (0) + αLiL (0) iL (t) = iL (0)e −αt e−αt sin(ωd t) cos(ωd t) + Sketches of iL and vC are shown in Figure 12.25 for the special case of iL (0) = 0. As was the case for the series circuit, the states in the parallel circuit display oscillatory and decaying behavior. It is also the case that Equations 12.105 and 12.106 reduce to Equations 12.21 and 12.22, respectively, as the circuit damping characterized by α vanishes. The difference here is that this occurs as R → ∞ because it is in this limit that Figure 12.24 reduces to Figure 12.6. A comparison of Equations 12.105 and 12.106 with Equations 12.63 and 12.64 shows that the under-damped dynamics of the parallel and series circuits are quite similar. This is to be expected because their characteristic equations are identical. It is for this reason that α, ω◦ , ωd , and Q have the same interpretations for the two circuits. Our comments concerning stored energy also hold for both circuits. Therefore, we will not repeat the details here. Rather, we will identify three important differences. The first difference, which has been mentioned already, is the reversed role of R. A large R in the series circuit corresponds to a small R in the parallel circuit and vice versa. The second difference is the evaluation of the quality factor Q. While Equation 12.65 still holds for the parallel circuit, that is, Q≡ 654e ω◦ 2α , (12.107) vC vC(0) -αt e | | 0 | π/ωd | | 2π/ωd | | 3π/ωd | | 4π/ωd | | 5π/ωd | | | | | 6π/ωd 7π/ωd t | iL F I G U R E 12.25 Waveforms of vC and iL in undriven, parallel RLC circuit for the case of iL (0) = 0. Io | 0 π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd t Equation 12.66 does not. Rather, for the parallel circuit shown in Figure 12.24, the substitution of Equations 12.86 and 12.87 into Equation 12.65 yields Q= 1 L R C (12.108) or Q= ωo L R . (12.109) 654f The third difference is the role of φ in Figure 12.17. For the parallel circuit, assuming iL (0) = 0 in Equations 12.105 and 12.106, vC is advanced with respect to iL by quadrature plus the additional angle φ, where φ = tan−1 (α/ωd ). 12.4.2 O V E R - D A M P E D D Y N A M I C S As with the case of the series circuit, the case of over-damped dynamics is characterized by α > ω◦ or, after substitution of Equations 12.86 and 12.87, by 2R < L/C. In this case, the quantity inside the radicals in Equations 12.88 and 12.89 is positive, and so both s1 and s2 are real. For this reason, the dynamic behavior of iL and vC , as expressed by Equations 12.100 and 12.101, does not exhibit oscillation. Rather, it involves two real exponential functions that decay at different rates, as the two equations show. The expressions for vC and iL for the case of iL (0) = 0 with over-damping are obtained from Equations 12.100 and 12.101, and are shown here: vC (t) = iL (t) = s1 vC (0) (s1 − s2 ) vC (0) L(s1 − s2 ) e s1 t + e s1 t + s2 vC (0) (s2 − s1 ) e s2 t vC (0) L(s2 − s1 ) e s2 t . (12.110) (12.111) Since α > ω◦ for over-damped circuits, note that s1 and s2 are both real in these two equations. As R becomes small, in particular smaller than 1/2 L/C, it becomes a significant short circuit across the capacitor and inductor. In this way it diverts the oscillating current that the capacitor and inductor share for larger values of R. As a consequence, the energy exchange between the capacitor and inductor is interrupted, and the circuit ceases to oscillate. Instead, its behavior is more like that of an independent capacitor and an independent inductor discharging through the resistor. To see this, let us determine the asymptotic values of s1 and s2 as R becomes small and hence as α becomes large. They are s1 = −α + ! α 2 − ω◦2 = α −1 + 1− ω◦ α 2 2 ≈ α −ω◦ = −R 2α 2 L (12.112) 654g ! s2 = −α − α 2 − ω◦2 = α −1 − 1− ω◦ α 2 ≈ −2α = −1 . (12.113) RC As expected the corresponding time constants approach RC and L/R, the time constants of an independent capacitor-resistor circuit and an independent inductor-resistor circuit. Note that, for over-damped dynamics, α > ω◦ from which it follows that RC is the faster time constant and L/R is the slower time constant. 12.4.3 C R I T I C A L L Y - D A M P E D D Y N A M I C S The case of critically-damped dynamics is characterized by α = ω◦ . In this case, it follows from Equations 12.88 and 12.89 that s1 = s2 = −α and that the characteristic equation, Equation 12.85, has a repeated root. Because of this, e s1 t and e s2 t are no longer independent functions, and so the general solution for v is no longer the superposition of these two functions as given by Equation 12.90. Rather, it is again the superposition of the repeated exponential function e s1 t = e s2 t = e−αt and te−αt . From this observation, and Equations 12.91 and 12.92, it follows that vC and iL will exhibit similar behavior. Perhaps the easiest way to determine vC and iL for the case of critical damping is to evaluate Equations 12.105 and 12.106 under the conditions of that case. To do so, observe from Equation 12.102 that, for critical damping ω◦ = α, and so ωd = 0. Therefore, we can obtain vC and iL for the case of critical-damping by evaluating Equations 12.105 and 12.106 in the limit ωd → 0. This results in vC (t) = vC (0)e−αt − iL (t) = iL (0)e−αt + αCvC (0) + iL (0) C te−αt (12.114) vC (0) + αLiL (0) te−αt . (12.115) L From Equations 12.114 and 12.115 we see that vC and iL contain both the decaying exponential function e−αt and the function te−αt , as expected. 654h 12.6 D R I V E N , P A R A L L E L R L C C I R C U I T * Consider now the circuit shown in Figure 12.50. As in previous sections of this chapter, we will analyze the behavior of this circuit using the node method beginning at Step 3. In doing so, we will follow the analysis presented in Section 12.4 very closely. We begin by completing Step 3, of the node method. To do so, we write KCL in terms of vC for the node at which vC is defined to obtain C dvC (t) dt + 1 R vC (t) + 1 L t −∞ vC (t̃)dt̃ = iIN (t), (12.198) which upon differentiation and division by C becomes d2 vC (t) dt2 + 1 dvC (t) RC dt + 1 LC vC (t) = 1 diIN (t) C dt . (12.199) Unlike Equations 12.4, 12.82 and 12.40, Equation 12.199 is an inhomogeneous differential equation because it is driven by the external signal iIN . Unfortunately, iIN enters Equation 12.199 through a derivative, which poses an unnecessary complication. To eliminate this complication, we substitute the constitutive law for the inductor, vC (t) = L diL (t) , dt into Equation 12.198 and divide by LC. This yields d2 iL (t) dt2 + 1 diL (t) RC dt + 1 LC iL (t) = (12.200) 1 LC iIN (t), (12.201) which is easier to work with. Equation 12.201 is an inhomogeneous differential equation, which unlike our previous undriven examples (for example, Equation 12.4 for the undriven vC iL F I G U R E 12.50 The parallel second-order circuit with a resistor, capacitor, inductor, and current source. 678a iIN + vC - C R L LC circuit) has an additional term for the input drive. Furthermore, notice the term proportional to diL /dt. As we saw in Section 12.5, this term modifies the homogeneous response to include damping. Therefore we now expect the oscillations in the step and impulse responses to decay in time. To complete the node analysis, we complete Steps 4 and 5 by solving Equation 12.201 for iL , and using it to determine vC and any other variables of interest. To do so we employ our usual method of solving differential equations: 1. Find the homogeneous solution iLH (t). 2. Find the particular solution iLP (t). 3. The total solution is then the sum of the homogeneous solution and the particular solution as follows: iL (t) = iLH (t) + iLP (t). Use the initial conditions to solve for the remaining constants. The homogeneous solution iLH (t) to Equation 12.201 is obtained by solving the differential equation with the drive iIN ≡ 0. With iIN ≡ 0, the circuit shown in Figure 12.50 is identical to the parallel, undriven RLC circuit shown in Figure 12.24, and so the two circuits have the same homogeneous equation. The homogeneous equation in terms of the current is given by d2 iLH (t) dt2 + 1 diLH (t) RC dt + 1 LC iLH (t) = 0. (12.202) Note the similarity between this homogeneous equation and Equation 12.4 for the undriven, parallel RLC circuit. Following the solution (Equation 12.10) of the homogeneous equation for the undriven, parallel RLC circuit, we can write the form of the homogeneous solution for our driven, parallel RLC circuit as iLH (t) = K1 e s1 t + K2 e s2 t (12.203) where K1 and K2 are as yet unknown constants that will be determined from the initial conditions after the total solution has been formed. s1 and s2 , the roots of the characteristic equation, s 2 + 2αs + ω◦2 = 0 α≡ ω◦ ≡ 1 (12.205) 2RC 1 LC (12.204) . (12.206) 678b The roots are given by s1 = −α + s2 = −α − ! ! α 2 − ω◦2 (12.207) α 2 − ω◦2 . (12.208) As observed with other second-order circuits, the circuit exhibits under-damped, over-damped, or critically-damped behavior depending on the relative values of α and ω◦ : α < ω◦ α = ω◦ α > ω◦ ⇒ ⇒ ⇒ under-damped dynamics; critically-damped dynamics; over-damped dynamics. For brevity, the rest of the section will assume that α < ω◦ so that the circuit displays under-damped dynamics. For the under-damped case, since s1 and s2 are now complex, they can be written explicitly in complex form as s1 = −α + jωd s2 = −α − jωd where ωd ≡ ! ω◦2 − α 2 . (12.209) (12.210) As we did with the series RLC circuit, we shall rewrite the homogeneous solution in Equation 12.121 into a more intuitive form using the Euler relation as follows: iLH (t) = A1 e−αt cos(ωd t) + A2 e−αt sin(ωd t) (12.211) where A1 and A2 are unknown constants we will evaluate later depending on the initial conditions of the circuit. Next, we need to find iLP (t). Knowing it, we can write the total solution as iL (t) = iLP (t) + iLH (t) = iLP (t) + A1 e−αt cos(ωd t) + A2 e−αt sin(ωd t). (12.212) At this point, only iLP , and A1 and A2 , remain as unknowns. We will now proceed to find the iLP , and then A1 and A2 . iLP depends on the input drive. We will find iLP for two cases of iIN , namely a step and 678c an impulse. That is, we will proceed to find the step response and the impulse response of the circuit. To simplify matters, we will assume that the circuit is under-damped, that both the step and the impulse occur at t = 0, and that the circuit is initially at rest prior to that time. The latter assumption implies that we are seeking the zero-state response for which iL (0) = 0 (12.213) vC (0) = 0. (12.214) and The zero-state response is the response of the circuit for zero initial state. Equations 12.213 and 12.214 provide the initial conditions for the solution of Equation 12.201 after the step and impulse occur, that is, for t > 0. 12.6.1 S T E P R E S P O N S E iIN Let iIN be the current step given by Io iIN (t) = I◦ u(t) (12.215) and shown in Figure 12.51. With the substitution of Equation 12.215, Equation 12.201 becomes d2 iL (t) dt2 + 1 diL (t) RC dt + 1 LC iL (t) = 1 LC I◦ (12.216) t 0 F I G U R E 12.51 A current step input. for t > 0. Any function that satisfies Equation 12.216 for t > 0 is an acceptable iLP . One such function is iLP (t) = I◦ . (12.217) Thus, we have the particular solution for a step input. The total solution is given by summing the homogeneous solution (Equation 12.211) and the particular solution (Equation 12.217) as iL (t) = I◦ + A1 e−αt cos(ωd t) + A2 e−αt sin(ωd t), (12.218) again for t > 0. Additionally, the substitution of Equation 12.218 into Equation 12.200 yields vC (t) = (ωd LA2 − αLA1 )e−αt cos(ωd t) − (ωd LA1 + αLA2 )e−αt sin(ωd t), (12.219) also for t > 0. Now only A1 and A2 remain as unknowns. 678d In Chapter 9, we saw that the voltage across a capacitor is continuous unless the current through it contains an impulse. We also saw that the current through an inductor is continuous unless the voltage across it contains an impulse. Since iIN contains no impulses, we can therefore assume that both vC and iL are continuous across the step at t = 0. Consequently, since both states are zero for t ≤ 0, Equations 12.218 and 12.219 must both evaluate to zero as t → 0. This observation allows us to use the initial conditions to determine A1 and A2 . Evaluation of both equations as t → 0, followed by the substitution of the initial conditions, yields iL (0) = I◦ + A1 = 0 (12.220) vC (0) = ωd LA2 − αLA1 = 0. (12.221) Equations 12.220 and 12.221 can be solved to yield A1 = −I◦ A2 = − α ωd I◦ . (12.222) (12.223) Finally, the substitution of Equations 12.222 and 12.223 into Equations 12.218 and 12.219 yields ω◦ −αt α −1 iL (t) = I◦ 1 − u(t) (12.224) e cos ωd t − tan ωd ωd vC (t) = I◦ ωd C e−αt sin(ωd t)u(t); (12.225) Equations 12.210 and 12.206 have also been used to simplify the results. Note that the unit step function u has been introduced into Equations 12.224 and 12.225 so that they are valid for all time. The validity of Equations 12.224 and 12.225 can be demonstrated by observing that they satisfy the initial conditions, and Equations 12.201 and 12.200, respectively, for all time. Because they do, our assumption that the states are continuous at t = 0 is justified. Figure 12.52 shows iL and vC as given by Equations 12.224 and 12.225. As expected, the ringing in both states now decays as t → ∞. This decay is well characterized by the quality factor Q, as defined in Equation 12.66 and discussed shortly thereafter. In fact, because the circuits shown in Figures 12.24 and 12.50 have the same homogeneous response, the entire discussion of α, ωd , and ω◦ given in Section 12.4 applies here as well. In fact, the series and parallel circuits are duals. This can be observed by comparing the evolution of their branch variables. For example, like the capacitor voltage vC in the series circuit, iL undergoes nearly a two-fold overshoot during the initial transient. 678e vC e-αt 0 π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd t | iL F I G U R E 12.52 iL and vC for the parallel RLC circuit shown in Figure 12.50 for the case of a step input through iIN . Io 0 π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd t Another observation concerns the short-time behavior of the circuit. We have seen in Chapter 10 that the transient behavior of an uncharged capacitor is to act as a short circuit during the early part of a transient, while the corresponding transient behavior of an uncharged inductor is to act as an open circuit. This behavior is observed in Figure 12.52 since iIN is carried entirely 678f by the capacitor (and iL is 0) at the start of the transient, and vC ramps up correspondingly. A related observation concerns the long-time behavior of the circuit. We have also seen in Chapter 10 that the transient behavior of a capacitor is to act as an open circuit as t → ∞, while the corresponding transient behavior of an inductor is to act as a short circuit. This behavior is also observed in Figure 12.52, since iIN is carried entirely by iL as t → ∞. We also note the overshoot of iL above the input current step of I◦ during the transient. Although the average value of iL is close to I◦ during the transient, the peak value is closer to 2I◦ . Finally, note that as t → ∞, iIN is carried entirely by the inductor since iL → I◦ . This is consistent with the relative long-time transient behavior of the inductor, resistor, and capacitor. 12.6.2 I M P U L S E R E S P O N S E Let iIN be the impulse given by iIN = Q◦ δ(t) as shown in Figure 12.53. Because iIN is an impulse, it vanishes for t > 0. Therefore, Equation 12.201 reduces to a homogeneous equation for t > 0, and so the simplest acceptable particular solution is iIN Qo iLP (t) = 0. 0 F I G U R E 12.53 The current impulse iIN . (12.226) t (12.227) The substitution of Equation 12.227 into Equation 12.212 now yields iL (t) = A1 e−αt cos(ωd t) + A2 e−αt sin(ωd t) (12.228) again for t > 0. Additionally, we can obtain vC (t) by using vC (t) = L diL (t) dt as vC (t) = (LA2 ωd − LαA1 )e−αt cos(ωd t) − (LA1 ωd + LαA2 )e−αt sin(ωd t) (12.229) also for t > 0. Now only A1 and A2 remain as unknowns. From this discussion, it is apparent that the role of the impulse in iIN is to establish the initial conditions for a subsequent homogeneous response. This, 678g incidentally, might explain how the circuit shown in Figure 12.24 began its operation. As mentioned earlier during our discussion of the step response, the transient behavior of an uncharged capacitor is to act as a short circuit during the early part of a transient, while the corresponding transient behavior of an uncharged inductor is to act as an open circuit. Because of this the impulse in iIN passes entirely through the capacitor while iL remains zero at t = 0. An important consequence of this is that the charge Q◦ delivered by iIN is delivered entirely to the capacitor, and so vC steps to Q◦ /C at t = 0. This establishes the initial conditions after the impulse needed to determine A1 and A2 . The evaluation of Equations 12.228 and 12.229 as t → 0, followed by the substitution of these initial conditions (vC (0) = Q◦ /C and iL (0) = 0), yields iL (0) = A1 = 0 vC (0) = ω◦ LA2 = (12.230) Q◦ C . (12.231) Equations 12.230 and 12.231 can be rearranged to yield A1 = 0 A2 = Q◦ LCωd (12.232) . (12.233) Finally, the substitution of Equations 12.232 and 12.233 into Equations 12.228 and 12.229 yields Q◦ ωo2 e−αt sin(ωd t) α Q◦ ω◦ −αt −1 vC (t) = u(t), e cos ωd t + tan C ωd ωd iL (t) = ωd (12.234) (12.235) where the unit step function u has been introduced into Equations 12.234 and 12.235 so they are valid for all time. Note that our solution in Equation 12.234 satisfies the initial conditions established by the impulse, and that it satisfies Equation 12.201. Because it does, it justifies our interpretation of the circuit behavior at t = 0. The waveforms for vC and iL are as shown in Figure 12.54. It is interesting to note that the impulse response of the circuit can also be obtained from the step response. The circuit shown in Figure 12.50 is a linear circuit. Therefore, since the impulse iIN given in Equation 12.226 is a scaled derivative of the step iIN given in Equation 12.215, it follows that the impulse response is the same scaled derivative of the step response. (See Section 10.6.2 678h vC Qo/C e-αt 0 π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd t iL | F I G U R E 12.54 Waveforms of iL and vC for the parallel RLC circuit for a short pulse input. e-αt 0 π/ωd 2π/ωd 3π/ωd 4π/ωd 5π/ωd 6π/ωd 7π/ωd t for a more detailed discussion on the use of linearity to obtain responses to the derivative or the integral of an input, once the response to the input is known.) To be more specific, iIN as given in Equation 12.226, can be constructed by applying (Q◦ /I◦ )d/dt to iIN as given in Equation 12.215. In other words, Q◦ δ(t) = (Q◦ /I◦ ) d dt I◦ u(t). Therefore, the same operator may be applied to Equations 12.234 and 12.235 to determine iL and vC respectively, for the impulse response. Thus, we can 678i obtain the impulse response by differentiating the step response. Thus, applying the operator (Q◦ /I◦ )d/dt to the step response, we obtain α ω◦ −αt I◦ 1 − u(t) e cos ωd t − tan−1 ωd ωd I◦ dt α = ω◦ Q◦ e−αt sin ωd t − tan−1 u(t) ωd αω◦ Q◦ −αt α + u(t) e cos ωd t − tan−1 ωd ωd ω◦ −αt α + Q◦ 1 − δ(t) e cos ωd t − tan−1 ωd ωd iL (t) = Q◦ d = Q◦ vC (t) = = = ω◦2 ωd e−αt sin(ωd t)u(t) Q◦ d I◦ dt Q◦ C I◦ ωd C e −αt (12.236) sin(ωd t)u(t) e−αt cos(ωd t)u(t) − αQ◦ ωd C e−αt sin(ωd t)u(t) + α u(t) e−αt cos ωd t + tan−1 C ωd ωd Q◦ ω◦ Q◦ ωd C e−αt sin(ωd t)δ(t) (12.237) as the impulse response of the circuit. Note that terms involving the impulse δ vanish in Equations 12.236 and 12.237 because δ is itself zero everywhere except t = 0, and the coefficients of the impulse are both zero at t = 0. From this experience with the impulse, we can see that the impulse response of the circuit is essentially a homogeneous response. Thus this response is identical to that studied in Section 12.4. In fact, the role of the impulse is to establish initial conditions for the subsequent homogeneous response. As we argued in Section 12.6, the current impulse passes entirely through the capacitor delivering its charge in the process. Therefore, vC steps to Q◦ /C as iL remains zero. As a result, for t > 0, the impulse response described by Equations 12.236 and 12.237 are identical to Equations 12.105 and 12.106, respectively, with vC (0) replaced by Q◦ /C, and iL (0) replaced by zero. Therefore, the entire discussion of the circuit shown in Figure 12.24 is applicable. Not surprisingly, note that vC and iL for the impulse as shown in Figure 12.54 are the same as those in Figure 12.25 with vC (0) replaced by Q◦ /C. 678j 12.10 S T A T E - S P A C E A N A L Y S I S * A state-variable analysis naturally results in a set of coupled first-order differential equations. The results of a node analysis can also be expressed in this way. Therefore, it is worth exploring the direct solution of coupled first-order differential equations. In the case of a state-variable analysis, this approach to solving the equations eliminates the need to perform their back substitution in order to obtain a single high-order differential equation. When working with a set of coupled first-order differential equations it is common to present them in the vector format referred to as a state-space format, and to solve them with the corresponding mathematical mechanics. We will refer to this method of solution as a state-space analysis of the differential equations. It is beyond our scope to present a detailed treatment of state space analysis.10 Rather, we will summarize its mechanics through an example. To illustrate the mechanics of a state-space analysis, consider again the circuit shown in Figure 12.50. In Section 12.9 we completed a state-variable analysis of this circuit. The resulting state equations are given in Equations 12.253 and 12.254. Those equations may be summarized in state-space format according to 1 d vC (t) − RC = 1 iL (t) dt L −1 C 0 1 vC (t) + C [iIN (t)] . iL (t) 0 (12.255) Equation 12.255 is an example of the more general linear time-invariant statespace format dx(t) dt = Ax(t) + Bz(t). (12.256) Here, x is referred to as the state vector, z is referred to as the input vector, A is referred to as the state matrix, and B is referred to as the input matrix. In the case of Equation 12.255, x(t) = vC (t) iL (t) z(t) = iIN (t) Au:Please provide dates of publication for these 691a (12.257) (12.258) 10. For a detailed treatment of this analysis, see G. Strang, Linear Algebra and Its Applications, Third Edition, Chapter 5, Academic Press; or Finizio and Ladas, Ordinary Differential Equations, with Modern Applications, Second Edition, Section 3.3. A= − 1 RC 1 L B= 1 C −1 C 0 (12.259) 0 . (12.260) It is interesting to note that the results of a node analysis can also be expressed in state-space format. This is important at least because most commercial numerical analysis packages focus on the solution of differential equations presented in this format. The circuit shown in Figure 12.50 was analyzed by the node method in Section 12.6, and the resulting differential equation is given in Equation 12.201. To put Equation 12.201, which is of order two, into state-space format, we use iL and diL /dt as the two states within x, and write d dt iL (t) diL (t) dt = 0 − 1 LC 1 − 1 RC iL (t) diL (t) dt + 0 1 LC [iIN (t)] . (12.261) Thus, the results of both a state-variable analysis and a node analysis can be put into the standard state-space format. However, note that Equations 12.255 and 12.261 have different values for x, A and B. Because Equations 12.255 and 12.261 describe the dynamics of the same circuit, it is also apparent that there exists more than one state-space representation of the dynamics of a given circuit. Since Equations 12.255 and 12.261 describe the dynamics of the same circuit, their solutions will ultimately yield the same branch variables. Therefore, for the sake of brevity, we will now consider the state-space analysis of only Equation 12.255; the analysis of Equation 12.261 proceeds in an identical manner. To be specific about the solution of Equation 12.255 we will consider its response to a step input at t = 0. That is, we will assume that iIN (t) = I◦ u(t) (12.262) as shown in Figure 12.51. To simplify matters, we will also assume that the circuit is at rest prior to the step. That is, we will assume that both vC and iL are zero for t ≤ 0. This information provides the initial conditions for the solution of Equation 12.255 after the step occurs, that is, for t > 0. To solve Equation 12.255 we now proceed essentially as we did in the earlier sections of this chapter. That is, we break the solution into two parts, namely a particular solution, xP , and a homogeneous solution, xH . The particular solution will satisfy Equation 12.255 without regard for initial conditions, and the homogeneous solution will match the initial conditions. 691b Consider first the homogeneous solution. In general, the homogeneous solution is the solution to Equation 12.256 with z ≡ 0. Therefore, xH satisfies dxH (t) dt = AxH (t). (12.263) Since Equation 12.263 represents a set of ordinary first-order homogeneous linear differential equations with constant coefficients, we expect its solution to be a superposition of terms of the form re st where r is a constant vector having the same dimension as x. The substitution of this candidate term into Equation 12.263 yields (sI − A)re st = 0 (12.264) where I is the identity matrix of appropriate dimension. Since e st is never zero for finite st, it follows that (sI − A)r = 0. (12.265) Further, since r = 0 is a trivial solution that leads to x = 0, we are interested only in solutions to Equation 12.265 for which r = 0. For Equation 12.265 to be satisfied for a nonzero r, the matrix (sI − A) must be singular, hence det(sI − A) = 0. (12.266) Equation 12.266 is a polynomial in s, referred to as the characteristic equation of A, and its roots are the eigenvalues of A. For each root, there is a corresponding r that is the corresponding right eigenvector of A.11 To determine each eigenvector, the corresponding root of Equation 12.266 is substituted into Equation 12.265, and the resulting equation is solved for r to within an arbitrary scale factor. With the substitution of Equation 12.259, Equation 12.266 becomes det(sI − A) = det 1 RC −1 L s+ 1 C = s 2 + 1 s + 1 = 0, RC LC s (12.267) which is the same as Equation 12.84. Thus, we see that the characteristic equation of A is the same as the characteristic equation of the circuit, and that 11. Here, we ignore the degenerate case in which repeated eigenvalues share a single eigenvector. 691c the eigenvalues of A are the natural frequencies of the circuit. Equation 12.267 has two roots and they are given by ! (12.268) s1 = −α + α 2 − ω◦2 ! s2 = −α − α 2 − ω◦2 (12.269) α≡ 1 (12.270) 2RC 1 ω◦ ≡ √ LC (12.271) just as given in Equations 12.125 and 12.126. This is expected because the homogeneous version of the circuit shown in Figure 12.50 is the circuit shown in Figure 12.24. Finally, the corresponding eigenvectors, determined from Equation 12.265 for each eigenvalue, are 1 (12.272) r1 = 1 r2 = s1 L 1 1 s2 L . (12.273) With these results we can now assemble the homogeneous solution of Equation 12.255. It is given by 1 1 s1 t s2 t s1 t e + A2 e s2 t (12.274) xH (t) = A1 r1 e + A2 r2 e = A1 1 1 s1 L s2 L where A1 and A2 are two coefficients that depend on initial conditions. Consider now the particular solution. In general, it is the solution to Equation 12.256 without regard for the initial conditions. Thus, any function xP that satisfies dxP (t) (12.275) = AxP (t) + Bz(t) dt is an acceptable particular solution. To treat the general case of the step input, we let z(t) = Z◦ u(t). (12.276) The substitution of Equation 12.276 into Equation 12.275 yields dxP (t) dt = AxP (t) + BZ◦ (12.277) 691d for t > 0. Assuming that A−1 exists, one solution to Equation 12.277 is xP (t) = −A−1 BZ◦ , (12.278) again for t > 0. With the substitution of Equations 12.262 and 12.276, Equation 12.258 becomes Z◦ = I◦ . (12.279) Then, with the substitution of Equations 12.259, 12.260, and 12.279, Equation Equation 12.278 becomes xP (t) = − − =− 1 RC 1 L −1 −1 0 L −C −L C 0 1 C I◦ 0 I◦ = 0 R 1 C 0 , I◦ (12.280) also for t > 0. We can now combine the particular and homogeneous solutions with the initial conditions to solve Equation 12.255. To begin, the superposition of Equations 12.274 and 12.280 yields vC (t) = x(t) = xP (t) + xH (t) iL (t) = 0 + A1 I◦ 1 e 1 s1 L s1 t + A2 1 e s2 t . 1 s2 L (12.281) Now, A1 and A2 are the only unknowns. To find A1 and A2 , we use the initial conditions. Since iIN contains no impulses, we can assume that both vC and iL are continuous at t = 0. Consequently, since both states are zero for t ≤ 0, Equation 12.281 must evaluate to zero as t → 0. This yields vC (0) iL (0) = 0 I◦ + A1 1 1 s1 L + A2 1 1 s2 L = 0 0 . (12.282) The two rows of Equation 12.282 are two equations that can be solved for A1 and A2 . Doing so yields A1 = 691e s1 s2 LI◦ s1 − s 2 = I◦ C(s1 − s2 ) (12.283) A2 = s1 s2 LI◦ s2 − s 1 = I◦ C(s2 − s1 ) ; (12.284) note that the second equalities in Equations 12.283 and 12.284 follow from the substitution of Equations 12.268 and 12.269. Finally, the substitution of Equations 12.283 and 12.284 into Equation 12.281 yields vC (t) iL (t) = 0 I◦ u(t) + I◦ C(s1 − s2 ) 1 1 s1 L e s1 t u(t) + I◦ C(s2 − s1 ) 1 1 s2 L e s2 t u(t) (12.285) as the solution of Equation 12.255. Note that the unit step function u has been introduced into Equation 12.285 to extend the range of its validity. With a little effort it can be shown that the two rows of Equation 12.285 are identical to Equations 12.224 and 12.225. This is to be expected since both sets of equations are the results of analyses of the same circuit. 12.10.1 N U M E R I C A L S O L U T I O N * The state equation (specifically, Equations 12.255 and in a more general form, Equation 12.256) can also be solved using numeric methods. Our goal here is to demonstrate that the initial state contains all the information that is necessary to determine the entire future behavior of the system given the subsequent input. To help our intuition, we will describe an extremely simple method here. However, we note that other more efficient, but less intuitive, methods are employed in practice. Suppose that the input signal vector z(t) is known for all time t ≥ t0 . Also suppose that the initial value of the state vector at time t = t0 (denoted as x(t0 ) and called the initial state) is also known. Then the slope of the state vector (that is, dx/dt) at time t0 can also be found from Equation 12.256 as follows: dx dt (t0 ) = Ax(t0 ) + Bz(t0 ). (12.286) From this slope and the initial state x(t0 ), the value of the state vector at time t0 + t can now be estimated by standard numerical methods. Using Euler’s method, for example, we can approximate the value of the state vector at time t = t0 + t as x(t0 + t) = x(t0 ) + dx dt (t0 )t = x(t0 ) + Ax(t0 )t + Bz(t0 )t. (12.287) 691f Proceeding in the same manner, the value of x at time t = t0 + 2t can then be determined from the value of x(t0 + t) and z(t0 + t). Subsequent values of x(t) can be determined using the same process. By choosing small enough values of t, a computer can determine the waveform for the x(t) vector to an arbitrary degree of accuracy. This process illustrates the fact that the initial state contains all the information that is necessary to determine the entire future behavior of the system from the initial state and the subsequent input. Notice the similarity between the numerical solution process for the second-order system (Equations 12.256 and 12.287) and the first-order system (Equations 10.82 and 10.83). The major difference is that we are dealing with vectors and vector-matrix operations in the second-order system, while the first-order system dealt with scalar operations. Higher-order systems with many capacitors and inductors will result in a larger set of first-order state equations, which can be gathered into a single-vector state equation that is identical in form to Equation 12.256. 691g 12.11 H I G H E R - O R D E R C I R C U I T S * To close this chapter, we briefly consider the analysis of circuits having an order higher than two. The important message here is that the methods of analysis developed earlier in this chapter for second-order circuits are perfectly applicable to the analysis of higher-order circuits. We will illustrate this through the analysis of the circuit shown in Figure 12.63. Since the circuit has two independent capacitors and two independent inductors, it is a fourth-order circuit. Despite this, it readily submits to both a node analysis with the node voltages as the primary unknowns, and a state-variable analysis with the states as the primary unknowns. Consider first the node analysis of the circuit shown in Figure 12.63, carried out using v1 and v2 and as the two unknown node voltages. To begin, we write KCL at Nodes #1 and #2 in terms of these voltages. This yields C1 dv1 (t) dt + 1 R (v1 (t) − v2 (t)) + 1 L1 t −∞ (v1 (t̃) − vIN (t̃))dt̃ = 0 (12.288) for Node #1, and C2 dv2 (t) dt − dvIN (t) dt 1 1 + (v2 (t)−v1 (t))+ L2 R t −∞ v2 (t̃)dt̃−iIN = 0 (12.289) for Node #2. To treat these equations simultaneously, we use Equation 12.288 to determine v2 in terms of v1 , and then substitute the result vIN iL1 + vC2 L1 C2 Node 2 Node 1 vIN + v1 - R + vC1 - C1 v2 F I G U R E 12.63 A fourth-order circuit. iL2 L2 iIN 691h into Equation 12.289. This yields v2 (t) = RC1 d4 v1 (t) + dt4 + 1 RC1 1 RC1 L2 C2 1 d3 vIN (t) dt3 RC1 dv1 (t) dt + + L1 d3 v1 (t) dt3 RC2 1 1 + dt d2 vIN (t) dt2 L1 C1 t −∞ dv1 (t) RC2 L1 C1 + 1 R + v1 (t) + (v1 (t̃) − vIN (t)(t̃))dt̃ 1 L1 C 1 + L1 C1 L2 C 2 dt2 1 v1 (t) = dvIN (t) RC2 L1 C1 vIN (t) + d2 v1 (t) L2 C2 L1 C 1 L2 C2 + 1 1 1 + (12.290) 1 dt RC1 C2 + d2 iIN (t) dt . (12.291) Note that in deriving Equation 12.291 we differentiated Equation 12.289 twice and divided it by RC1 C2 prior to the substitution of Equation 12.290. Finally, to complete the node analysis, we solve Equation 12.291 for v1 , substitute the result into Equation 12.290 to determine v2 , and then use the two node voltages to determine any other branch variables of interest. For brevity, however, we will not carry out these remaining steps. Instead, we note that to do so requires initial conditions for v1 , and its first, second, and third derivatives. Most likely, this information will be determined from the state variables specified at the initial time, which takes additional work. Consider next a state-variable analysis of the circuit shown in Figure 12.63. To carry out this analysis we determine the state equation for each capacitor and inductor. This yields, C1 C2 dvC1 (t) dt dvC2 (t) dt = iC1 (t) = = iC2 (t) = L1 L2 691i 1 R 1 (vIN (t) − vC1 (t) − vC2 (t)) + iL1 (t) (12.292) (vIN (t) − vC1 (t) − vC2 (t)) + iL2 (t) − iIN (t) (12.293) R diL1 (t) dt diL2 (t) dt = vL1 (t) = vIN (t) − vC1 (t) (12.294) = vL2 (t) = vIN (t) − vC2 (t). (12.295) These equations may be summarized in state-space form as vC1 (t) v (t) C2 d = dt iL1 (t) iL2 (t) 1 RC1 − 1 RC2 −1 L1 1 RC1 − 1 RC2 1 C1 0 0 1 C2 0 0 0 −1 L2 0 − + 1 RC1 1 RC2 1 L1 1 L2 − 0 vC1 (t) v (t) C2 0 iL1 (t) 0 iL2 (t) vIN (t) . 0 iIN (t) 0 1 C2 (12.296) Finally, to complete the state-variable analysis, we solve Equation 12.296 for the states, and then use them to determine any other branch variables of interest. For brevity, however, we will not carry out these remaining steps. Instead, we note that to do so requires an initial condition for each state. To close this section, it is again worth mentioning that both analyses predict the same behavior for the circuit shown in Figure 12.63. The only difference is that they do so in terms of different sets of variables, and through different mathematical mechanics. Thus, the important message here is that both analyses are applicable to higher-order systems. 691j 13.4.3 T H E B O D E P L O T : S K E T C H I N G T H E FREQUENCY RESPONSE OF GENERAL FUNCTIONS * Sections 13.4.1 and 13.4.2 demonstrated the ease with which we can sketch the frequency response of simple circuits by observing their behavior at low frequencies and high frequencies. Things get more complicated for a network with several inductors or capacitors. This section discusses a simple and intuitive method called Bode plots for sketching the frequency response of more general circuits. The Bode method uses the insight gained from Sections 13.4.1 and 13.4.2 that the frequency response plots can be closely approximated by straight line segments derived from the asymptotic behavior of the transfer functions. The method proceeds as follows: First, write the relationship (Equation 13.46, for example) in the form of a system function, the ratio of the complex amplitude of the response to the complex amplitude of the input: H(s) = Response Input . (13.91) In general, the system function H(s) will be the ratio of two polynomials: H(s) = am sm + am−1 sm−1 + · · · + a1 s + a0 bn sn + bn−1 sn−1 + · · · + b1 s + b0 (13.92) where the coefficients ai and bi are real numbers since our circuit parameters are real numbers. We saw one example of this in Equation 13.64. We can factor the numerator and denominator polynomials and write H(s) = K1 (s − z1 )(s − z2 ) · · · (s − zm ) (s − p1 )(s − p2 ) · · · (s − pn ) (13.93) where K1 is a constant and z1 , z2 , . . . , zm are the roots of the numerator polynomial, and p1 , p2 , . . . , pn are the roots of the denominator polynomial.9 9. Because the system function goes to zero when s = zi , the roots of the numerator, z1 , z2 , . . . , zm , are called the zeros, definition of the system function. Similarly, the roots of the denominator, p1 , p2 , . . . , pn are called the poles of the system function. The system function goes to infinity when s takes on the value of one of the poles (in other words, when s = pi ). When one or more of the zi s or pi s is zero, the system is said to have zeros or poles at the origin. The poles and zeros of a system function are important system parameters because they characterize the general behavior 741a In general, some of the roots of the numerator or the denominator polynomials can be zero. Furthermore, the roots of the numerator and denominator polynomials can also be complex. If any of the roots are complex, then they must appear in complex conjugate pairs, so that the overall system function remains real. We will rewrite Equation 13.93 into the following standard form to reflect these facts: Ko sl (s + a1 )(s + a2 ) · · · s2 + 2α1 s + ω12 · · · H(s) = . (s + a3 )(s + a4 ) · · · s2 + 2α2 s + ω22 · · · (13.94) In Equation 13.94, we have combined complex conjugate pairs into quadratic terms of the form (s2 + 2αs + ω2 ). Thus all the remaining ai values are real. The sl term, where l can be positive or negative, reflects the case where the roots in Equation 13.93 are zero. We will now show that it is possible to sketch without formal calculation the general shape of H(s) as a function of frequency. More precisely, we can make an approximate sketch of the magnitude and phase of H(s) as a function of the input frequency ω. The resulting pair of graphics representing an approximate sketch of the frequency response is called a Bode plot, in honor of the Bell Laboratories engineer who devised it to study stability in feedback amplifiers.10 The Bode plot is an approximation of the frequency response and accordingly has two parts: a sketch of the log magnitude of H( jω) versus logω and a sketch of the angle of H( jω) versus logω. These coordinates are chosen because they facilitate straightforward construction of the frequency response graphs even for complicated functions without the use of a computer. Taking the magnitude and log on both sides of Equation 13.94, log|H(s)| = log Ko + log |s| + log |s| + · · · (l terms)+ log |s + a1 | + log |s + a2 | + · · · − log |s + a3 | − log |s + a4 | + · · · log |s2 + 2α1 s + ω12 | + · · · − log |s2 + 2α2 s + ω22 | + · · · (13.95) of the system. A detailed discussion of system analysis using poles and zeros is beyond the scope of this book. 10. Bode, H.W., Network Analysis and Feedback Amplifier Designs, Van Nostrand, New York, 1945, Chapter 15. 741b and for the phase ∠H(s) = ∠Ko + ∠s + ∠s + · · · (l terms)+ ∠(s + a1 ) + ∠(s + a2 ) + · · · − ∠(s + a3 ) − ∠(s + a4 ) − · · · + ∠(s2 + 2α1 s + ω12 ) + · · · − ∠(s2 + 2α2 s + ω22 ) − · · · (13.96) Notice that there are four types of terms in the magnitude and phase equations: 1. The Ko constant term, 2. the s terms, 3. terms of the form (s + a), and 4. quadratic terms of the form (s2 + 2αs + ω2 ), which have complex roots. This gives us a simple way of approximating the magnitude and phase curves of the frequency response plot. First, draw the individual magnitude and angle curves for each of the four types of terms in the numerator and denominator of Equation 13.94. Then, construct the overall magnitude and phase plots by simply adding together the individual curves. Let us now address each of the four terms: 1. The Ko constant term. We saw how to draw the frequency response of constant terms in Section 13.4.1. Essentially constant terms result in horizontal lines on the magnitude plot and have a phase of zero. 2. The s terms. Terms of the form s and 1/s (if l is negative) were also plotted in Section 13.4.1. We saw that each of these terms result in lines of +1 or −1 slope on the log magnitude plot and contribute to a phase of 90◦ or −90◦ , respectively. 3. Terms of the form (s + a). Section 13.4.2 addressed terms of the form (s + a). We showed that the magnitude part of the frequency response of these terms is approximated by two straight lines corresponding to the low and high frequency asymptotes meeting at the break frequency a. Accordingly, Bode plots result in a series of straight line segments attached together at the break frequencies. The phase plot also uses low- and high-frequency asymptotes and passes through 45◦ at the break frequency a. For more accuracy, the phase curve can be approximated by a straight line that passes through 45◦ at the 741c break frequency a, and meets the low- and high-frequency asymptotes at 0.1 times the break frequency (0.1a) and 10 times the break frequency (10a), respectively. 4. Quadratic terms of the form (s2 + 2αs + ω2 ) with complex roots. Although not as straightforward, it is possible to sketch frequency response plots for system functions of the form (s2 + 2αs + ω2 ), where the roots are complex. However, we will defer a further discussion on plotting Bode plots for complex roots to Section 14.4. For now, we will focus on real roots. 741d e x a m p l e 13 .5 b o d e p l o t f o r s e r i e s r l c i r c u i t Let us sketch the Bode plot for the RL circuit of Figure 13.11. From Equation 13.47, the system function here is a voltage ratio: H( jω) = Vo = Vi R/L jω + R/L . (13.97) To make the example specific, let us assume that the time constant L/R has a value of 50 msec. Thus the break frequency is at a= R L = 20 rad/s and the system function becomes H( jω) = 20 jω + 20 . (13.98) The system function has two terms: a constant term and a term of the form (s + a). Figures 13.26 and 13.27 show the construction of the magnitude and phase plots, respectively. The dashed lines in Figures 13.26c and 13.27c form the composite Bode plot, and are obtained by simple subtraction of Figures 13.26b from Figure 13.27a. For reference, the solid lines show the true magnitude and phase functions. Note that at the break frequency, the true magnitude is given by: |H( jω)| = 1/1.41 (13.99) = 0.707. The principal advantage of the Bode plot is that the composite magnitude asymptotes for system functions that can be written in the form of Equation 13.94 are always lines of integer slope in log space. Further, any system function that can be written as a ratio of polynomials in ω (regardless of whether the roots are real or complex) must approach at both low and high frequencies ( jω)n , where n is some integer. Hence the magnitude asymptotes on Bode plots for both small and large ω must be straight lines of integer slope in log space, and the phase must approach a multiple of 90◦ . 742a 3 100.00 2 10.00 1 1.00 0 0.10 -1 log |R/L |R/L| log scale 1000.00 0.01 10-1 100 101 102 103 ω 1000.00 3 100.00 2 10.00 1 1.00 0 0.10 -1 log |jω + R/ |jω + R/L| log scale (a) 0.01 -1 10 F I G U R E 13.26 Magnitude curve of the Bode plot for RL circuit: (a) the magnitude curve for R/L; (b) the magnitude curve for jω + R/L; (c) the composite magnitude curve obtained by subtracting (b) from (a). 100 101 102 103 | |||| | | | | 100.00 | |||| | | | | 10.00 | |||| | | | | 1.00 | |||| | | | | 0.10 3 ω log |H| 1000.00 |||| | | | | |H| log scale (b) 2 1 0 -1 | | 0.01 | 10-1 | | | | | | | || | | | | | | | || 100 101 (c) | | | | | | | || 102 | | | | | | | || 103 ω 742b <R/L <R/L + jω <H F I G U R E 13.27 Phase curve of the Bode plot for RL circuit: (a) the phase curve curve for R/L; (b) the phase curve for jω + R/L; (c) the composite phase curve obtained by subtracting (b) from (a). 742c 90 70 50 30 10 -10 -1 10 -30 -50 -70 -90 90 70 50 30 10 -10 -1 10 -30 -50 -70 -90 90 70 50 30 10 vv -10 -1 10 -30 -50 -70 -90 100 101 102 103 ω (a) 100 101 102 103 ω (b) 100 101 102 103 ω (c) e x a m p l e 13 . 6 a n o t h e r bode plot e x a m p l e To illustrate the Bode method for more general transfer functions, let us sketch the Bode plot for the following transfer function: H( jω) = 0.025(1000 + jω) 100 + jω . (13.100) The specific circuit that results in this transfer function is not relevant to us right now, but will be discussed later in Section 13.6. The system function has three terms: a constant term, and two terms of the form (s + a). The Bode construction of the magnitude curve of the frequency response for the above transfer function is shown in Figure 13.28. The corresponding phase construction is shown in Figure 13.29. For reference, the actual frequency response generated using a computer is shown using solid curves. 742d | ||||| | | | | 10-1 | ||||| | | | 10 ||||| | | | |0.025| 0 ||||| | | | 10 | 1 ||||| | | | 102 | 103 ||||| | | | 104 4 3 2 1 0 -1 | | 10-2 | -2 | 100 | ||||| | | | | | 1000 + jω | ||||| | | | ||||| | | | 10-1 | 100 ||||| | | | 10 | 1 ||||| | | | | 10-2 | | | | | | | || | | 101 | | | | | || | | 102 | | | | | || | | 103 | | | | | || 104 ω 4 3 2 1 0 -1 -2 | 100 | | | | | | || 10 | 1 | | | | | | || 102 | | | | | | | || 103 | | | | | | | || 104 ω 104 4 3 3 10 2 2 101 1 100 0 10-1 -1 10 | 100 + jω | F I G U R E 13.28 Construction of the magnitude curve of the Bode plot. The composite magnitude curve for the transfer function is obtained by subtracting the magnitude curve of (1000 + jω) from the sum of the magnitude curves of 0.025 and (100 + jω). 102 | 103 ||||| | | | 104 | -2 -2 10 0 101 10 102 103 104 |H| ω 104 4 3 3 10 2 2 101 1 100 0 10 -1 10 -1 -2 10-2 100 101 102 103 104 ω 742e <0.025 90 60 30 0 -30 -60 <1000 + jω -90 100 101 102 103 104 ω 90 60 30 0 -30 -60 <100 + jω -90 | 100 101 102 103 104 ω 90 F I G U R E 13.29 Construction of the phase curve of the Bode plot. 60 30 0 -30 -60 <H -90 100 101 102 103 104 ω 90 60 30 0 -30 -60 -90 100 101 102 103 104 ω 742f e x a m p l e 13 .7 maximizing power transfer using a t r a n s f o r m e r One use of the transformer discussed in Section 9.3.4 is to match impedances between two halves of a circuit, and in doing so to maximize the power transfered from a source to a load. For example, consider connecting a source having a 1-V-peak and 50- Thévenin equivalent operating in the sinusoidal steady state to a 1800- load as shown in Figure 13.56. In the case of this direct connection, the voltage across the load is 1800 1850 1 V sin(ωt), and so the time average power delivered to the load is approximately 0.26 mW; note that the time average of sin2 (ωt) is 0.5. Next, consider the circuit shown in Figure 13.57. In this circuit, an ideal transformer having N1 primary turns and N2 secondary turns is inserted between the source and load; with help from Figure 9.30, an equivalent model of this circuit is shown in Figure 13.58. 50 Ω F I G U R E 13.56 A source connected directly to a load. 1 Vsin (ωt) + RL = 1800 Ω - Source Load 50 Ω F I G U R E 13.57 A source connected to a load through a transformer. 764a 1 V sin (ωt) + - N1 N2 1800 Ω 50 Ω i1 i2 + + 1 V sin (ωt) + - + v1 N ------2 i2 N1 - - v2 N -----2 v1 N1 1800 Ω F I G U R E 13.58 An equivalent circuit model of the circuit in Figure 13.57. - To analyze this new circuit, consider first the secondary side of the transformer. There, i2 = − N2 v1 N1 RL , (13.175) and so at the primary side of the transformer, i1 = − N2 N1 i2 = N22 v1 N21 RL . (13.176) Thus, as viewed from the primary side of the transformer, the transformer and resistor together behave as a resistor having resistance (N1 /N2 )2 RL . In other words, the transformer has transformed the resistance of the load resistor by the ratio of (N1 /N2 )2 . It is straightforward to show that any secondary-side impedance is transformed to the primary side by the same ratio. Similarly, a primary-side impedance is transformed to the secondary side by a ratio of (N2 /N1 )2 . Let us now determine the ratio N2 /N1 that maximizes the power delivered to the load. To do so, we use the circuit in Figure 13.59, in which the transformer and load resistor 50 Ω i1 + 1 V sin (ωt) + - 2 v1 N1 ------ 1800 Ω N2 F I G U R E 13.59 An equivalent circuit model with the transformer and load resistor replaced by the effective load resistor. - 764b are replaced by the effective load resistor having resistance (N1 /N2 )2 1800 . In this case, the voltage across the effective load resistor is 1800N21 /N22 50 + 1800N21 /N22 1 V sin(ωt), and the average power delivered to the effective load resistor is 0.5 1800N21 /N22 (50 + 1800N21 /N22 )2 W. Since the power into the primary side of an ideal transformer instantaneously exits the secondary side of the transformer, this is the power delivered to the actual load. This power is maximized for 50 = 1800N21 /N22 , or N2 /N1 = 6, in which case the resistance of the effective load resistor is 50 , and the power delivered to the load resistor is 2.5 mW. Thus, to achieve maximum power transfer, the resistance of the load must match that of the source, and the ideal transformer performs this matching. 764c e x a m p l e 13 . 8 n o n - i d e a l t r a n s f o r m e r s Real transformers are never ideal, and at times their nonidealities are important. Such nonidealities include the resistance of the coils, the leakage inductance of the coils and the magnetizing inductance of the core. These non-idealities can be added to the model shown in Figure 9.29 to arrive at the model shown in Figure 13.60; note that the transformer symbol in Figure 13.60 represents the original ideal transformer from Figure 9.29. In Figure 13.60, R1 and R2 represent the resistances of the two coils, and LL1 and LL2 represent the leakage inductances of the two coils. The inductance L0 represents the magnetizing inductance of the core given a single-turn coil, and so must be multiplied by N21 if placed on the primary side of the ideal transformer, or by N22 if placed on the secondary side of the ideal transformer. In either case, it represents the effect of the non-infinite permeability of the core. Let us now examine the effect of the magnetizing inductance on the results of Example 13.7. Consider the case of N1 = 100, N2 = 600, and L0 = 8 µH, as might be the case for a small-signal transformer. This case is shown in Figure 13.61. Following the results of Example 13.7, we can replace the combination of the ideal transformer and the 1800- load resistor with a 50- resistor, and compute the magnitude of v1 to be " " " " " " " " ( jω 80 mH)(50 ) ω " " " 1V = " |v1 | = "" " 1V. " " 4ω2 + (625 rad/s)2 " 50 + ( jω 80 mH)(50 ) Ideal Transformer LL1 R1 LL2 N1 N12L0 R2 F I G U R E 13.60 A non-ideal transformer. N2 50 Ω + + 1 V sin (ωt) + - v1 - N12L0 = 80 mH N1 = 100 N2 v 2 = 600 1800 Ω F I G U R E 13.61 Power transfer with a non-ideal transformer. - 764d Thus, for ω 312.5 rad/s, that is, for source frequencies well above 50 Hz, the voltage magnitude across the transformer primary is approximately 0.5 V peak. In this case, the maximum power is transfered to the resistor load. However, as the frequency goes below 50 Hz, the inductor behaves like a relative short circuit in comparison to the 50- resistance of the transformed load resistor, and so the magnitude of v1 drops. The magnitude of v2 and the power delivered to the load drops accordingly. In general, the time-average power delivered to the load resistor is that which flows into the primary of the ideal transformer, namely: ω2 4ω2 + (625 rad/s)2 764e 10 mW. 14.4 T H E B O D E P L O T F O R R E S O N A N T FUNCTIONS * In this section, we will extend the Bode method for plotting approximate frequency responses (Section 13.4.3) to resonant system functions. Recall that a Bode plot is an approximate sketch of the frequency response, which can be drawn by intuition without the use of a computer. Section 13.4.3 discussed a simple and intuitive method for sketching the Bode plots for general circuits. The method is based on the intuition that a general system function can be written in the form shown in Equation 13.94, which contains four types of terms: 1. A constant term, 2. s terms, 3. real terms of the form (s + a), and 4. quadratic terms of the form (s2 + 2αs + ωo2 ) with complex roots. The Bode method proceeded by drawing the individual magnitude and angle curves for each of the four types of terms in the numerator and denominator of Equation 13.94. The magnitude curves are drawn on log-log scales and the phase curves on log-linear scales. Observing that log-magnitudes and phases add (Equations 13.95 and 13.96), the method concluded by constructing the overall magnitude and phase plots by simply adding together the individual curves. Section 13.4.3 discussed how the real terms (types 1, 2, and 3) could be plotted. This section discusses how we can plot type 4 terms, namely, quadratic terms with complex roots. Once we know how to sketch the plots for each of the four types of terms, we can then sketch any general system function by superposition (see Section 13.4.3). The Bode plot for a quadratic term with complex roots is easily drawn from the insight gained in Section 14.2. There we showed that the low- and highfrequency magnitude and phase asymptotes of second-order system functions yielded insight into the general form of response. It turns out that for a quadratic term of the form (s2 + 2αs + ωo2 ), the low- and high-frequency asymptotes can be combined to yield a good approximation of the actual curve. Accordingly, the following is a procedure for sketching the form of the frequency response for a quadratic term of the form s2 + 2αs + ωo2 , which has complex roots: Magnitude Plot 1. Sketch the low-frequency asymptote. For our quadratic term, the low-frequency asymptote is given by the horizontal line: |H( jω)| ≈ ωo2 . 808a <H (degrees) |H| 1010 109 108 107 106 102 103 104 105 10 6 Frequency (rad/s) 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 102 O 103 104 (a) F I G U R E 14.28 Sketching the frequency response of the resonant function s2 + 2αs + ωo2 . 105 10 6 Frequency (rad/s) (b) 2. Sketch the high-frequency asymptote. The high-frequency asymptote is given by: |H( jω)| ≈ ω2 . This asymptote appears as a line of slope 2 in log-log scales. Figure 14.28a shows these two asymptotes in dashed lines, assuming ωo = 104 α = 500. For comparison, the actual magnitude is also shown as a solid curve. The two straight line asymptotes intersecting at ωo are a good approximation of the magnitude curve. It is also clear from Figure 14.28a that our approximation and the actual curve differ in the vicinity of ωo , and amount by which they differ relates to the peakiness of the curve, which in turn relates to the value of Q. For ωo = 104 and α = 500, Q= ωo 2α = 10. Figure 14.29 plots the frequency response for several values of Q (keeping ωo constant). It is easy to see that the difference between the 808b <H (degrees) |H| 1010 109 0.5 1 2 | 108 5 10 107 20 Q O Q 0.5 1 2 510 20 | 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 102 106 102 103 104 105 106 Frequency (rad/s) 103 (a) 105 106 Frequency (rad/s) (b) actual magnitude (solid curves) and the approximate value from the Bode splot (dashed curve) at ωo becomes substantial for large values of Q. The exact difference is computed in Equation 14.74. 104 F I G U R E 14.29 Frequency response of s2 + 2αs + ωo2 for different values of Q. Phase Plot 1. Sketch the low-frequency asymptote. The low-frequency asymptote is given by: ∠H( jω) ≈= 0◦ . 2. Sketch the high-frequency asymptote. The high-frequency asymptote is given by: ∠H( jω) ≈= 180◦ . 3. Mark ∠H( jωo ) = 90◦ , the angle of the system function at the frequency ωo . 4. Draw a smooth line starting with the low-frequency asymptote, passing through 90◦ at ωo , and finishing off at the high-frequency asymptote. Figure 14.28b shows these two asymptotes in dashed lines. For comparison, the actual phase curve is also shown as a solid line. 808c e x a m p l e 14 .6 b o d e p l o t e x a m p l e Let us sketch the frequency response of the admittance of the second-order circuit in Figure 14.25 using the Bode method. From Equation 14.66, the desired system function is H(s) = Iz Vz = s2 + s RL + s C + 1 LC R LC . For L = 1 mH C = 10 µF R=1 we get ωo = 104 rad/s, and Q = 10. Since Q > 0.5, the roots of the characteristic equation are complex and the circuit is resonant. Substituting the numerical quantities into our system function, we get H(s) = s2 + 1000s + 108 105 (s + 103 ) . The system function has three terms: a constant term, a term of the form (s + a), and a quadratic term of the form (s2 + 2αs + ωo2 ). The Bode construction of the magnitude curve of the frequency response for the preceding transfer function is shown in Figure 14.30. The corresponding phase construction is shown in Figure 14.31. For reference, the actual frequency response generated using a computer is shown using solid curves. 808d 1012 12 1010 10 108 8 106 6 104 4 102 2 100 0 10-2 -2 102 |s + 103| 103 104 105 106 ω |H| |105| |s2 + 1000s + 108| 1012 12 1010 10 108 8 106 6 104 4 102 2 100 0 10-2 -2 102 103 104 105 106 ω 1012 12 1010 10 108 8 106 6 104 4 102 2 100 0 10-2 -2 102 101 1 100 0 10-1 -1 10-2 -2 102 103 104 105 106 ω 103 104 105 106 ω 103 104 105 106 ω <H <s2 + 1000s + 108 102 102 103 104 105 106 ω 180 150 120 90 60 30 0 -30 -60 -90 101 102 103 104 105 106 ω | 180 150 120 90 60 30 0 -30 -60 -90 101 180 150 120 90 60 30 0 -30 -60 -90 | 101 | | 180 150 120 90 60 30 0 -30 -60 -90 101 <s + 103 <105 F I G U R E 14.30 Construction of the magnitude curve of the Bode plot. The composite magnitude curve for the transfer function is obtained by subtracting the sum of the magnitude curves of 105 and (s + 103 ) from the magnitude curve of (s2 + 1000s + 108 ). 102 103 104 105 106 ω F I G U R E 14.31 Construction of the phase curve of the Bode plot. 808e 15.4.4 G E N E R A L I Z A T I O N O N I N P U T R E S I S T A N C E * It is obviously of some importance to the circuit designer to know whether feedback is going to increase or decrease the effective input resistance of a circuit. We can generalize from the two circuits we have examined to state that the effect of feedback on input resistance depends on the circuit topology. If the source current and the current through the feedback resistor and the current through the Op Amp input resistor ri all sum at a common node as in Figure 15.12, then the effective input resistance is very low, as shown in Equations 15.36 and 15.38. (Remember, here we are referring to Ri , the resistance of the Op Amp circuit to the right of Rs .) Equation 15.36 is in fact a general result: The input conductance for any feedback circuit with this input topology (neglecting ri ) is the conductance without feedback, here 1/(Rf + rt ), multiplied by 1 + A. If, on the other hand, the source and the Op Amp input resistor are in series, forming a loop with the feedback resistor, as in Figure 15.14, the effective input resistance of the circuit will be very high. In a word, if at the Op Amp input we sum currents at a node, the circuit input resistance is low, if we sum voltages in a loop, the input resistance is high. 855a 15.6.5 S A L L E N - K E Y F I L T E R This section introduces a lowpass filter called the Sallen-Key filter. Its circuit and impedance model are shown in Figure 15.25. Let us focus on sinusoidal inputs and use the impedance method to obtain its input-output relationship. First, notice that the portion of the circuit within the dashed box is a non-inverting connection of the Op Amp with gain: G=1+ R1 R2 . (15.94) C vi v1 R v2 + vo R - C R1 R2 (a) Circuit F I G U R E 15.25 The Sallen-Key circuit. 1/Cs R R V1 + V2 Vo - 1/Cs Vi R1 R2 (b) Impedance model 866a Thus, for the purpose of analysis, we can replace the circuit within the dashed box with an amplifier whose gain is G. Therefore, we can write Vo = GV1 . (15.95) Applying KCL for node V1 V2 − V 1 = R V1 1/Cs , which simplifies to: V2 = (RCs + 1)V1 . Substituting for V1 in terms of Vo from Equation 15.95, we get V2 = RCs + 1 G Vo . (15.96) Now, KCL for node V2 yields, Vi − V 2 V2 − V1 = R R V2 − Vo + 1/Cs . (15.97) Substituting for V1 and V2 in terms of Vo from Equations 15.95 and 15.96, we get Vi − RCs+1 Vo G R = RCs+1 G Vo − 1 V G o R + RCs+1 G Vo − Vo 1 Cs . (15.98) We can simplify Equation 15.98 and obtain the following expression relating the output voltage to the input voltage: H(s) = Vo (s) Vi (s) = G R 2 C 2 s2 + RCs(3 − G) + 1 . (15.99) As a specific example, let us draw the frequency response for the filter transfer function for RC = 1 and R1 = R2 . For these values, G = 2 and the 866b 1 0.8 0.6 Imag Axis 0.4 0.2 0 F I G U R E 15.26 Pole-zero plot of the Sallen-Key filter. -0.2 -0.4 -0.6 -0.8 -1 -1.5 -1 -0.5 Real Axis 0 0.5 transfer function is given by: H(s) = 2 s2 +s+1 (15.100) or, factoring the denominator, H(s) = 2 . (s + 1/2 + j 3/4)(s + 1/2 − j 3/4) (15.101) The transfer function represents a second-order filter. The expression in the 3/4 and denominator has a pair of complex conjugate roots: −1/2 + j −1/2 − j 3/4. In terms of the pole-zero nomenclature introduced in Section 13.4.3, the transfer function has two polesand no zeros. Thepoles are a complex conjugate pair located at −1/2 + j 3/4 and −1/2 − j 3/4. Figure 15.26 depicts the pole locations using X’s in the complex plane. (When zeros exist, their locations are depicted using circles.) We can now plot the frequency response as shown in Figure 15.27 by substituting s = jω in the transfer function: H( jω) = 2 ( jω)2 + jω + 1 (15.102) 866c Magnitude 101 100 10-1 F I G U R E 15.27 Frequency response for the Sallen-Key filter. Phase (degrees) 10-2 10-1 100 Frequency (radians) 101 100 Frequency (radians) 101 0 -50 -100 -150 -200 10-1 or, in terms of the factored transfer function, H( jω) = 2 . ( jω + 1/2 + j 3/4)( jω + 1/2 − j 3/4) (15.103) As before, the frequency response in Figure 15.27 plots the magnitude and the phase of H( jω) versus the frequency ω. 866d 15.9 T W O - P O R T S * It should be obvious by now that circuits with dependent sources can perform much more interesting and useful signal processing than those constructed solely from two-terminal resistive elements. But inclusion of dependent sources has brought about a modest increase in circuit complexity, so it is useful at this point to generalize some of the concepts introduced in previous chapters. In particular, let us examine how to generalize the Thévenin calculations to three-terminal or four-terminal systems. We start with a linear network containing resistors, voltage sources, and current sources as we did in Figure 3.55, but now we assume two pairs of external terminals, as shown in Figure 15.36. This network is called a two-port, or a two-terminal-pair network. For the purposes of the present discussion, it doesn’t matter whether the two negative leads are tied together or go to some common ground, or both terminal pairs are floating with respect to ground. We wish to find a two-port Thévenin equivalent of this network. The derivation is a simple extension of the method in Section 3.6.1. We apply current sources at each of the ports, as in Figure 15.37a, then solve the problem by superposition. We first set all the independent sources, both internal and external, to zero except i2 , and measure the resulting v2a as in the subcircuit of Figure 15.37b. Because there is nothing left of the network except resistors (and possibly dependent sources), v2a must be linearly dependent on i2 without offsets. In other words, the ratio v2a /i2 is a pure resistance, a Thévenin-equivalent output resistance: RThout = v2a i2 . i2 i1 + v1 - - + + v2 - F I G U R E 15.36 Linear two-port network. (15.114) Then we set i1 and i2 to zero, leave the internal sources active, as in Figure 15.37c, and measure v2b = v2oc , (this is what we previously called the open-circuit voltage). Finally we set i2 and the internal sources to zero, leaving i1 active, and measure v2c , which must be linearly dependent on i1 , and hence can be written as v2c = i1 R21 . (15.115) This is clearly a dependent source relationship: an output voltage dependent on an input current. Now by superposition, the total output voltage is the sum of these three terms: v2 = i1 R21 + i2 RThout + v2oc . (15.116) A completely analogous argument yields for the input terminals: v1 = i1 RThin + i2 R12 + v1oc (15.117) 872a + + + v1 - i1 - i2 v2 - (a) i1 = 0 + V=0 I=0 v2a v2a RThout = ------i2 (b) F I G U R E 15.37 Two-port calculations. + + - i1 = 0 - + v2b - (c) + V=0 i1 I=0 (d) 872b v2c v2c R21 = ------i1 i2 i1 + v1a V=0 - i2 = 0 I=0 v1a RThin = ------i1 (a) + + V1b = v1oc - - i2 = 0 F I G U R E 15.38 Two-port input calculations. (b) + V=0 v1c - i2 I=0 (c) v1c R12 = ------i2 where RThin , v1oc , and R12 are measured or calculated using the subcircuits in Figures 15.38a, 15.38b, and 15.38c, respectively. Equations 15.116 and 15.117 taken together, are a complete representation of the network as viewed from the two terminal pairs or two ports. It is common practice in linear network theory to assume that there are no independent sources inside the network. In this case a rather simple generalization of the Thévenin equivalent circuit emerges. Equations 15.116 and 15.117 simplify to v1 = i1 RThin + i2 R12 (15.118) v2 = i1 R21 + i2 RThout (15.119) 872c and a simple circuit interpretation is now apparent. The term i2 R12 in the equation for the input port, Equation 15.118, is a voltage, dependent on the current at the output. That is, it is a dependent voltage source, under the control of i2 . The first term in Equation 15.118 is the Thévenin input resistance. Hence the equation can be represented in circuit form by the left half of Figure 15.39a. The expression for the output port, Equation 15.119 has similar structure, except the role of input and output variables have been reversed. Hence the right half of Figure 15.39a. The circuits and equations for calculating the four parameters (called z parameters in linear network theory) are given in Figures 15.37b and 15.37d, and Figures 15.38a and 15.38c. If we had chosen to drive the two-port with two voltage sources, rather than two current sources as in Figure 15.37, then from Section 3.6.2, the twoport version of the Norton equivalent would have emerged. The equations analogous to Equations 15.118 and 15.119 are i1 i1 = yin v1 + y12 v2 (15.120) i2 = y21 v1 + yout v2 (15.121) Rthout Rthin i2 + + i2R12 v1 + + - - v2 i1R21 - (a) z parameter model F I G U R E 15.39 z and y parameter models. i1 i2 + v1 + y21v1 yin v2 yout y12v2 - (b) y parameter model 872d where the Y terms are conductances for resistive circuits. The circuit equivalent, called the y parameter model, is shown in Figure 15.39b. The expressions for each of the y parameters are readily derivable from Equations 15.120 and 15.121, or from first principles, as in Figures 15.37 and 15.38, or by a linear transformation on the z parameters. Two other representations, the g parameters and the h parameters, arise if one excites the two-port with a voltage source at one port and a current source at the other. All four representations are related by linear transformations. It is helpful to re-examine the calculation of Op Amp input and output resistance in Section 15.4 from the more general two-port point of view of this section. Because in Figures 15.11 and 15.12 we used a test voltage source at the input and a test current source at the output, we in fact were calculating the g-parameters, defined in Figure 15.40a. To complete the calculation, we assume that in the Op Amp circuit, Figure 15.12, the reverse signal flow through the circuit is negligibly small. Hence g12 in Figure 15.40a is zero. Also, from Figure 15.12 the forward dependent source g21 is approximately A, if we neglect the drop in rt caused by current through Rf . On this basis the g-parameter representation for the inverting Op Amp connection is as shown in Figure 15.40b, assuming Rs is external to this model. It is now (finally) possible to justify the omission of the ±12 V power supplies in all calculations in this chapter. In terms of a two-port model, the i1 g22 i2 + + + g11 v1 g12i2 - v2 g21v1 - i1 = g11v1 + g12i2 v2 = g21v1 + g22i2 (a) g parameters F I G U R E 15.40 g parameter model for inverting Op Amp. Ro v+ + + 1/Ri - A(v+ - v-) vo - v(b) 872e power supplies would produce no measurable voltage or current at either the input or the output of the circuit, because of the balanced nature of the circuit in the active region. Hence inclusion of the power supplies would not change the model parameters we have just derived, so it is correct to neglect these supplies in all Op Amp active-region calculations. 872f 16.4.3 A S W I T C H E D P O W E R S U P P L Y U S I N G A D I O D E In this example, we will analyze the behavior of the diode-based switched power supply circuit shown in Figure 16.15. Notice that this circuit is similar to that in Figure 12.41, with the switch S2 replaced with a diode. As before, the purpose of the circuit is to convert the DC input voltage V to a different DC output voltage vOUT . The MOSFET in the circuit operates as a switch, and the square-wave input to the MOSFET is shown in Figure 16.16. As before, we are interested in determining the behavior of vOUT over time. As we will see shortly, the diode in the circuit also acts a switch, and results in an output waveform that is largely the same as that of the circuit in Figure 12.41. We will assume that the switch S1 has zero resistance associated with its ON state, and that the diode is ideal, so that the model in Figure 16.6 applies. Specifically, this means that the diode turns on and behaves like a short circuit when a positive current (iD ) flows through it. The diode turns off and behaves like an open circuit when the voltage (vD ) across it is negative. When the switch S1 is closed, it shorts the terminal connecting the diode and the inductor to ground. Assuming that vOUT is non-negative, the diode being reverse biased is off. The DC voltage V appears directly across the inductor as illustrated in Figure 16.17, and the inductor current iL ramps up. Since S1 is the on for time T, the inductor current builds up to iL = VT (16.34) L as shown in Figure 16.16. Meanwhile, if there is no applied load at vOUT , the capacitor voltage vOUT remains constant. Next, when S1 is opened, the inductor current cannot instantaneously go to 0. Instead, the current finds a path through the diode (thereby turning it on) and into the capacitor. In its ON state, the diode behaves like a short circuit, and so the driven LC circuit shown in Figure 16.18 results. The current iL in the iL L iD vOUT + vD vC + + V - S1 C - F I G U R E 16.15 A switched power supply circuit with diode and a switch. 918a TP One cycle S1 State CLOSED (ON) T OPEN (OFF) t Diode State Diode OFF Diode ON Diode OFF t F I G U R E 16.16 Switched power supply operation. iL VT -----L 0 t vC vC [n + 1] vC [n] 0 t LC circuit follows a sinusoidal pattern as illustrated in Figure 16.16. Because of the flow of current into the capacitor, its voltage vOUT starts to increase, and it too follows a sinusoidal pattern. As iL follows its sinusoidal pattern, it soon reaches zero and the positive voltage on the capacitor attempts to drive it negative. At this instant, the diode turns off and disconnects the capacitor from the rest of the circuit, so in the absence of a load, the capacitor maintains its voltage. 918b iL L + F I G U R E 16.17 The equivalent circuit when S1 is closed and the diode is open. S1 V - iL iD L vC + + C V - - F I G U R E 16.18 The equivalent LC circuit when S1 is open and the diode is ON. This cycle repeats, dumping some amount of charge into the capacitor each cycle. We can compute the increase in vOUT very quickly using an energy argument similar to that used in Example 12.4 as follows: At the end of the ramp, the inductor current is given by Equation 16.34, and so the energy stored in the inductor is given by: wM = V2 T2 . 2L Since the capacitor is charged by the inductor until iL becomes zero, the energy (wM ) stored in the inductor is transferred completely to the capacitor in each cycle. After n cycles, the energy stored in the capacitor becomes n times the energy transferred in a single cycle, plus any energy initially stored on the capacitor (say wE [0]): V2 T2 + wE [0]. 2L Unlike Example 12.4, the capacitor must start with vC = V, since it is connected by a diode instead of a switch to a voltage source. Unlike the switch, which can wE [n] = n 918c be forced to stay off, the (ideal) diode turns on if V is greater than vC . Therefore, wE [0] = 1 2 CV2 . Since wE [n] = CvOUT [n]2 /2, we can derive the voltage after n cycles as: vOUT [n] = V nT2 LC + 1. √ Substituting, ωo = 1/ LC, we have ! vOUT [n] = V nT2 ωo2 + 1. If nT2 ωo2 1, we get √ vOUT [n] = VTωo n. Finally, when a load is added to the circuit as shown in Figure 16.19, the capacitor begins to discharge through the load. Suppose we wish to maintain the voltage vOUT at a specified average value, say vREF , then in each cycle, we must arrange to have the capacitor charged up by the same amount of charge that it supplies to the load. This can be accomplished by using a feedback system as shown in Figure 16.20. In the circuit in Figure 16.20, the controller compares vOUT to vREF , and if vOUT falls below vREF , it increases the duration T for which the switch S1 is kept ON, thereby increasing vOUT . Conversely, the controller decreases the duration T if vOUT increases past the value of vREF . Thus, vOUT is kept close to vREF throughout. iL + L F I G U R E 16.19 Adding a load. + V - vC + S1 C - RL vOUT - 918d iL + L + V - S1 C vC + - vOUT Control RL vREF change T F I G U R E 16.20 Feedback system to maintain a voltage vREF at the load. - T TP t 918e 16.5 A D D I T I O N A L E X A M P L E S For review purposes, more examples of both piecewise linear and incremental analysis are given in the following subsections. No new material is presented, so readers who do not need additional practice can omit this section without loss of continuity. 16.5.1 P I E C E W I S E L I N E A R E X A M P L E : CLIPPING CIRCUIT The output voltage vo in the diode clipper circuit, shown in Figure 16.21a, will resemble the input voltage vi , except that the bottom of the waveform will be clipped off. The circuit has only one diode, so that the Thévenin solution method discussed in Chapter 3.6.1 can be used, but here we will use the method of assumed diode states. Assume that the diode in Figure 16.21 is ideal, then draw the two subcircuits, one with the diode OFF, and the other with the diode ON, as shown in Figures 16.21b and 16.21c. By inspection, the output voltage with the diode OFF is constant, because there is a fixed current IO flowing up through R. Thus vo1 = −IO R. (16.35) The current source and the voltage source are in series, so the voltage source has no effect on vo1 . Furthermore, when the diode is OFF, vi = vo1 + vD . (16.36) Because the diode is in the OFF state, vD must be negative. It follows that in the OFF state vi must always be more negative than −IO R. Next, when the diode is ON, the output is directly connected to the input: vo2 = vi . (16.37) In the ON state, vi must be more positive than −IO R. Hence the valid portions of the waveforms in the subcircuits are the darkened segments, and the complete output waveform is as shown in Figure 16.21d. As promised, the circuit has clipped off the bottom of the input wave. 16.5.2 E X P O N E N T I A T I O N C I R C U I T The circuit shown in Figure 16.22 produces an output voltage vOUT that is proportional to the exponential of the input voltage vIN for sufficiently large vIN . To analyze this circuit, assume that the Op Amp is ideal, the saturation current of the diode is Is = 10−12 A, and the temperature of the diode is approximately 29◦ C so that its thermal voltage is VTH = 26 mV. Because 918f IO + + vi - R vo vo1 (a) vi IO t iD = 0 + + vi - vD - + R -IOR vo1 (b) - Valid for vi < -IOR vo2 F I G U R E 16.21 Diode clipper. IO + + vi - vi = vo2 t - + vD = 0 R Valid for vi > -IOR -IOR vo2 (c) vo vo t -IOR (d) vi 918g R = 100 kΩ iD + F I G U R E 16.22 A diode-based exponentiation circuit. vIN + vOUT + - - the Op Amp is ideal, and used in a stable negative-feedback configuration, the voltage at the inverting terminal of the Op Amp is zero. As a result, iD = Is evIN /VTH − 1 = 10−12 A evIN /(26 mV) − 1 . For sufficiently large vIN , for example for vIN ≥ 120 mV, the exponential term dominates, and this relation simplifies to iD ≈ 10−12 A evIN /(26 mV) . Next, because the voltage at the inverting terminal of the Op Amp is zero, and because the current into that terminal is zero, the output voltage is given by vOUT = −RiD ≈ −10−7 V evIN /(26 mV) , which exhibits an exponential dependence on vIN . For example, for vIN = 200 mV, 300 mV, and 400 mV, vOUT = −0.219 mV, −10.3 mV, and −480 mV, respectively. 16.5.3 P I E C E W I S E L I N E A R E X A M P L E : L I M I T E R The circuit in Figure 16.23 is useful for making square waves out of sine waves, and for limiting the amplitude of an output waveform when the input waveform amplitude varies over a wide range. To analyze the circuit, we note that the Thévenin approach is not helpful, and a graphical solution might be messy because of the two diodes (not so, in fact, but that is not obvious yet). So resort to analysis by assumed diode states. The subcircuits for the four states, assuming an ideal-diode model, are shown in Figures 16.23b, 16.23c, 16.23d, and 16.23e 918h R D1 + V - + vi - D2 + V vo + - (a) Limiter circuit vo1 vi R + + +v OFF v- D1 OFF D2 vo1 + V V+ - + vi - +V t 0 -V (b) Both diodes OFF vo2 R + vi - + V - + OFF vo2 V + - +V t 0 (c) D1 ON F I G U R E 16.23 Diode limiter. vo3 R + OFF + V- + vi - V + vo3 - (d) D2 ON -V t 0 vo vi R + vi - ON + V - + ON - vo4 V + - (e) Both diodes ON vo 0 t (f) Complete waveform 918i along with the appropriate subcircuit output voltages, obtainable by inspection. From Figure 16.23b, vo1 = vi (16.38) because there is no current through R. When either diode is ON, the output voltage is independent of the source voltage vi . For D1 , ON, for example, vo2 = V. The fourth diode state, Figure 16.23e, cannot be reached with this topology, (assuming V is a positive quantity) because there is no value of vi that will force both diodes ON at the same time. Now we must identify the valid segments of these waveforms. In Figure 16.23b, both diodes are assumed OFF, so vd1 and vd2 must both be less than zero. Hence, using KVL: vi − V = vD1 < 0 (16.39) vi < V (16.40) −vi − V = vD2 < 0 (16.41) vi > −V. (16.42) Thus vi must be between −V and +V. Likewise vo1 , from Equation 16.38. This range of validity is indicated by the darkened segments of the waveform in Figure 16.23b. It follows that the complete output wave must be as shown in Figure 16.23f. If the peak amplitude of vi is ten or twenty times V, then vo is a reasonable approximation of a square wave. 16.5.4 E X A M P L E : F U L L - W A V E D I O D E B R I D G E Figure 16.24 shows one of the most common rectifier circuits found in electronic equipment, the full-wave diode bridge. We assume therefore that vi is a 60-Hertz sinusoid with 10-volt peak amplitude, and we wish to find the waveform vo across the output resistor. A full-blown assault using assumed diode states would yield 16 subcircuits, but it will turn out that only two of these are possible, suggesting a more insightful approach. Suppose that vi is a small positive voltage. Then current must flow down through the bridge. The only available path is D1 , RL , and D4 , because of the orientation of D3 and D2 . Similarly, for vi negative, current must flow up, and thus must follow the path D3 , RL , D2 . The two corresponding subcircuits, assuming ideal diodes, are shown in Figures 16.24b and 16.24c. Now, by inspection, for vi positive, vo = vi (16.43) vo = −vi . (16.44) and for vi negative, 918j D1 + vi - RL (a) + vi - D2 + vo - D3 + voA D3 OFF (b) Subcircuit for vi positive D1 OFF - D4 + vi - D1 OFF v + oB D4 OFF (c) Subcircuit for vi negative vi + vi - + voC - D3 OFF D4 OFF F I G U R E 16.24 Full-wave diode bridge. (d) D1 and D2 ON vo t t (e) All other subcircuits are degenerate. Consider, for example, the subcircuit for both D1 and D2 ON, as in Figure 16.24d. Clearly no current can flow in RL . Also, current can’t flow down through D3 , or up through D4 , so all diode currents must be zero in this state. A similar argument holds for all adjacent diode pairs, whether ON or OFF. Hence the two states depicted in Figures 16.24b and 16.24c are the only ones we need to consider. Note that the current always flows in the same direction through RL , regardless of the polarity of vi . For sinusoidal input the waveforms appear as in Figure 16.24e. The circuit is called a full-wave rectifier because current flows through RL on both halves of the input wave. Neglecting diode voltage drops, the average value of the output voltage, that is the DC voltage, is 0.637 times the peak of the input sinusoid. Further, by symmetry there is no frequency component in the output waveform at the input frequency, 60 Hertz in our example, or odd multiples thereof. Hence the circuit has a much higher percentage of DC relative to harmonics compared to the half-wave rectifier discussed in Section 4.3. 918k R i + i F I G U R E 16.25 Zener-diode regulator. + - v v + - 50 mV AC vo 20 V DC (a) (b) 16.5.5 I N C R E M E N T A L E X A M P L E : Z E N E R - D I O D E REGULATOR All semiconductor diodes will break down and conduct appreciable current under reverse bias conditions if the reverse voltage across the diode is large enough. This breakdown is non-destructive if the current is not excessive; the diode returns to normal reverse-bias behavior if the voltage is reduced. A Zener diode is a semiconductor diode in which this breakdown under reverse bias is carefully controlled by the manufacturing process so that the breakdown occurs at a specified voltage, the so-called Zener voltage of the diode. A typical v i curve is shown in Figure 16.25a. Because the breakdown voltage of a Zener diode can be carefully controlled by the manufacturing process, and the incremental resistance in the breakdown region is quite small (around 10 to 50 ), Zener diodes are quite useful as voltage regulators. A simple example is shown in Figure 16.25b. Equation 4.74 is clearly inappropriate for finding the incremental resistance in breakdown, because this part of the characteristic is not an exponential. Hence the value must be obtained from the data sheet for the Zener diode in question. Integrated-circuit regulators, with transistors, Zener diodes, and resistors all on a single chip, will certainly outperform either of the crude regulator circuits discussed here. 16.5.6 I N C R E M E N T A L E X A M P L E : DIODE ATTENUATOR It should be clear from Section 4.5, and particularly from Equations 4.63 and 4.74, that for small increments of voltage or current, the semiconductor diode looks like a linear resistor whose value depends on the DC current flowing through it. Thus it should be fairly easy to build an attenuator with an attenuation constant that can be changed by means of an external voltage or current. Figure 16.26 shows a simple example. Here a diode is used in the shunt branch of a voltage divider on a small-signal source vi . The DC current through the diode is controlled by the DC voltage VC through the large 918l RC Rt = R1||RC R1 + VC - R1 - + VOC = VC ------------------R1 + RC - + vi - (a) (c) F I G U R E 16.26 Diode attenuator. RC RC + VC - + - 0.6 V Rd R1 + R1 0 ID0 (b) + vi - (d) vo rd - resistor RC . If we assume that vi produces less than a 5 mV change in the diode voltage, then the incremental analysis approach discussed in Section 4.5 can be applied. First, draw the circuit for the calculation of the DC current ID0 is to form the Thévenin equivalent of the linear part of the circuit, as shown in Figure 16.26b. An easy way to solve for ID0 is to form the Thévenin equivalent of the linear part of the circuit, as shown in Figure 16.26c. At the same time we replace the diode by its piecewise linear model. Then ID0 = (VOC − 0.6) Rt + R d . (16.45) The incremental resistance rd of the diode will thus be a function of VC : rd = kT qID0 kT (R1 RC ) + Rd . = q VC R1 − 0.6 (16.46) (16.47) R1 +RC Now draw the subcircuit that relates the incremental variables. Replace the diode in Figure 16.26a by the incremental resistance rd , and set all DC sources, in this case VC , to zero, as indicated in Figure 16.26d. By inspection, vo = vi RC rd R1 + (RC rd ) . (16.48) The attenuation is clearly dependent on the DC voltage VC , as desired. 918m