APPLIED PHYSICS LETTERS 92, 163508 共2008兲
On the dc and noise properties of the gate current in epitaxial
Ge p-channel metal oxide semiconductor field effect transistors
with TiN / TaN / HfO2 / SiO2 gate stack
Debabrata Maji,1,a兲 Felice Crupi,2 Gino Giusi,2 Calogero Pace,2 Eddy Simoen,3
Cor Claeys,3 and V. Ramgopal Rao1
1
Indian Institute of Technology, Bombay 400076, India
DEIS, University of Calabria, Arcavacata di Rende, Cosenza 87036, Italy
3
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
2
共Received 27 February 2008; accepted 7 April 2008; published online 24 April 2008兲
In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel
metal oxide field effect transistors 共pMOSFETs兲 with a Si passivated surface. The gate stack
consists of HfO2 / SiO2 dielectric with TiN / TaN metal gate. The observed temperature dependence
of the gate current indicates that the dominant charge transport mechanism through the gate
dielectric consists of Poole–Frenkel conduction. Gate current 1 / f noise is more than two orders
higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion
into the gate oxide is the suspected cause for the enhanced Poole–Frenkel conduction and the high
gate current 1 / f noise in Ge pMOSFETs. © 2008 American Institute of Physics.
关DOI: 10.1063/1.2916821兴
In the nano scale metal oxide field effect transistors
共MOSFETs兲 regime, requirements of high mobility channel
materials are being researched. In recent days, Ge is gaining
lots of interest in the semiconductor industry as an alternative to Si due to its bulk electron and hole mobilities that are
two and four times higher, respectively.1 However, Ge itself
has a much lower melting temperature, and more importantly, GeO2 has a poor electrical quality and is water
soluble.2–4 With the advancement in the high-k deposition, it
is possible to continue the research with Ge as a channel
material. As the research is progressing, it is understood that
Ge surface passivation is essential to control the interface
structure and interface state density between the high-k and
the Ge substrate. In particular, Si passivation exhibits relatively lower interface state densities and improved leakage
current.5 On the other hand, HfO2 is the most researched
high-k material due to its wide band gap and large band
offsets. Recently, high performance metal gate/ HfO2 / Ge
MOSFETs on unstrained and strained Ge on Si substrates
have been reported in literature.6,7 In spite of this progress,
questions remain about the quality of the high-k metal gate
stack on Ge due to the large amount of Ge that can be found
inside the HfO2 when HfO2 is deposited on Ge.3,8,9 Hf based
as well as diffused Ge related defects can cause serious reliability issues such as threshold voltage instability, bias temperature instability, and trap assisted tunneling.10 In this letter, we investigate the quality of a TiN / TaN / HfO2 / SiO2
gate stack on epi-Ge pMOSFETs through measurements of
the dc and the noise characteristics of the gate current.
Ge pMOSFETs are fabricated by using a standard Si
compatible process flow, as outlined in Ref. 6, starting from
epitaxial Ge on 200 mm diameter Si wafers. The 1.6 ␮m Ge
top layer is directly grown by chemical vapor deposition on
Si and has a threading dislocation density of ⬃107 cm−2 after
postgrowth annealing. The wafers first received a deep phosphorous implant for the n well. The Ge surface is passivated
a兲
Electronic mail: dmaji14@ee.iitb.ac.in.
by a 0.8 nm epitaxial Si layer. This ultrathin Si layer is partially oxidized to form a thin SiO2 interfacial layer. Immediately after, HfO2 is deposited by atomic layer deposition.
Finally, after deposition of 10 nm TaN, capped with 100 nm
TiN for the metal gate, the wafers undergo a 350 ° C for
20 min, forming gas anneal for interface state passivation.
The equivalent oxide thickness 共EOT兲 of the gate stack is
1.3 nm. A schematic of the Ge pMOSFETs is shown in Fig.
1共b兲 as an inset. For comparison purposes, we characterized
a second set of devices on a Si substrate and with a similar
gate stack consisting of TiN / HfO2 / SiO2 with 1.2 nm EOT.
Figure 1共a兲 shows good area scaling and low dispersion
in the gate current of Ge pMOSFETs, thus, indicating that
the gate stack under investigation is quite uniform. In order
to study the charge conduction mechanism through the gate
stack, we evaluated the temperature dependence of the gate
current. As shown in Fig. 2, a stronger temperature dependence is observed for Ge pMOSFETs compared to the Si
FIG. 1. 共a兲 Gate current density at VG = −1.5 V in Ge pMOSFETs with
channel width W = 10 ␮m and channel lengths L = 1, 5, and 10 ␮m. Five
different samples have been measured for each channel length. Gate current
exhbits good area scaling and low dispersion. Inset 共b兲 Cross-sectional diagram of Ge pMOSFETs.
0003-6951/2008/92共16兲/163508/3/$23.00
92, 163508-1
© 2008 American Institute of Physics
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163508-2
Appl. Phys. Lett. 92, 163508 共2008兲
Maji et al.
FIG. 2. Gate current density at a gate voltage VG = −1.5 V at different temperatures normalized with respect to gate current density at T = 300 K for Ge
pMOSFETs and reference Si pMOSFETs. A stronger temperature dependence is observed in Ge pMOSFETs.
FIG. 4. GNP vs gate current density for Ge pMOSFETs and reference
Si pMOSFETs. GNP in Ge pMOSFETs is remarkably higher and more
scattered.
reference device. In Fig. 3, the logarithm of JG / E is plotted
as a function of the square root of the electric field for different temperatures in the case of Ge pMOSFETs and
straight lines are observed for moderate electric fields, which
suggest that the charge transport is dominated by Poole–
Frenkel 共PF兲 conduction.11 Also, we found that the slope
parameter ␰ of the PF plot is 1 with an extracted activation
energy of the traps, 0.3 eV, which is in good agreement with
the reported data in the literature.12 A possible explanation is
that the traps responsible for enhanced PF conduction in the
device operative regimes are due to Ge out diffusion into the
gate oxide.3,7,8,13
On wafer gate current, low frequency noise measurements have been done by using a dedicated noise measurement system.9 The gate current power spectral density 共PSD兲
for both Ge pMOSFETs and reference Si pMOSFETs show
a 1 / f ␥ behavior with ␥ nearly equal to 1. We evaluated the
gate noise parameter 共GNP兲 defined as14
than two orders of magnitude higher when compared to the
Si based pMOSFETs. One can also notice in Fig. 4 that the
GNP values for Ge pMOSFETs are more scattered than for
Si. This kind of tendency was also observed by Guo et al.,15
in the case of drain current low frequency noise measurements on similar Ge devices. Hence, the results of Fig. 4
clearly indicate that the quality of the gate stack on the
epi-Ge is inferior with respect to the Si substrate counterpart.
Ge out diffusion can be attributed as one of the causes for the
lower quality of the gate oxide when deposited on Ge. In
fact, the outdiffused Ge acts as a trap center near the interface inside the gate oxide. The traps enhance the trapping
and detrapping processes of charging.16,17 Hence, the higher
gate current noise is observed in Ge pMOSFETs.
In summary, we have experimentally characterized
the dc and noise properties of the gate current in
TaN / TiN / HfO2 / SiO2 / epi-Ge/ Si pMOSFETs and the results are compared with Si samples with a similar gate stack.
The gate current in Ge pMOSFETs exhibits a stronger temperature dependence and higher 1 / f noise when compared to
Si pMOSFETs. Both effects are ascribed to the same cause,
which consists of additional traps due to Ge out diffusion
into the gate oxide. This suggests that Ge out diffusion is a
serious reliability issue when using Ge MOSFETs in future
technologies. However, to support the proposed hypothesis
in more detail, it is felt that one should investigate unexplored issues such as the impact of the interfacial SiO2 thickness on the Ge out diffusion in terms of drain current and
gate current noise performances. Additionally, the evaluation
of interface and slow traps deserved some further investigations which are currently on going. Finally, the possible use
of characterization tools to determine the Ge content in the
gate dielectric should also be explored.
GNP ⬅
Sig fA
2 ,
IG
共1兲
where f is the frequency, Sig is the gate current noise PSD 共in
the 1 / f regime兲, A is the area of the device channel, and IG is
the dc gate current. According to the analytical model of the
gate current 1 / f noise proposed in Ref. 14, the GNP is proportional to the effective trap density in the dielectric. As
shown in Fig. 4, the GNP for the Ge pMOSFETs is more
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