Configurable System-on-Chip:
Xilinx EDK
Heiner Giefers
Computer Engineering Group
University of Paderborn
hgiefers@upb.de
1
Outline

FPGAs

FPGA Tool Flow

System on Chip (SoC)

SoC Tool Flow

Demonstration
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
2
Field-Programmable Gate Arrays (FPGAs)


Flash PROM

Fine-grained reconfigurable hardware
Gate-Array: regular structure of “logic cells”, connected
through an interconnection network
Configuration stored in SRAM, must be loaded on startup
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
3
FPGA toolflow
HDL

(VHDL /
Verilog)

Synthesize
Hardware design is traditionally done by
modeling the system in a hardware
description language
An FPGA “compiler” (synthesis tool)
generates a netlist,
Netlist
Map

Place

Route

Bitstream
which is then mapped to the FPGA
technology,
the inferred components are placed on the
chip,
and the connecting signals are routed
through the interconnection network.
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
4
HDL Synthesis
process(clk, reset)
HDL
begin
(VHDL /
Verilog)
if reset = ‘1‘ then
output <= ‘0‘;
elsif clk‘event AND clk = ‘1‘ then
output <= a XOR b;
end if;
Synthesize
end process;
Netlist
Map
Register
Place
Route
a
b
D
⊕
clk
Bitstream
Q
output
clear
reset
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Technology Mapping
Register
HDL
a
b
(VHDL /
Verilog)
D
⊕
clk
Synthesize
Q
output
clear
reset
Netlist
Map
Place
Route
a
b
output
FF
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Place & Route
HDL
(VHDL /
Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Xilinx ISE
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Evolution of FPGA
Virtex-6 ’09
Virtex-5 ’06

Glue logic

Prototyping

Reconfigurable
System-on-Chip
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Traditional Embedded System
Ethernet
MAC
Audio
Codec
Power Supply
CLK
CLK
Interrupt
Controller
GP I/O
Address
Decode
Unit
CLK
SRAM
Memory
Controller
SRAM
SRAM
CPU
UART
(uP / DSP)
SDRAM
Timer
CoProc.
SDRAM
L
C
custom
IF-logic
Display
Controller
Images by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Traditional Embedded System
Ethernet
MAC
Audio
FPGA Codec
Power Supply
CLK
CLK
Interrupt
Controller
GP I/O
Address
Decode
Unit
CLK
SRAM
Memory
Controller
SRAM
SRAM
CPU
UART
(uP / DSP)
SDRAM
Timer
CoProc.
SDRAM
L
C
custom
IF-logic
Display
Controller
Images by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
11
Configurable System on Chip (CSoC)
Audio
Codec
Flash PROM
Power Supply
L
C
SRAM
SRAM
SRAM
SDRAM
SDRAM
Images by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
12
Advantages

Fewer physical components

Shorter development cycles

Field-programmable (updates, new features...)
  Custom

co-processors / accelerators
Possibly higher performance through on-chip integration
  Signals
on a chip can typically be clocked higher than signals across
board traces
  Optimization between modules possible

Partial reconfigurability
  Exchange
peripherals while the rest of the system keeps running
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
13
Building a SoC

HW-Blocks are called IP “cores”
  Buy
them like Software
  Implement own cores
  Usually highly parametrizable

Interconnect infrastructure
  Bus
Architectures
  P2P Links

Cores implement (standardized)
interfaces

Modelling kit determines parameters for
cores and “generates” the system
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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CoreConnect Bus Architecture

Flexible bus architecture for embedded Systems and SoCs
  Developed
by IBM
  Used by Xilinx EDK



Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register Bus
(DCR)

Alternatives:
  AMBA
(Altera)
  Wishbone (OpenCores)
  Proprietary bus architectures
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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Embedded CPUs

PowerPC 440 (hard core)
  32
bit embedded PowerPC RISC
  Up to 550 MHz
  2x 32 kB instruction and data caches
  Memory management unit (MMU)
  Hardware multiply and divide
  Coprocessor interface (APU)
  PLB and DCR bus interfaces

Images by Xilinx
MicroBlaze (soft core)
  32

bit RISC architecture, up to 235 MHz
  Min. configuration: 1,010 LUTs
[XC5VLX330 FPGA: 207,360 LUTs  .5%]
  Highly configurable
Others
  NIOS
(Altera)
  ARM
  PicoBlaze
(Xilinx), ...
Barrel Shifter
  MMU, 2-64 kB instruction and data caches
  HW Multiplier/Divider, FPU, Debug

  PLB,
LMB, FSL bus interfaces
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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IXCL_S
Memory Management Unit (MMU)
DXCL_M
ALU
Program
Counter
Shift
Special
Purpose
Registers
IPLB
Barrel Shift
Data-Cache
IXCL_M
Instruction-Cache
Microblaze Configuration
DXCL_S
DPLB
Multiplier
Divider
Bus
IF
ILMB
FPU
Instruction
Buffer
Instruction
Decode
Bus
IF
Register File
32 x 32b
  High
bandwith  Processor Local Bus (PLB)
  Configurable caches  Xilinx Cache Link (XCL)
  Local (BRAM) memory  Local Memory Bus (LMB)
  Co-processor port  Fast Simplex Link (FSL)
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
DLMB
MFS1..16
SFSL1..16
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CSoC Design Flow (Hardware)
HDL
Platform
(VHDL /
Description
Verilog)


Higher level of abstraction
Transform platform description into netlist
  Map,
place & route to FPGA, or
  Import in ISE and used in a larger FPGA design
Synthesize
Netlist
Generation
Netlist
Netlist
VHDL
Map
Place
XST
(Map, Place & Route)
Xilinx ISE
(VHDL Edit, Map,
Place & Route)
Route
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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CSoC Design Flow (Hardware)
Platform
Description
Netlist
Generation
VHDL
Netlist
XST
(Map, Place & Route)
Xilinx ISE
(VHDL Edit, Map,
Place & Route)
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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CSoC Design Flow (Software)
Platform
Description
Library
Generation
Netlist
Generation
*.a
User sources
*.h
*.h
*.c
Compile &
Link
Netlist
Update
Bitstream
*.elf
XST or ISE
(Map, Place & Route)
Bitstream
Bitstream
with
executable
Code
Program
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
20
CSoC Design Flow (Software)
Platform
Description
Library
Generation
Netlist
Generation
*.a
User sources
*.h
*.h
*.c
Compile &
Link
Netlist
Update
Bitstream
*.elf
XST or ISE
(Map, Place & Route)
Bitstream
Bitstream
with
executable
Code
Program
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
21
Demonstration
Spartan III FPGA
50 MHz clock
(back side)
7-segment display
Reset button
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
22
void
void main(){
main(){
c_count
while(1)= 0;
while(c_count<10000)
{
{ while(c<10000)
seven_seg_ctrl(0,
c_count);
GPIO_Write(c,CHANNEL,POS);
wait(1000000);
c++;
}c_count++;
}
Microblaze
CPU
FSL
LED0
LED5
7-seg
ctrl
LED6
LED1
LED2
LED4
LED3
PLB
7
GPIO
LED0
LED1
LED2
LED3
LED4
LED5
LED6
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
23
Questions?
More information on Xilinx FPGAs and design tools
  http://www.xilinx.com
  http://www.xilinx.com/edk

Student projects / Theses (BA/MA)

Heiner Giefers
P1.7.08.3
hgiefers@upb.de

Enno Lübbers
P1.7.08.4
enno.luebbers@upb.de
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
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