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DOE Seminar Series (in collaboration with IEEE Ottawa SSC/CASS/EDS,
AP/MTT & CPMT chapters)
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Title: System on Package (SoP) Integration Technologies and CAD methods for Micro, Nano and Bio Convergence
Speaker: Professor Madhavan Swaminathan, Fellow IEEE, Deputy
Director,
Packaging Research Center, Georgia Institute of Technology,
Atlanta, USA
Time: 5:00pm-6:15pm, Nov. 10 (Monday), 2008
Location: 5050MC (Minto Center) Carleton University
Refreshments Pizza/Donuts/Soft Drinks/Coffee Will be Served
Abstract:
As the semiconductor industry moves beyond the 45nm node and as systems become more heterogeneous, System on Chip (SoC) solutions are facing major barriers due to technical and business related reasons.
This is leading to the development of new technological solutions such as System on Package (SoP). SoP, a technology being pioneered by
Georgia Tech, allows for integration of functions in the package.
Higher levels of integration are possible by embedding functions in the substrate and merging the package and board level technologies into one. SoP enables the integration of digital, RF, opto-electronic and sensor electronics in the package leading to system miniaturization with micro, nano and bio convergence. This talk will focus on some of the technologies and CAD methods for SoP being developed at Georgia Tech.
Bio:
Madhavan Swaminathan is the Joseph M. Pettit Professor in Electronics in the School of Electrical and Computer Engineering. He was the
Deputy Director of the Microsystems Packaging Research Center, Georgia
Tech from 2004 - 2008. He is the co-founder of Jacket Micro Devices, a

leader in integrated RF modules and substrates for wireless applications. Prior to joining Georgia Tech, he was with IBM working on the packaging for supercomputers. He is the author of more than 300 journal and conference publications, holds 15 patents, and is the author of two books entitled “Power Integrity Modeling and Design for
Semiconductors and Systems”, ISBN 0_13_615206_6. Prentice Hall, Nov
2007 and “Introduction to System on Package”, MCGraw Hill, Mar. 2008.
He is an IEEE Fellow and has been recognized for his research through several awards including the 2007 Technical Excellence Award from the
Semi-conductor and Global Research Corporation (SRC/GRC). He received
his M.S and PhD degrees in Electrical Engineering from Syracuse
University in 1989 and 1991, respectively.
RSVP by Nov. 9th.
Ram
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Ram Achar, Ph. D., P. Eng.
Associate Professor
Chair, Ottawa IEEE SSC/EDS/CAS joint chapter
Department of Electronics, Carleton University
Ottawa, Ontario, Canada - K1S 5B6
Ph: 613-520-5651; Fax: 613-520-5708
Email: achar@doe.carleton.ca
URL: http://www.doe.carleton.ca/~achar
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