Appendix A
TUTORIAL
Verilog Design with Altera Quartus II
Hardware & Software Requirements of this tutorial
 A PC running the Windows 7.
 Quartus II, version 13.0 (Quartus II is a registered trademark of Altera Corporation)
Contents:
1.
Introduction.
2.
Getting Started. Start the Quartus II software and set some extra setting. For
example, create a new Quartus Project, targeted FPGA device, etc.
3.
Design Entry.Illustrates the process of using the Verilog design entry tools provided in
Quartus II, which is called the Text Editor.
4.
Compilation. Use the Quartus II synthesis tool to translate the Verilog language into
logic expressions, determines how each logic expression should be implemented in
the logic elements available in the target chip.
Simulation. Use Quartus II waveform editor to create the desired waveform, called
full_adder.vwf, to represent input signals, and use Quartus II simulation tool to
simulate the behaviour of the circuit.
5.
6.
Example Design. Complete the design of 4-bit ripple carry adder using structural
modelling approach. Compile and simulate.
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APPENDIX A
1. Introduction
This tutorial presents the step-by-step instructions on how to use the Altera Quartus II CAD
software in the Verilog design of a full adder (named FA). The FA is then instantiated as a
lower-level module, and applied in the modular design of a 4-bit Ripple-Carry Adder (named
adder4), which is shown in Fig. 1.
Fig. 1: 4-bit Ripple Carry Adder (adder4)
2.
Getting Started
2.1
Open Quartus II Software
1.
On opening the CAD tool, the first screen display of Quartus II 64-bit version 13.0 is as
shown in Fig. 2.
Fig. 2: The Quartus II main display
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2.2
211
Quartus II Settings
1.
Go to menu bar, select Tools >> Customize.
2.
Under the Toolbars, check the boxes: File, Standard, Utility Windows and Applications
(see Fig. 3). Click OK.
Fig. 3: Tools >> Customize Toolbars Display Window
2.3
Start a New Quartus II Project
1.
From the menu bar, choose File >> New Project Wizard to start a wizard to create a new
project. Click Next to skip the Introduction page and to get the window shown in Fig. 4.
2.
In the first text box, set the working directory to: c:/...... /Altera_tutorial_1
3.
In the second textbox, set the project name to adder4. Observe that Quartus II
automatically suggests that the name adder4 be also the name of the top-level design
entity in the project.
Fig. 4: Specifying the project directory and name
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APPENDIX A
4.
Click Next.
5.
Since the directory c:/.....Altera_tutorial is not yet created, Quartus II displays the pop-up
box, asking if it should create the desired directory. Click Yes to enter the window, New
Project Wizard: Add Files.
6.
Since we don’t have any existing files to include in the new project, click Next to enter
New Project Wizard: Family & Device Settings.
7.
Specify the following options: (see Fig. 5)
Family
: Cyclone II
Package
: Any
Pin count
: Any
Speed grade: Any
Select Auto device selected by the Fitter under Target device.
Fig. 5: Select targeted FPGA device
8.
Click Next to enter New Project Wizard: EDA Tool Settings. See Fig. 6.
9.
Since Quartus II is the only CAD tool we are using here, click Next to enter New Project
Wizard: Summary, as shown in Fig. 7. Click Finish.
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Fig. 6: EDA Tool Settings window
Fig. 7: New Project Summary
3.
Design Entry
3.1
Open the Text Editor
1.
In the menu bar, select File >> New. Click Device Design Files tab, and then select Verilog
HDL File, as shown in Fig. 8.
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APPENDIX A
Fig. 8: Choosing the type of design file
2.
Click OK.
This selection opens the Text Editor Window shown on the right side of Fig. 9.
Fig. 9: Text Editor Window
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3.2 Create FA.v Verilog Code
1.
Type the Verilog code of the full adder FA in the editor window as shown in Fig. 10.
Fig. 10: The Verilog code entered in the Text Editor
2.
Click
to save the file. Change the file name to FA and click Save. Make sure the Add
file to current project is checked.
3.
Instead of typing the Verilog program from scratch, user can also use the built-in
templates. To familiarize with this resource, browse through the template by doing the
following steps:
i. From the menu bar, select Edit >> Insert Template, the Insert Template window
appears.
ii. Under Language templates, select Verilog HDL.
iii. Select the template that you need.
4. Compilation
In a full compilation, the Compiler’s Analysis & Synthesis module first extracts information that
defines the hierarchical connections between a project’s design files and checks the designs for
basic design entry errors. This is syntax error checking and language compiling stage.
Then, it creates an organizational map of the design and combines all design files in a flattened
database that can be processes efficiently. Logic synthesis is then performed.
Next, the Fitter selects the optimum interconnection paths, pin assignments, and logic cell
assignments needed to fit the design into the selected device. The Assembler then completes
project processing by converting the Fitter’s assignments into a programming image for the
device. Technology mapping to the device (or physical design) is now completed.
Finally, the Timing Analyzer runs automatically to report timing information for all logic in the
design.
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APPENDIX A
4.1 Compilation of a lower-level entity
We have earlier set the top-level entity of this Quartus project to adder4, but the current entity
that we are processing is FA, which is a sub-module of adder4, therefore a lower-level entity.
To compile this current low-level component, we need to modify the top-level entity in the
General Setting. Hence, compile the FA.v file with the following procedure:
1.
In the menu bar, select Assignments >> Settings (or Click
on the tool bar) to open up
the Settings – adder4 window. In the list of Category, select General.
2.
In the text box of Top-Level Entity, change adder4 to FA. See Fig. 11. Click OK to close the
setting window.
Fig. 11: Select Entity
4.2 Compiling (Synthesizing)
1.
From the menu bar, select Processing >> Start Compilation (or Click
from the toolbar;
or Press Ctrl + L shortcut key) to start the full compilation process. As the compilation
proceeds, its progress is reported in the Tasks window on the left side of Quartus II display.
2.
If the compilation process generates any errors, correct the error based on the error
message shown in Message Editor. See Fig. 12. When double click the error statement, it
will highlight and locate the error source in text editor window.
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3.
217
After the compilation process is finish, a Compilation Report – Flow Summary is
automatically generated. See Fig. 12. If the window is accidentally closed, it can be view
by doing this: Select Processing >> Compilation Report from menu bar (or Press Ctrl + R
shortcut key; or Click
from the toolbar).
Fig. 12: Compilation Process
4.
Expand the compilation report to observe details. For example, selecting in Table of
Contents >> Analysis & Synthesis >> the Resource Usage Summary, we obtain the
resource usage summary as shown in Fig. 13.
Fig. 13: Sample of Compilation Report
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APPENDIX A
5. Simulation
Simulation allows you to test a design thoroughly to ensure that it responds correctly in all
possible situations before you “program” (or configure) a device. Depending on the type of
information you need, you can perform functional or timing simulation with the Simulator.
Functional simulation tests only the logical operation of a design by simulating the behaviors of
flattened netlists extracted from the design files. Timing simulation, on the other hand, uses a
netlist that is synthesized and technology mapped, which contains timing information to test
the functionality of the design taking into account the worst-case timing in target device.
5.1 Creating Test Waveforms for Simulation
1.
To create the waveform file:
Select File >> New from menu bar, the New dialog box appears. Select the
Verification/Debugging Files >> University Program VWF, then click OK.
2.
The Waveform Editor opens, displaying an empty waveform file. See Fig. 14.
3.
To change the end time for the file, choose Edit >> End Time from menu bar. In the Time
box, type 500 and select ns in the list. Click OK.
4.
To save the vector waveform file, select File >> Save As from menu bar or click
toolbar. The Save As dialog box appears.
5.
In the Save As dialog box, browse to the ../Altera_tutorial1 working directory.
6.
In the File name box, type FA. Click Save.
Fig. 14: Simulation Waveform Editor Window
from
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219
5.2 Add Input & Output Nodes to the File
1.
In the Waveform Editor window, select Edit >> Insert >> Insert Node or Bus. In the pop-up
window that appears, which is shown in Figure 15, click on Node Finder.
Fig. 15: Node Finder
Fig. 16: The Node Finder dialog
2.
To find the nodes you want to add to the .vwf file, in the Node Finder, set the filter
setting to Pins: all, and then click on List. See Fig. 16
3.
In the Nodes Found list, select the Cin, Cout, Sum, x and y pins and by highlighting the
desired nodes and clicking on the > button. Click OK in this window. This returns to the
Waveform Editor window, with the selected signals included as presented in Figure 17.
Fig. 17: The selected signals
4.
Arrange the input/output sequence according to the sequence: Cin, x, y, Sum, Cout. You
can do this by moving a waveform up or down in the Waveform Editor window, click on
the node name in the Name Column and release the mouse button.
5.
See Fig. 19. Observe that all input signals are at logic level 0. The outputs are shown as
undefined. Next, we have to draw the input waveforms. Then, we can simulate the circuit,
which will produce the output waveform.
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APPENDIX A
Fig. 19: Signals in Waveform Editor
5.3 Edit the Input Waveforms
To make it easier to draw the input waveforms, the Waveform Editor displays dashed grid lines.
The spacing of the grid lines can be adjusted by selecting Edit >> Grid Size, and in the pop-up
box specifying the desired size. The default spacing of grid lines is 10 ns. Another convenience
in drawing is to have transitions of a waveform snap on grid lines. This feature is activated by
clicking on the Snap to Grid icon. Change the grid size to 20 ns.
Edit the Cin Input Node Waveform
1.
If necessary, click the Selection Tool
button.
2.
Use the Selection Tool to click and hold at time 160 ns on the Cin input waveform and drag
the pointer to the time until 320 ns. The selected waveform will be highlighted.
3.
Click the
on the Waveform Editor Toolbar to force the selected waveform to high.
Edit the x Input Node Waveform
1. Click the Selection Tool at time 80 ns on the x input waveform and drag the pointer to the
time until 160 ns. The selected waveform will be highlighted.
2. Click the
on the Waveform Editor Toolbar to force the selected waveform to high.
3. Repeat step (1) & (2) to the x input waveform from time at 240 ns until 320 ns.
4. Repeat step (1) & (2) to the x input waveform from time at 400 ns until 480 ns.
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221
Edit the y Input Node Waveform
5.
To select the entire y input node waveform, click the Selection Tool on the “handle”
of the y node. The entire node, including the waveform, is
highlighted.
6.
Click the
on the Waveform Editor Toolbar, the Count Value window displays.
7.
Click on the Timing tab. In the Count every box under At Absolute Time, type 40 and
select ns in the list. Click OK to close the Count Value window.
8.
To see the entire waveform, select View >> Fit in Window . You can also click
zoom in (left click) or zoom out (right click). See Fig. 20.
to
Fig. 20: Complete Simulation Input
9.
Click File>> Save to save the waveform file. It is saved to FA.wvf file. (vwf stands for vector
waveform file.)
5.4 Simulate the Design
Functional Simulation
Now that we have created the input vector waveform, we can simulate the circuit. Select
Simulation >> Run Functional Simulation. A second Simulation Waveform Editor window then
opens the output waveform, as depicted in Fig. 20.
The output waveform is read-only, so any changes in simulation have to be done by modifying
the FA.vwf file, and re-simulating the circuit. Observe that the outputs are as expected (Sum
and Cout obeys the truth table of FA), which verifies the correctness of our design.
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APPENDIX A
Fig. 21: Result of the Functional Simulation
Timing Simulation
To observe the actual propogation delays in our circuit, we have to perform a timing
simulation. Select Simulation>> Run Timing Simulation. Fig. 22 gives the result of the timing
simulation.
Compare the Timing Simulation Output with Functional Simulation in Fig. 21.
Fig. 22. Result of the Timing Simulation
The timing simulation shows that there are delays when signals change from one value to
another. Fig. 23 gives the waveform zoomed in, showing the propogation delay between the
outputs and inputs. The waveform indicates that the maximum delay is approximately 10 ns.
There are also glitches due to static hazards.
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223
Fig. 23. Result of the timing simulation, waveform is zoomed in.
NOTE:
Changes in the input waveforms can be made using the approaches given above. The circuit
can be resimulated using the modified waveforms. If errors in the circuit are discovered, then
these errors can be fixed by changing the Verilog code and recompiling and resimulating. If you
want to use a different simulation file (i.e. simulate with a different waveform file), select
File >> Open from menu bar. Double-click the file you want, which will open the waveform
editor with the new waveform. Then you can simulate with this test file.
6. Example Design: Modular Design of a 4-bit Ripple Carry Adder
6.1 Complete the adder4 top-level design
1.
Using the same approach in “Design entry” presented in Section 3.2, create a new file
named adder4.v. Type the following Verilog code in the adder4.v as provided in Fig. 24.
Fig. 24:(Cin,
Top-level
Verilog
code
module adder4
x, y, Cout,
Sum)
; of adder4.v
input Cin;
input [3:0] x, y ;
output [3:0] Sum ;
output Cout;
wire c1, c2, c3 ;
FA fa0 (.Cin(Cin), .x(x[0]), .y(y[0]), .Sum(Sum[0]), .Cout(c1) );
FA fa1 ( .Cin(c1), .x(x[1]), .y(y[1]), .Sum(Sum[1]), .Cout(c2) ) ;
FA fa2 ( .Cin(c2), .x(x[2]), .y(y[2]), .Sum(Sum[2]), .Cout(c3) ) ;
FA fa3 ( .Cin(c3), .x(x[3]), .y(y[3]), .Sum(Sum[3]), .Cout(Cout) ) ;
endmodule
Fig. 24: Verilog code of adder4
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6.2
APPENDIX A
Compilation
Change the Compiler Setting of Top-Level Entity
1.
On the tool bar, select Assignment >> Settings (or Click
) to open up the Settings –
adder4_Verilog window. In the list of Category, select General. The general window
shows.
2.
In the text box of Top-Level Entity, change the top-level entity from FA to adder4.
3.
Click OK to close the setting window.
Compile the Top-Level Design
1.
Using the procedure as discussed in Section 4.2, compile the adder4 design.
2.
If there are any errors occur, please correct the errors before proceeding to the next
section.
6.3
Simulation
1.
You can create a new vector waveform file, named adder4.vwf and randomly choose
several variations to simulate the 4-bit carry adder design using the same approach as in
Section 5. Remember to change the Simulation input from FA.vwf to adder4.vwf.
2.
Perform the Functional Simulation or Timing Simulation, and verify correctness of design.
Congratulations!
You have completed the modular design of a 4-bit Ripple Carry Adder using Altera
Quartus II!