I/O Organization
 1997 John D. Carpinelli, All Rights Reserved
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Outline
I/O interfacing
u Asynchronous data transfer
u Interrupt driven I/O
u DMA transfers
u I/O processors
u Serial communications
u
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A CPU that cannot interact with the outside world is basically useless. This
module examines input/output organization of computer systems. We begin
by examining I/O interfacing, or the connection between I/O devices and the
CPU. We then study asynchronous data transfers. This concept is used to
transfer data between devices. For example, transferring data via modem is an
asynchronous data transfer. Next we describe the types of input/output and
how they are prioritized.
Sometimes it is preferable to bypass the CPU when performing I/O transfers.
Direct Memory Access, or DMA, and I/O processors are two devices used to
accomplish this. We also examine serial communications. Finally, concluding
remarks are presented.
I/O interfacing
See figure 11.1, p. 386 of the textbook.
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This figure shows how generic I/O devices are interfaced to a CPU. An
interface block sits between the CPU and an individual I/O port. This interface
consists of combinatorial logic which recognizes when the correct address and
control signals are present. It may also contain latches and/or tri-state buffers
to receive data and to isolate the I/O device from the bus. For example,
consider an I/O device not shown in this figure, a mouse. If the mouse is
connected as an input-only device at port address 3F8H (a commonly-used
address for serial ports on the PC), the interface might enable a buffer which
allows data to pass from the mouse to the CPU when the address lines are set
to 11 1111 1000 and the CPU is performing an I/O read operation.
I/O commands
Control commands
u Status commands
u Data output command
u Data input command
u
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When dealing with I/O devices, it is useful to consider all interaction as taking
place via I/O commands. In fact, there are I/O interface chips, or I/O
controllers, designed to coordinate transfers via I/O commands. These
commands fall into four distinct categories. Control commands cause the I/O
device to do something other than transfer data. A typical control command
might cause a disk drive to position its head over a specific track or to move its
head one step in a given direction. The status commands request non-data
information from the I/O device, such as whether the device is ready to
transfer data or the setting of some hardware parameters.
The remaining commands transfer data. Data output commands transfer data
from the bus to the I/O interface, which in turn transfers it to the I/O device.
Data input commands do just the opposite, moving data from the I/O device to
the bus via the I/O interface. Writing data to and reading data from a disk is a
common example of when these commands would be used.
Types of I/O
u
Isolated I/O
– Separate address space
– Separate control lines and instructions
u
Memory-mapped I/O
– I/O ports treated as memory locations
– Same address space, control lines and
instructions as used for memory access
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CPUs implement I/O in one of two ways. In isolated I/O, each I/O device has
a unique address that is separate from the memory addresses used by the
system. There are separate control lines to distinguish between I/O transfers
and memory transfers, as well as separate instructions to access I/O ports.
Memory-mapped I/O treats each I/O port as a memory location. As such, the
same address space and control lines are used to access an I/O port as are used
to access a memory location. The same instructions are used to access both.
Asynchronous data transfer
Strobe: a pulse supplied to indicate the
time at which data is being transmitted
Handshaking: a control signal is
transmitted along with the data; another
signal is sent by the receiver
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Asynchronous data communication is used when transmitting data between
two devices which cannot share a common clock. For example, data
transmitted via modem would be sent asynchronously, whereas data
transmitted within a single computer would be transmitted synchronously. A
strobe is a pulse used by one computer to alert the other that it will send data.
In some systems, the receiving unit sends an acknowledge signal back to the
sender. This is handshaking.
Source-initiated strobe
Data bus
SOURCE
UNIT
DESTINATION
UNIT
Strobe
Data
Valid data
Strobe
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There are four general methods for transmitting data asynchronously,
depending on whether the source or destination initiates the transfer and on
whether or not handshaking is used. In source-initiated strobe, the source first
places data onto the data bus. After giving it some time to settle down, it
activates the strobe signal. This alerts the destination device that data is ready
and the destination device reads in the data. After some set amount of time,
the source unit de-asserts the strobe and then removes data from the bus.
Some devices may load in data on the falling edge of the strobe, so the order of
the last two operations is important.
Note that the source device never receives confirmation that the data was
received successfully. That is a tradeoff inherent in this type of transfer. The
advantage gained is that hardware requirements are reduced. This type of
transfer could be useful for such operations as updating remote LED displays.
Destination-initiated strobe
Data bus
SOURCE
UNIT
DESTINATION
UNIT
Strobe
Data
Valid data
Strobe
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Destination-initiated strobe is similar to source-initiated strobe except, as its
name implies, the destination device initiates the data transfer by asserting the
strobe. This causes data to be placed on the data bus; the destination device
then reads in the data. After some preset amount of time, it releases the strobe,
which signals the source unit to stop sending valid data. A circuit that uses
this form of transmission might have a tri-state buffer as part of the source
unit. The data from the source unit is input to the tri-sate buffer. The output
of the buffer is connected to the data bus. The strobe is connected to the buffer
enable.
As with the source-initiated strobe, there is no guarantee that the data read in
by the destination device is valid. For instance, if the source device was turned
off, the strobe would still be initiated, all zeroes would be read in and the
strobe would be de-asserted. The destination device cannot tell if the all-zero
data was read in from an active device or a powered-down device.
Source-initiated transfer using
handshaking
Data bus
SOURCE
UNIT
Data bus
Data valid
Data accepted
DESTINATION
UNIT
Valid data
Data valid
Data accepted
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Handshaking removes the uncertainty in asynchronous data transfers by
providing confirmation that data was read in successfully. The tradeoff is the
increased hardware requirements. In source-initiated data transfer using
handshaking, the source unit places valid data onto the data bus and then
asserts a data valid signal. So far this is the same as before, with the data valid
signal replacing the strobe.
But now something different happens. The data valid signal does not stay high
for some predetermined amount of time. Instead it stays high until the
destination unit tells it to stop. The destination unit reads in the data and then
asserts a data accepted signal. This tells the source that the data has been
accepted and to remove it from the bus. It de-asserts the data valid signal and
removes data from the bus. The destination unit acknowledges this by deasserting its data accepted signal, which in turn tells the source device that it
may now initiate another data transfer.
One thing not noted here is what to do if the destination device never accepts
the data (for example, if it is turned off). The source unit might include a
timer that will check for this condition and report an error when it occurs.
Destination-initiated transfer
using handshaking
Data bus
SOURCE
UNIT
Data bus
Data valid
Ready for data
DESTINATION
UNIT
Valid data
Data valid
Ready for data
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Destination-initiated transfer using handshaking is also similar to its nonhandshaking counterpart. The ready for data signal replaces the strobe and is
asserted by the destination device to request data. The source device responds
by placing data onto the bus and then, after some predetermined amount of
time to allow for settling, it asserts the data valid signal. This tells the
destination device that it can now read in the data. It does so and signals the
source device by de-asserting the ready for data signal. This is followed by the
source unit removing the data from the data bus and resetting the data valid
signal. This notifies the destination unit that it can now request another data
transfer.
Both source- and destination-initiated transfer using handshaking are similar to
the process used by the Basic Computer.
Synchronous serial transmission
Share a common clock (short distance)
u Separate clocks with synchronization
signals (long distance)
u Bits are transmitted continuously
u
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Serial data transmission may be synchronous or asynchronous. In synchronous
transmission, the source and destination units share a common clock. This is
useful when data must be transmitted within a computer or over very short
distances for which both devices may access a single clock.
Data can also be transmitted over longer distances synchronously. To do this,
both the source and destination units must also send synchronization signals
periodically to maintain calibration between the two clocks.
Unlike asynchronous data transmission, in which the transmission line is used
only when sending data, synchronous data transmission requires that
transmission occurs continuously. When no data is to be sent, bits must still be
transmitted to maintain synchronization.
Asynchronous serial transmission
Bits are transmitted as data is available
u Data is sent in the following format:
u
– Start bit (0)
– Character bits
– Stop bit(s) (1)
u
Line is set to 1 when idle
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In asynchronous serial data transmission, the transmission line is only used
when information is transferred. When not in use, the line is set to 1. To send
a single character, the source sends a start bit, which is 0, for one clock cycle.
This signals the destination unit to receive data. Following this, the source
unit places the character data onto the transmission line, one bit per clock
cycle. Finally, it sends one or more stop bits, which is 1.
The two units must agree on a few things beforehand. First of all, they must
both expect the character to contain the same number of bits. They must also
agree on whether or not there will be a parity bit transmitted and, if so,
whether it will be odd or even parity. Finally, they must agree on the number
of stop bits, usually 1, 1 1/2 or 2. (These numbers refer to the number of clock
periods. For example, for 57600 bits per second, these correspond to 17.36 us,
26.04 us and 34.72 us, respectively.)
UARTs
Universal Asynchronous Receiver/
Transmitter (also called Asynchronous
Communication Interface)
u Performs serial/parallel conversion
u Bidirectional (input and output)
u
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A Universal Asynchronous Receiver/Transmitter, or UART, is a specialized
circuit or chip used to transmit and receive serial data. The serial ports of most
computers are designed to use UART chips. On the transmitting side, it
receives data from the computer in parallel form. It converts the data to serial
form and transmits it, along with the requisite start, parity and stop bits. The
receiving UART performs exactly the opposite functions. It receives the data,
stripping out the start, parity and stop bits, and converts it to parallel form.
The parallel data is then made available to the computer.
As noted previously, both the sender and the receiver must agree on the parity,
the number of character bits and the number of stop bits.
UARTs
See figure 11.8, p. 399 of the textbook.
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Here is a block diagram of a generic UART. First we’ll review the
components and then we’ll go through the functions of the UART.
The transmitter register is used to hold a character to be transmitted. It is
loaded in parallel. It makes its data available to a shift register which loads the
data in parallel and outputs it serially. The receiver register works exactly the
opposite way. Serial data is received by another shift register which converts
it to parallel form. The receiver register reads it in parallel. The register
selects (RS), read (RD) and write (WR) signals, along with the chip select
(CS), are combined to write data to and read data from the registers.
The computer configures the UART by sending commands to the control
register. These commands include such operations as setting the baud rate
(number of bits per second), the parity and the number of stop bits. The status
register is used to store information the computer will need. Two status bits in
all UARTs tell whether the transmitter and receiver registers are full or empty.
UARTs
See figure 11.8, p. 399 of the textbook.
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To transmit data, this process is followed. If not already done, the CPU initializes the
UART, setting the speed and numbers of character and stop bits. This is done only
once regardless of the number of characters to be transmitted. To transmit a character,
the CPU reads the status register to see if the transmitter register is empty. If not, it
may continue to read the status register periodically until it is ready. This is done to
avoid overwriting the previous data. Once it is empty the CPU writes data to the
transmitter register. The UART modifies its flag to indicate that the transmitter
register is not empty.
Next, the UART moves this data, along with the start and stop bit(s), in parallel to the
shift register and resets its flag to empty. (This assumes that the shift register is empty.
Internal circuitry assures that data in the shift register is not overwritten.) The UART
transmits data serially by shifting it out of the shift register.
The process of receiving data is similar. The receiver shift register accepts serial data,
strips off the start and stop bit(s), and moves it to the receiver register in parallel,
setting its flag. The CPU reads the flag and, when indicating that the receiver register
contains data, reads in the data; this causes the UART to reset its flag.
Notice that while one piece of data is being transmitted or received serially, another
may be input to or output from the CPU. This set up is called double buffering; it
improves performance by avoiding delays between characters.
UART errors
Parity error
u Framing error
u Overrun error
u
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As with most things in life, errors can and do occur. The UART interface
checks for three types of transmission errors. Parity errors occur when the
parity, or number of 1’s, is incorrect. Framing errors occur when the number
of stop bits is incorrect. Overrun errors occur when incoming data overwrites
data in the receiver register which has not yet been read in by the CPU,
resulting in lost data. The status register contains a bit for each of these
conditions.
FIFOs
First In First Out
u Used to buffer data during transmission
u Can be serial or parallel
u
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A FIFO is a buffer which stores data in a first-in first-out manner. It is
essentially a hardware queue. Data is input to the back end of the FIFO and is
propagated forward. The first piece of data in the queue is the only one that
can be output. FIFOs are used as data buffers; they can process data either
serially or in parallel.
FIFOs
See figure 11.9, p. 401 of the textbook.
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This figure shows a circuit diagram for a 4x4 parallel FIFO. The registers at the top of the
diagram, R1, R2, R3 and R4, hold the actual data. The rest of the circuit keeps track of which
registers contain valid data and handle I/O operations. Each register has a corresponding SR
flip-flop, Fi, which indicates the status of register Ri. If Fi=0, Ri does not contain valid data;
otherwise it does. The inverted output of the leftmost flip-flop, F1, drives the output signal
called input ready. If R1 contains valid data, F1=1 and input ready=0. This signals the outside
world not to write data to the FIFO. If R1 does not contain valid data, then input ready=1 and
the FIFO may receive valid data. The output ready signal is 1 whenver F4=1, which occurs
whenever R4 contains valid data. Thus it is only set when the FIFO contains data ready to be
output. There is also an input called master clear. By resetting each SR flip-flop to zero, it
marks all registers Ri as not having valid data.
Now let’s look at what happens when data is input to the FIFO. Assume that initially it has
one valid piece of data. To input the data, an external device checks the status of input ready.
If it is 1, then the FIFO can accept at least one more data input, so the external device places
its data on the data input lines and asserts the insert signal. This loads the data into R1. It also
sets F1 to 1, which in turn sets F’1 to zero, disabling the clock. Since the FIFO initially had
more than one location available, F2=0 and F’2=1, so the clock for R2 is activated,
propagating the data from R1 to R2. The R2 clock signal is also fed back, both setting F2=1
and F1=0. This same process is followed as the data propagates to R3. Once the data reaches
R3, it stops because R4 already has data; F4=1, so F’4=0 and the clock of R4 is not activated.
To read data from the FIFO, the external device simply reads the data from the data output
pins and asserts the delete signal. This resets F4 to zero, marking the contents of R4 as invalid
data. Other data in the FIFO will now propagate forward as in the case of inserting data.
Data transfer modes
Programmed I/O
u Interrupt-initiated I/O
u Direct memory access
u
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I/O transfers are handled in one of three ways. In programmed I/O the
computer program under execution has specific instructions which access the
I/O device. Interrupt-initiated I/O occurs when the I/O device issues an
interrupt signal to the CPU which causes it to suspend the program currently
under execution and to service the I/O device. It is possible to perform I/O
operations without involving the CPU at all. This is referred to as direct
memory access, or DMA. We will discuss each of these in more detail shortly.
Programmed I/O
Data is transferred between an I/O device
and the CPU, and between the CPU and
memory, but not directly between the I/O
device and memory
u CPU may poll I/O device to determine
data request or availability
u
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Programmed I/O transfers data between the CPU and an I/O device. The data
may, in turn, be transferred between the CPU and memory. However,
programmed I/O does not allow data to be transferred directly between an I/O
device and memory.
In programmed I/O the program must not only transfer the data, but it must
also make sure the data is ready. This is often accomplished via a status bit
which is set when the I/O device is ready to transfer data. This could be used
with the UART described earlier, which has a bit in its status register to
indicate whether or not input data is ready.
Interrupt-driven I/O
I/O device sends interrupt request to the
CPU
u CPU calls a subroutine which processes
the interrupt
u Vectored or non-vectored interrupt
u Example: Basic Computer I/O (nonvectored interrupt)
u
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Constantly polling an I/O device until it is ready to transfer data is an
inefficient use of CPU power. Interrupt-driven I/O is one way to relieve the
CPU of this task. In this I/O methodology, the I/O device sends an interrupt
signal to the CPU when it is ready to transfer data. The CPU finishes its
current instruction and then, if interrupts are enabled, calls an interrupt service
routine to process the interrupt.
If the CPU has more than one I/O device which sources interrupts, it must
differentiate them. Vectored interrupts supply information to the CPU, the
interrupt vector, which determines the location in memory of the interrupt
service routine. Each I/O device would have its own routine. Non-vectored
interrupts, often assigned unique input pins on a CPU, call routines at fixed
locations. The Basic Computer uses non-vectored interrupt-driven I/O.
Priority interrupts
Some interrupts are more important or
time-critical than others
u Daisy-chaining priority
u Parallel priority interrupt
u
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Some interrupts are more important or time-critical than others. For example,
a computer screen must be updated every 33 ms or so, and it must be updated
very nearly at those times in order to avoid screen flicker. If the computer is
reading data from a disk when the screen needs to be updated, the disk transfer
can wait.
There are two primary methods of implementing priority interrupts in
hardware: daisy-chaining and parallel priority interrupts. Explanations of both
follow.
Daisy-chaining
See figure 11.12, p. 409 of the textbook.
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This figure shows how to implement priority interrupts via daisy chaining.
Each device supplies an interrupt request input to the CPU; all the interrupt
requests are wire-ored together to generate a single interrupt signal. When the
CPU receives an interrupt, it doesn’t know which device generated the
interrupt request. When ready, the CPU sets INTACK to 1, thus initiating the
interrupt acknowledge. Device 1 receives this signal at its PI input. If it
requested the interrupt, it sets its PO to zero and outputs its interrupt vector at
VAD1. If it did not request an interrupt, it sets PO to 1, thus passing the
interrupt acknowledge to the next device.
A device can be in one of three states. If PI=1 and PO=1, it could control the
interrupt but does not want to do so. If PI=1 and PO=0 it is controlling the
interrupt. Finally, if PI=0 and PO=0 it is pre-empted by an interrupt of higher
priority, whether or not it requested an interrupt. It is never possible to be in a
state where PI=0 and PO=1. Note that interrupts can themselves be interrupted
by an interrupt of higher priority.
Daisy-chaining: stage design
See figure 11.13, p. 410 of the textbook.
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This figure shows the internal organization of a stage of the daisy-chained
priority hardware. If an interrupt is requested, the output of the interrupt
request flip-flop, RF, is set to 1. If PI=1, the VAD lines are enabled and the
vector address is made available to the bus. Also, PO is set to zero. After
some sufficient predeterined delay, the flip-flop is reset to zero. By this time
the CPU already will have begun servicing the interrupt.
If PI=0, VAD is not enabled, PO=0 and RF is never reset. This allows
preempted interrupts to remain pending and not become lost.
Parallel priority interrupts
See figure 11.14, p. 411 of the textbook.
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It is also possible to arbitrate interrupt requests in parallel by using a priority
encoder. As shown in this figure, each device has its own interrupt bit as well
as its own interrupt mask, which enables or disables the interrupt. The enabled
bits are input to a priority encoder which encodes the active interrupt request.
If more than one interrupt request is active, it encodes the request of highest
priority. If the interrupts overall are enabled, i.e. IEN=1, and any interrupt is
activated, i.e. IST=1, an interrupt request is issued to the CPU. Once it is
acknowledged, the vectored address, which contains the encoded priority
interrupt, is forwarded to the CPU, which then invokes the proper interrupt
service routine.
Interrupt process
The process used by the Basic Computer
1. Finish the current instruction!
2. Push return address onto the stack
3. Acknowledge interrupt; disable
further interrupts
4. Go to interrupt service routine
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The interrupt process, regardless of how the interrupt is signaled, is very
similar to the process used in the Basic Computer. First and foremost, the
CPU finishes executing the current instruction. Then it pushes the return
address onto the stack and acknowledges the interrupt. Also, it disable further
interrupts, at least until the interrupt service routine is initiated. If the interrupt
is vectored, the CPU reads in the vectored address and goes to the routine at
that address; otherwise it goes to the routine at the predetermined address
associated with the interrupt.
Direct Memory Access (DMA)
Useful for transfers of blocks of data
between I/O and memory (e.g. loading
programs from disk, screen refresh)
u DMA controller issues control signals,
address
u Coordinates control with CPU
u
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Direct Memory Access, or DMA, is an efficient method for transferring data
between memory and an I/O device directly, without involving the CPU. Such
transfers are much faster than moving data between memory and the CPU and
between the CPU and an I/O device. Loading programs from disk into
memory is a function well served by DMA.
Under DMA transfer, a DMA controller issues the necessary signals to the
computer system, including address and control information. It coordinates
with the CPU to make sure the CPU tri-states its equivalent pins to avoid
conflicts.
DMA controller - interface
See figure 11.16, p. 416 of the textbook.
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The DMA controller gains control of the system buses only after obtaining
permission from the CPU. The DMA controller issues a Bus Request to the
CPU, thus asking for permission to perform a DMA transfer. When it is ready
to allow this, the CPU issues a Bus Grant and tri-states its address, data and
control pins. The DMA controller then performs the data transfer. When
finished, the DMA controller de-asserts the Bus Request. The CPU then deasserts the Bus Grant and reactivates its other pins, continuing with its
previous tasks.
DMA controller - block diagram
See figure 11.17, p. 417 of the textbook.
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Internally, the DMA controller has several components it needs in order to
perform its functions. It has three registers. The address register is used to
specify the address of the memory location to be accessed. After each word is
transferred, this register is incremented to point to the next location. The word
count register, as its name implies, contains the number of words to be
transferred. After every word transfer, this register is decremented. The
control register contains information regarding the mode of transfer. In burst
transfer mode, the DMA controller retains control of the system buses as it
transfers the entire block of data. In cycle stealing mode, the DMA controller
transfers one word at a time, interleaving its operations with those of the CPU.
The DMA controller also has a logic section which handles interaction with
the CPU and with the I/O device. The DMA select is an enable signal;
systems may have more than one DMA controller. The register select is used
by the CPU when accessing the registers within a DMA controller; each
register is treated as a separate I/O port by the CPU. The read and write
signals are used both when communicating with the CPU and when
performing the DMA transfer. The Bus Request and Bus Grant signals
operate as described previously. The DMA Request and DMA Acknowledge
signals interface directly with the I/O device. They implement a handshaking
between the two.
DMA initialization
Set starting address of memory block
u Set word count (i.e. block size)
u Set transfer direction control (read/write)
u Initiate DMA transfer signal
u
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Before performing a DMA transfer, the DMA controller must be initialized by
the CPU. To do this the CPU sends the following information to the DMA
controller: the starting address in memory; the word count, i.e. the number of
words to be transferred; and the control word, which specifies the transfer
mode and direction. The CPU then sends a control word to the DMA
controller instructing it to initiate a Bus Request.
DMA configuration
See figure 11.18, p. 419 of the textbook.
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This figure shows how a DMA controller is configured in a computer system.
Note that the Bus Grant signal is not bidirectional, although it is drawn that
way here. That signal is sent from the CPU to the DMA controller; it cannot
travel in the opposite direction.
Also note that the data bus connects to both the DMA controller and the I/O
device. The connection to the DMA controller is used solely to load the
registers and issue commands. The actual data to be transferred passes
between memory and the I/O device and does not pass through the DMA
controller.
Input-Output Processor (IOP)
Used to relieve CPU of I/O tasks
u Useful for batch processing
u IOP can handle data files as well as
program files
u Transfer is similar to DMA transfer
u
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I/O processors are used to relieve the CPU of I/O tasks by interfacing directly
with the I/O devices. This is similar to DMA controllers, except each I/O
processor (IOP) can handle several I/O devices. Systems which perform batch
processing or time-sharing may benefit from I/O processors which can move
both programs and data files in and out of memory, thus freeing up the CPU to
execute programs.
IOP/CPU configuration
See figure 11.19, p. 421 of the textbook.
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The IOP interfaces to the computer system in a manner similar to that of a
DMA controller. The CPU issues commands to the IOP, which acts on those
commands to perform the requisite I/O operation. The IOP performs the task
and writes a status word into a predetermined memory location which the CPU
will examine at its leisure.
IOP/CPU communication
See figure 11.20, p. 422 of the textbook.
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A more complete description of how this works is given in this diagram. First
the CPU sends a status request to the I/O processor, which returns its status to
a predetermined memory location. The CPU reads this result and, if OK,
sends a command to the IOP to start an I/O operation. The CPU then
continues with another program while the IOP conducts the data transfer, via
DMA, and prepares a status report. When finished, it interrupts the CPU,
which in turn requests the status of the transfer. The IOP moves the status
word to a predetermined memory location from which the CPU reads it in. At
this point, the CPU can perform whatever operations it needs to on the data.
Serial communication
Data communication processor: distributes
and collects data from many remote
terminals
– Communicates via individual connections, as
opposed to the bus used by IOPs
– Data and control are transferred serially
– Communicates with the CPU in the same way
as an IOP
 1997 John D. Carpinelli, All Rights Reserved
35
Unlike an IOP, a data communication processor interfaces to each I/O device
through a dedicated serial connection. Both data and control information are
sent via this connection. It communicates with the CPU just as an IOP does.
Serial communication - MODEM
MODEM: modulator-demodulator
– Converts data to an audio signal
– Can be synchronous or asynchronous
– Half-duplex or full-duplex
 1997 John D. Carpinelli, All Rights Reserved
36
A modem (modulator-demodulator) is used to establish serial communications,
most commonly over standard telephone lines. The sender converts the data to
be sent to an audio signal and then transmits that signal. The destination unit
converts this signal back to the original data. Depending on the units
connected, this may be synchronous or asynchronous. The communication
may be half duplex, i.e. only one of the two units can send data at a given time,
or full duplex. In full duplex mode, each unit can transmit data to the other
unit simultaneously. This is accomplished by using different carrier
frequencies.
Serial communication - modes
Block transfer
u Longitudinal Redundancy Check (LRC)
u Cyclic Redundancy Check (CRC)
u Protocols
u
 1997 John D. Carpinelli, All Rights Reserved
37
Asynchronous communications require start and stop bits for each character
transmitted; for large blocks of data this presents significant overhead. In synchronous
transmission, these bits are not used. The two units have internal clocks with the same
frequency; the frequency of the incoming bit stream is used to adjust the receiver clock
to maintain synchronization.
In synchronous transmission, data is sent in blocks. Special characters at the
beginning and end of the block supply information needed to complete successful data
transmission. Another thing needed to check on the successful transmission is error
checking. First, each character includes a parity bit which determines if there is a
single bit error within the character. There are also two other checks which can be
performed. Longitudinal Redundancy Check (LRC) is basically a parity check for the
entire block. It is the exclusive-or of all characters in the block; it is transmitted along
with the characters. The destination unit reads the incoming characters, calculates the
LRC and compares it to the value transmitted. If they do not match, it discards the
block and sends a request for retransmission. A third method of checking data validity
is the Cyclic Redundancy Check (CRC). This involves passing the characters
received through a feedback shift register which includes some exclusive-or gates to
generate a value. This CRC value is used to detect burst errors.
A critical component in successful transmission is that both the source and destination
units expect data to be transmitted using the same rules. These rules are called a
protocol. They establish and terminate transfers, identify sender and receiver and
perform error checking.
Special characters
Character
Function
SYN
SOH
STX/ETX
EOT
ACK/NAK
Establish synchronization
Start of header
Start/end of text
End of transmission
Acknowledge/Negative ack.
 1997 John D. Carpinelli, All Rights Reserved
38
When transmitting data using a character-oriented protocol, several special
characters are needed. SYN is used to establish synchronization between the
two units. SOH denotes the start of the block header. STX and ETX show the
start and end of the block of text being sent. BCC is a checking value, either
the LRC or CRC of the data.
The receiver processes incoming data and sends one of two characters back to
the sender. If the data was received properly, it sends an acknowledge, ACK;
if not, it returns a negative acknowledge, NAK.
Transmission example
SYN SYN SOH Header STX Text ETX BCC
 1997 John D. Carpinelli, All Rights Reserved
39
Here is a simple example of data transmission using a character-oriented
protocol. First, two SYN characters are sent to establish synchronization.
Then a SOH character is sent, followed by the header information. The header
may include address and control information. Then the text of the block is
sent, surrounded by an STX and an ETX character. Finally the BCC character
and the value of either the LRC or CRC are sent.
Transmission example
See table 11.5, p. 434 of the textbook.
 1997 John D. Carpinelli, All Rights Reserved
40
This figure shows a typical transmission from a terminal to the processor.
Notice that the header is fairly simple; it contains the address of the source
terminal. The text may be of any length up to a maximum specified by the
protocol. Transmission is ended by sending the value of LRC.
Transmission example
See table 11.6, p. 435 of the textbook.
 1997 John D. Carpinelli, All Rights Reserved
41
The processor would receive this request and, if there were no transmission
errors, send two SYN characters and an ACK. It would process the request,
issuing SYN characters while the line is idle in order to maintain
synchronization. It would then send the result to the terminal using exactly the
same procedure. It would also finish with the value of its LRC.
There is one problem not yet discussed: what if one of the characters of data
has the same ASCII value as a control character, such as SOH or ETX? One
method to resolve this is the Data Link Escape (DLE) character. It is inserted
in front of each control character. For example, the leading SOH character is
actually transmitted as DLE SOH. If the text portion contains data with the
DLE bit pattern, it is transmitted with an additional DLE character following
it. The destination unit performs the inverse operation and restores the data.
Bit-oriented protocol
Flag
01111110
Address
8 bits
 1997 John D. Carpinelli, All Rights Reserved
Control Info Frame check
8 bits
16 bits
Flag
01111110
42
Bit oriented protocols are used to transmit data that may not be characteroriented. As shown in this figure, the frame used to transmit the data begins
with an 8-bit flag 0111 1110. This is followed by the address field which, as
its name implies, contains the address of the device. The control field
specifies information about the transfer associated with this frame. We will
look at this field in more detail next. The information field is the binary data
to be transmitted; it may be of any length. After the data comes the frame
check, which is a CRC value used to detect transmission errors. Finally, a flag
terminates the frame.
Just as in the character-oriented protocol, it is possible to have a problem in
transmission due to a valid data value. In this case it occurs if the bit pattern
0111 1110, the same value as the flag, occurs in the data. The bit oriented
protocol uses zero insertion to avoid this problem. After any five consecutive
ones, a zero is inserted into the data stream; the destination unit removes this
bit to restore the original bit pattern. Since the flag has six consecutive ones,
this assures that an erroneous flag will not occur.
Control fields
See figure 11.27, p. 438 of the textbook.
 1997 John D. Carpinelli, All Rights Reserved
43
Here are the three control field formats in the bit oriented protocol. The
information transfer format is used when the frame contains data to be
transmitted. The Ns and Nr fields indicate the number of sent and successfully
received frames. The P/F bit is used to request a transfer and to denote that the
final packet has been sent.
The supervisory format is used to acknowledge receipt of a previous frame and
to convey status and error information. Frames with this control field format
do not have an information field. The unnumbered format is used to initialize
and to terminate links and to report errors.
Summary
þ I/O
interfacing
þ Asynchronous data transfer
þ Interrupt driven I/O
þ DMA transfers
þ I/O processors
þ Serial communications
þ Next module: memory systems
 1997 John D. Carpinelli, All Rights Reserved
44
This module has examined various modes of I/O interfacing. We have
examined asynchronous data transfers and the hardware required to implement
them. We also reviewed I/O interrupts and their implementation. We also
looked at DMA transfers and I/O processors, two methods used to alleviate
the CPU of I/O tasks. We also discussed serial communications.
In the next module we will examine memory systems. We will discuss various
system design methodologies and their effects on system performance.