SWITCH-BASED DYNAMIC INTERCONNECTION NETWORKS (single-stage, and multistage) Mariam A. Salih Single stage network Multi-stage network Blockage in Multistage Interconnection Networks Single-Stage Networks In this case, a single stage of switching elements (SEs) exists between the inputs and the outputs of the network. The simplest switching element that can be used is the 2 x 2 switching element (SE). The connection in a 2×2 switch will either be straight, exchange, lower broadcast or upper broadcast as shown in the Figure. Straight; the upper input is transferred to the upper output and the lower input is transferred to the lower output. Exchange; the upper input is transferred to the lower output and the lower input is transferred to the upper output. Upper-broadcast; the upper input is broadcast to both the upper and the lower outputs. Lower-broadcast; the lower input is broadcast to both the upper and the lower outputs. A two function switch box can assume either the straight or exchange state A four function switch box can be any of the four legitimate state CONCEPT OF PERMUTATION NETWORK In permutation interconnection networks the information exchange requires data transfer from input set of nodes to output set of nodes and possible connections between edges are established by applying various permutations in available links. Let us look at the basic concepts of permutation with respect to interconnection network. Let us say the network has set of n input nodes and n output nodes. Permutation P for a network of 5 nodes (i.e., n = 5) is written as follows: The permutations can be combined. Where two or more permutations are applied in sequence, e.g. if P1 and P2 are two permutations defined as follows: 1 1 1 2 2 2 3 3 3 A single stage network To establish communication between a given input (source) to a given output (destination), data has to be circulated a number of times around the network. 1)Shuffle-Exchange A well-known connection pattern for interconnecting the inputs and the outputs of a single-stage network is the Shuffle-Exchange. 2) Butterfly permutation: This permutation is obtained by interchanging the most significant bit in address with least significant bit. Multistage Networks Multistage interconnection networks (MINs) were introduced as a means to improve some of the limitations of the single bus. The most undesirable single bus limitation that MINs is set to improve is the availability of only one single path between the source and the destination modules. Multistage Networks a general MIN consists of a number of stages each consisting of a set of switching elements. Stages are connected to each other using Inter-stage Connection (ISC) Pattern. There are few Inter-stage Connection are provided by hardware. 1) Multistage butterfly 2) The Omega Network The Omega Network represents another wellknown type of MINs. (Shuffle– Exchange networks) Number of stages log2 (n) Number of switches in each stage n/2 Total number of switches (n/2)*log2(n) Example: Figure illustrates the case of an N = 8 Omega network. As can be seen from the figure, the inputs to each stage follow the shuffle interconnection pattern. Final design 3)Clos network: This network was developed by Clos (1953). Consider an I input and O output network Number N is chosen such that (I= n.x) and (O=p.y). In Clos network input stage will consist of X switches each having n input lines and z output lines. The last stage will consist of Y switches each having m input lines and p output lines the middle stage will consist of z crossbar switches, each of size X × Y. To utilize all inputs the value of Z is kept greater than or equal to n and p. The connection between various stages is made as follows: all outputs of 1st crossbar switch of first stage are joined with 1st input of all switches of middle stage. all outputs of 2nd crossbar switch of first stage are joined with 2nd input of all switches of middle stage, and so on… Similar connections are made between middle stage and output stage. Example : Consider a Clos network with, 3 stages and 3×3 switches in each stage 4) The Banyan Network In the banyan If the number of inputs, for example, processors, in an MIN is N and the number of outputs, for example, memory modules, is N, the number of MIN stages is log2 (N) and the number of SEs per stage is N/2, Each stage use inverse shuffle permutation. Destination-tag routing In destination-tag routing, switch settings are determined by the message destination. The most significant bit of the destination address is used to select the output of the switch in the first stage; if the most significant bit is 0, the upper output is selected, if it is 1, the lower output is selected. The next-most significant bit of the destination address is used to select the output of the switch in the next stage, and so on until the final output has been selected. Example of tag Routing destined = 4 (= 100 ) 0 1 2 0 4 1 2 2 3 3 4 4 5 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 0 1 2 0 4 1 2 2 3 3 4 4 5 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 5 5 6 7 4 6 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 4 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 4 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 5 5 6 7 4 6 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 5 4 5 6 6 7 7 Example of tag Routing destined = 4 (= 100 ) 2 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 7 Multiple Concurrent Paths 0 1 0 5 2 3 1 2 7 3 4 4 5 5 6 6 7 7 Multiple Concurrent Paths 0 1 0 5 2 3 1 2 7 3 4 4 5 5 6 6 7 7 Multiple Concurrent Paths 0 0 1 1 2 2 3 3 4 5 5 6 7 4 5 7 6 7 Multiple Concurrent Paths 0 0 1 1 2 2 3 3 4 5 4 5 5 6 6 7 7 7 Multiple Concurrent Paths 0 0 1 1 2 2 3 3 4 5 4 5 5 6 6 7 7 7 Multiple Concurrent Paths 0 0 1 1 2 2 3 3 4 4 5 5 5 6 6 7 7 7 Multiple Concurrent Paths 0 1 0 5 2 3 1 2 7 3 4 4 5 5 6 7 1 6 7 Multiple Concurrent Paths 0 1 0 5 2 3 1 2 7 3 4 4 5 5 6 7 1 6 7 Multiple Concurrent Paths 0 0 1 1 2 2 3 1 3 4 5 4 5 6 7 5 7 6 7 Multiple Concurrent Paths 0 0 1 1 2 1 3 3 4 2 5 4 5 5 6 6 7 7 7 Multiple Concurrent Paths 0 1 0 1 1 2 2 3 3 4 5 4 5 5 6 6 7 7 7 Multiple Concurrent Paths 0 0 1 1 1 2 2 3 3 4 4 5 5 5 6 6 7 7 7 Source (000) -> destination (101) Source (101) -> destination (011) Source (110) -> destination (010) Blockage in Multistage Interconnection Networks A number of classification criteria exist for MINs. Among these criteria is the criterion of blockage. Blocking Networks; Blocking networks possess the property that in the presence of a currently established interconnection between a pair of input/output, the arrival of a request for a new interconnection between two arbitrary unused input and output may or may not be possible. Nonblocking Networks; Nonblocking networks are characterized by the property that in the presence of a currently established connection between any pair of input/output, it will always be possible to establish a connection between any arbitrary unused pair of input/output. The Clos is a well-known example of nonblocking networks. Output Port Contention 0 1 0 4 1 2 2 3 3 4 4 5 5 6 7 4 6 7 Output Port Contention 0 1 0 4 1 2 2 3 3 4 4 5 5 6 6 7 4 7 Output Port Contention 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 4 7 Output Port Contention 0 0 1 1 2 2 3 3 4 4 5 6 7 4 5 4 6 7 Output Port Contention 0 0 1 1 2 2 3 3 4 4 4 5 4 5 6 6 7 7 Output Port Contention 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Output Port Contention 0 0 1 1 2 2 3 3 4 4 4 5 5 6 6 7 7 Path Contention 0 2 0 1 1 2 2 3 3 4 3 4 5 5 6 6 7 7 Path Contention 0 2 0 1 1 2 2 3 3 4 3 4 5 5 6 6 7 7 Path Contention 0 2 0 1 3 1 2 2 3 3 4 4 5 5 6 6 7 7 Path Contention 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Path Contention 0 1 0 3 1 2 2 3 3 4 4 5 5 6 6 7 7 Path Contention 0 0 1 1 2 3 2 3 3 4 4 5 5 6 6 7 7 Path Contention 0 0 1 1 2 2 3 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Performance Degradation 0 5 1 2 0 1 0 2 3 3 4 3 4 5 2 5 6 4 6 7 6 7 Performance Degradation 0 5 0 1 3 1 2 2 3 2 3 4 0 4 5 4 5 6 6 7 6 7 Performance Degradation 0 3 0 1 5 1 2 2 2 3 3 4 0 4 5 4 5 6 6 7 6 7 Performance Degradation 0 3 0 1 0 1 2 2 2 3 3 4 5 4 5 4 5 6 6 7 6 7 Performance Degradation 0 0 0 1 3 1 2 3 2 2 3 4 4 5 5 6 6 7 6 7 Performance Degradation 0 0 0 1 3 1 2 2 3 2 3 4 5 4 5 5 6 6 7 6 7 Performance Degradation 0 0 1 0 1 2 3 2 3 2 3 4 5 4 5 5 6 6 7 6 7 Performance Degradation 0 0 0 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 7 Myrinet-2000 Clos Network for 128 Hosts Network Topology • Backplane of the M3E128 Switch • M3-S16-8F fiber line card (8 ports) Simple Quiz..