Boris Murmann
Stanford University
Department of Electrical Engineering murmann@stanford.edu

• Motivation
– Progress in digital circuits has outpaced performance growth in analog circuits by a large margin
• Digitally Assisted A/D Converters
– Using digital computing capabilities as a new driver to improve A/D converter energy efficiency
– Examples
• Experimental proof-of-concept result
• Next generation designs
• Conclusions
Digitally Assisted Analog C ircuits B. Murmann 2

• Trend towards ubiquitous sensing, communication and computing
– "Ambient Intelligence"
• Signal processing predominantly done in digital domain
– Rapidly improving digital capabilities, fueled by "Moore's Law"
• Irreplaceable "bottleneck" - analog circuits
– Analog-Digital Converters (ADCs)
– Digital-Analog Converters (DACs)
– Filters and amplifiers (Anti-aliasing, RF power amplification, …)
• Focus of this talk: ADCs
Digitally Assisted Analog C ircuits B. Murmann 3

10000
1000
100
10
µ
P MI
PS
(2 x /
1.
5 y ea rs)
ADC*
(2x / 4.
7 years
)
1
1987 1995 2003
15 years
* Performance measure: Bandwidth x Number of quantization levels
150x
Digitally Assisted Analog C ircuits B. Murmann 4

• Example: Cell phone
– Battery has roughly 3Wh of Energy
– For a talk time of 12 hours, can draw no more than 250mW
– Only a fraction of that power available for ADC
• In an increasing number of applications, key issue is how much performance you can squeeze into a fraction of 0.1…1Watt
• What is the trend in ADC versus digital power/energy consumption?
Digitally Assisted Analog C ircuits B. Murmann 5

• Interesting metric to look at
– How many digital gates can you toggle for the energy needed in one A/D conversion?
• Example
– Standard digital gates (NAND2) in 0.13mm CMOS consume about
6nW/Gate/MHz
• Energy/Gate = 6fJ
– State-of-the-art 10-bit ADC consumes 1mW/MSample/sec
• Energy/Conversion = 1nJ
– Energy equivalent number of gates
• 1nJ/6fJ= 166,666
Digitally Assisted Analog C ircuits B. Murmann 6

500,000
ADC
Resolution: 400,000
6bits
8bits
10bits
12bits
14bits
16bits
300,000
200,000
100,000
0.8
0.6
0.4
Feature Size [
µ m]
0.2
0.0
0
Digitally Assisted Analog C ircuits B. Murmann 7

• Energy equivalent number of gates per A/D conversion has gone through the roof
• Reason
– Digital circuits have scaled well with technology
– Analog doesn't benefit quite as much from smaller features
• Issues: Low supply voltage, low device gain, …
• Key idea
– Build "digitally assisted analog circuits"
– Find a way to leverage digital processing capabilities to improve performance and lower power of analog circuits
Digitally Assisted Analog C ircuits B. Murmann 8

Speed Precision
Matching and linearity constraints are not fundamental
Digitally Assisted Analog C ircuits
Noise Matching Linearity
Power Dissipation
B. Murmann 9

• Conventional ADC
– Precisely linear mapping from input to output
– Relies on highly linear and well matched analog components
• Digitally assisted
ADC
– A "sloppy" one-to-one mapper
– Digital postprocessor estimates ADC errors and applies corrections
V in
V in
“Accurate”
ADC
Low Complexity
“Sloppy” ADC
D accurate
D sloppy
Digital
Postprocessor
D accurate
Digitally Assisted Analog C ircuits B. Murmann 10

• Digitally assisted pipeline ADC
– Murmann & Boser, ISSCC 2003
• Minimum complexity, ultra low energy pipeline ADC
– Under development in my research group
• ADC with embedded calibration for OFDM systems
– Under development in my research group
Digitally Assisted Analog C ircuits B. Murmann 11

V in
S/H STAGE 1 STAGE N-1 STAGE N
R bits
(e.g. R=1)
V in
A/D
D
D/A
!
-
2 R
V res
"
• Bottleneck: Highly linear gain element
D=0
V in
D=1
Digitally Assisted Analog C ircuits B. Murmann 12

Conventional Precision Amplifier Open-Loop Amplifier
+ Lower Noise
+ Increased Signal
Range
+ Lower Power
+ Faster
– Nonlinear
 Use DSP to linearize!
Digitally Assisted Analog C ircuits B. Murmann 13

Analog
Nonlinearity
Digital
Inverse
Vin Dout Dout,corr
Modulation
Parameters
System
ID
• Use digital system identification techniques to determine optimum post distortion function
• Possible (and often necessary) to track correction parameters without interrupting normal ADC operation
Digitally Assisted Analog C ircuits B. Murmann 14

LOGIC
REFERENCE
AND BIAS
PIPELINE
BACKEND
STAGE1
CLK
SHA
• 12bit, 75MSamples/sec, 0.35µm, post-processor off chip
• Based on commercial part (Analog Devices AD9235)
Digitally Assisted Analog C ircuits B. Murmann 15

~8400 Gates
(0.042mm
2 in
0.13
µ m)
• Proof of concept design
– Open-loop amplifier only in first, most critical stage
• Judicious analog/digital co-design
– Only two corretion parameters (linear and cubic amplifier error)
Digitally Assisted Analog C ircuits B. Murmann 16

20
Post-Proc. OFF
Post-Proc. ON
10
0
-10
-20
0
Digitally Assisted Analog C ircuits
1000 2000
Code
3000 4000
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60
50
40
30
20
10
0
Commercial Part
(Precision Amplifier)
Digitally Assisted Analog C ircuits
-62% (33mW)
This Work
(Simple Amplifier)
B. Murmann 18

• 8400 Gates, 64 bytes RAM, 64kBit ROM
• Place & Route in 0.35
µ m technology
Area=1.4mm
2 (18%)
Pipelined ADC
(7.9 mm 2 )
Post-Processor
Digitally Assisted Analog C ircuits
40
30
20
10
0
Power=10.5mW (3.6%)
Amplifier
Savings
Post-
Processor
B. Murmann 19

• Proof-of-concept design showed that the idea of digital assistance works, but power savings were not "revolutionary"
• As a more aggressive step, it is now interesting to explore the question:
How many "analog" transistors do we really need?
Digitally Assisted Analog C ircuits B. Murmann 20

!
2
V in
!
1
!
1
C
DAC
!
2 V res
!
2 !
1 !
1 C
L
(next stage)
V
REFN,P
V
DAC
• Use a single active device, operated like a charge pump to implement gain element
• Highly energy efficient, low noise, …
• Gain is imprecise and nonlinear, but post-processor can take care of that
Digitally Assisted Analog C ircuits B. Murmann 21

1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
Minimalistic Pipeline
ISSCC 1998-2005
Expon. (ISSCC 1998-2005)
1.E+00
30 40 50 60 70
SN(D)R [dB]
80 90 100 110
• 9-bit, "minimalistic" pipeline ADC prototype in 90nm technology
– Roughly 20,000 gates used for digital post-processing
– Only 7pJ per conversion, ~50x below state-of the art
Digitally Assisted Analog C ircuits B. Murmann 22

• At 10MSamples/s (~video-rate), this ADC consumes only 70 µ W
• Can be powered from a 1cm 3 size battery for more than 1 year!
– A state-of the art ADC will drain the battery within a few days…
Digitally Assisted Analog C ircuits B. Murmann 23

An l a og O p er a tions
(
2 p
J
) D igit l a
Post p rocessing
( 5 p
J
)
29
%
7
1
%
• Energy/conversion is dominated by digital postprocessing
• Great news!
– Energy efficiency will improve further when design is scaled to
65nm, 45nm, …
Digitally Assisted Analog C ircuits B. Murmann 24

• The "sloppier" we make the analog portion of the
ADC, the more parameters we need to estimate and track
– Can become quite complex or even impossible without disturbing normal ADC operation
• Idea: "System Embedded" postprocessing and calibration of ADC
– Leverage redundancy and knowledge of certain input signal properties to estimate ADC errors
– Re-use existing system resources for ADC calibration
• Example: ADC for OFDM receivers
Digitally Assisted Analog C ircuits B. Murmann 25

pilot
error
ADC DSP FFT IFFT DAC Channel pilot f f
• Communications protocol uses "pilot tones" to measure and equalize RF channel nonidealities
• Why not use these pilots to "equalize" ADC?
– Errors in pilot signals can be used to estimate correction parameters for sloppy ADC
Digitally Assisted Analog C ircuits B. Murmann 26

Digitally Assisted Analog C ircuits
~100ms
B. Murmann 27

• Analog circuit improvements lag progress of digital functions
– Technology scaling only conditionally benefits analog circuit performance
• Digitally assisted analog circuits offload accuracy constraints to digital processor
• ADCs are obvious candidates for "digital assistance"
– The benefits of digital pre/postprocessing are also being investigated for several other analog circuit blocks
• Signal pre-distortion in RF power amplifiers
• Signal pre-distortion in DACs
• High-speed wireline interfaces
Digitally Assisted Analog C ircuits B. Murmann 28

• Key benefits
– Lower power and potentially higher speed
• Up to 100x reduction in ADC energy/conversion
– Digitally assisted ADCs will benefit from future technology scaling
• "Sloppy" circuits will be compatible with low voltage, low gain, ultimately scaled CMOS
• Key challenges
– Interdisciplinary nature of design problem
• Device modeling, circuit design
• Math, signal processing algorithms
• Inclusion of application layer
– Design complexity and turnaround time
Digitally Assisted Analog C ircuits B. Murmann 29