Chapter 6
PC Peripheral Chips - Pt 1
RTC, Timers, Keybd Ctlr
PC Architecture for
Technicians: Level-1
Systems Manufacturing Training
and Employee Development
Copyright © 1996 Intel Corp.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 1
OBJECTIVES: At the end of this section,
the student will be able to do the following:
l
Describe the Real-Time CMOS Clock Chip.
l
Discuss the CMOS Address Map.
l
Explain how to access the CMOS RAM.
l
Describe the 8254 Programmable Interval Timer.
l
Explain the function of the three Counter/Timers.
l
Describe the 8742 Keyboard Controller.
l
Discuss the functions of the Keyboard Controller.
l
Name the I/O Ports associated with the 8742.
l
Discuss the Misc. Keyboard Controller Signals.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 2
REAL-TIME
CMOS
CLOCK
Description
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 3
REAL-TIME CMOS CLOCK
l
CMOS RAM - Complimentary Metal Oxide
Semiconductor Random Access Memory
l
CMOS RAM is a small amount of low power battery backed memory used to store time & configuration
information used during the boot-up process.
The configuration information includes the number & type
of floppy drives, graphics adapter, base memory, etc.
n
The RTC is independent of the CPU & all other chips &
keeps updating time in the background.
n
l
Also know as:
RTC - Real Time Clock
n
NVRAM- Non-Volatile RAM
n
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 4
REAL-TIME CMOS CLOCK
CLOCK
BATTERY
BACKUP
RAM
INT (To IRQ8)
0
13t
14t
63t
}
USED BY CLOCK
}
USED TO STORE
CONFIGURATION
INFORMATION
CMOS CLOCK CHIP
Motorola MC146818
or DALLAS 12887
or equivalent
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 5
REAL-TIME CMOS CLOCK
l
REAL-TIME CMOS CLOCK CHIP WITH BATTERY
BACKUP
l
The clock chip contains battery backup and 64 (40H)
bytes of CMOS RAM, accessed through ports 70H
and 71H. (Newer versions contain 128 (80H) bytes.)
l
14 bytes (0-0DH) of the CMOS RAM are used by the
internal clock circuitry to keep track of time in BCD
format and as Status Registers.
l
The remaining bytes are used to store Configuration
Status information used by BIOS.
l
The clock chip can be used to generate an interrupt on
IRQ8, interrupt type 70H (no defined PC function) .
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 6
REAL-TIME CMOS CLOCK
40H bytes of CMOS RAM
BATTERY BACKED UP CMOS / RTC
"PC/AT" CONFIGURATION STORAGE
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 7
RTC Address
Map
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 8
RTC Address Map
00
00H
14 BYTES
0DH
13
14
50 BYTES
CONFIGURATION
REGISTERS
63
3FH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
SECONDS
SECONDS ALARM
MINUTES
MINUTES ALARM
HOURS
HOURS ALARM
DAY OF THE WEEK
DAY OF THE MONTH
MONTH
YEAR
REGISTER A
REGISTER B
REGISTER C
REGISTER D
BINARY
OR
BCD
INPUTS
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 9
RTC Address Map - Bytes 0-13t
FUNCTION
FUNCTION
Time, Calendar, and Alarm Bytes
Status Registers
Seconds register
Seconds alarm register
Minutes register
Minutes alarm register
Hours register
Hours alarm register
Day of week register
Date of month register
Month register
Year register
Status register A
Status register B
Status register C
Status register D
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 10
RTC Address Map - Bytes 14t-63t
FUNCTION
General Configuration Bytes
Diagnostic status byte
Shutdown status byte
Floppy drive type byte
Reserved
Fixed disk type byte
Reserved
Equipment byte
Low base mem byte
High base mem byte
Low exp mem byte
High exp mem byte
Drive C ext type byte
Drive D ext type byte
0EH
OFH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
FUNCTION
General Configuration Bytes
Reserved
Features installed byte
Misc Reserved
Product Dependent
CMOS CHECKSUM byte
LSB of extended mem
MSB of extended mem
Date century byte
Setup information byte
System speed byte
Misc Reserved
Misc Reserved
1BH--1EH
1FH
20H-27H
28H-2DH
2EH-2FH
30H
31H
32H
33H
34H
35H-3CH
3DH-3FH
NOTE: Use of some locations
varies with BIOS Vendor & BIOS
Version.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 11
Sample of “CMOS.DOC” from SPEED
INTEL PHASE III BIOS CMOS USAGE GUIDE
PRODUCT:
MORRISON MC (CH0_)
VERSION:
1.00.01.CH0
BYTE DESCRIPTION
10 Floppy Information
Bit 7-4 Floppy Drive A Type
Bit 3-0 Floppy Drive B Type
0000 = Not Installed
0001 = 360KB 5.25"
0010 = 1.2MB 5.25"
0011 = 720KB 3.5"
0100 = 1.44MB 3.5"
0101 = Reserved for Future Use
0110 = 2.88MB 3.5"
0111-1111 Reserved for Future Use
DEFAULTS
[BIOS] {MFG} CUST
[40]
{44}
0100y 0100y YES
0000y 0100y YES
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 12
Sample of “CMOS.DOC” from SPEED
DEFAULTS
[BIOS] {MFG} CUST
[POST] [POST]
BYTE DESCRIPTION
14
Equipment Byte
Bit
Bit
Bit
Bit
Bit
Bit
7-6 Number of Floppy Drives
5-4 Display Type
3 Display Installed
2 Keyboard Installed
1 Co-Processor Installed
0 Floppy Installed
POST
POST
POST
POST
POST
POST
POST
POST
POST
POST
POST
POST
NO
NO
NO
NO
NO
NO
15
Base Memory Low Byte/KB
[POST] {POST} NO
16
Base Memory High Byte/KB
[POST] {POST} NO
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 13
Sample of “CMOS.DOC” from SPEED
BYTE DESCRIPTION
2E Standard CMOS Checksum High Byte
2F Standard CMOS Checksum Low Byte
DEFAULTS
[BIOS] {MFG} CUST
[POST] {POST} NO
[POST] {POST} NO
7E Extended CMOS Checksum High Byte
7F Extended CMOS Checksum Low Byte
[POST] {POST} NO
[POST] {POST} NO
NOTE:
1. Extended CMOS (128Bytes) must be available for use.
2. The standard cmos checksum is on cmos registers from 10h to 2Dh.
Standard cmos checksum: 10+11+..+2C+2D => 2E(H), 2F(L)
3. The extended cmos checksum is on cmos registers from 48h to 7Dh.
Extended cmos checksum: 48+49+...+7D => 7E(H), 7F(L)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 14
ACCESSING
CMOS RAM
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 15
REAL-TIME CMOS CLOCK
l
The CMOS RAM is accessed in the following ways:
1. Writing the address of the desired byte to port 70H.
n
The address range is 0-3FH (0-63t).
3
2. Reading from or writing to the byte using port 71H.
n
l
Example: To access location 10H in CMOS RAM
Write the RAM Address (10H) to I/O Port 70.
n
Read/Write the RAM by performing an I/O Read/Write
to Port 71.
n
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 16
REAL-TIME CMOS CLOCK
BATTERY BACKED-UP CMOS / RTC
"AT" CONFIGURATION STORAGE
7 6 5 4 3 2 1 0
PORT 70: ADDRESS "POINTER"
7 6 5 4 3 2 1 0
PORT 71: DATA "SHOOTER"
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 17
Real Time Clock , CMOS Memory and Battery
Battery
IRQ8
OUT 70 (RTCALE#)
Port 70 Address
Port 71 Data
X-Bus 8 bits
A
D
D
R
CMOS
Memory
OUT 71 (RTCWR#)
D
A
T
A
IN 71 (RTCRD#)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 18
ACCESSING CMOS RAM
l
ITP COMMAND EXAMPLE (OFFSET 10H).
l
PORTS TO ADDRESS CMOS RAM
l
n
70H = ADDRESS PORT
n
71H = DATA PORT
READ
;READ OFFSET 10H
Port (70H) = 10H
n
Port (71H)
n
l
WRITE
;READ IT
;WRITE OFFSET 10H
Port (70H) = 10H
n
Port (71H) = 44H
n
;WRITE IT
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 19
ACCESSING CMOS RAM
l
ASSEMBLY LANGUAGE EXAMPLE (OFFSET 10H).
l
PORTS TO ADDRESS CMOS RAM
l
l
n
70H = ADDRESS PORT
n
71H = DATA PORT
READ
;READ OFFSET 10H
n
MOV
AL, RAM_ADDRESS
n
OUT
70H,AL
n
IN
AL,71H
;e.g. MOV AL, 10H
;READ IT
WRITE
;WRITE OFFSET 10H
n
MOV
AL, RAM_ADDRESS
n
OUT
70H,AL
n
MOV
AL, RAM_DATA
n
OUT
71H, AL
;e.g. MOV AL, 10H
;e.g. MOV AL, 44H
;WRITE IT
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 20
ACCESSING CMOS RAM
l
NOTES: Bit 7 of port 70H controls the enable and
disable of the NMI interrupts.
Take care to leave bit 7 unchanged when addressing the
clock chip.
n
You may notice that some BIOS accesses to the
Shutdown Byte at offset 0FH, use address 8FH.
n
3
8F in HEX => 1000 1111 in Binary
The MSB (Bit 7) is set to 1 to keep NMI Disabled.
n
3
(NMI is covered in detail in the Interrupt Section)
7 6 5 4 3 2 1 0
1 0
0 0
1 1
1 1
PORT 70: ADDRESS "POINTER"
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 21
8254
PROGRAMMABLE
INTERVAL TIMER
(PIT)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
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Ch 6 - Page 22
PC Compatible Timers
l
The PC/AT incorporates an 8254 PIT (Programmable
Interval Timer) which generates timing signals for use
on the System Board.
l
Frequency = 1/ time (1/period)
l
One clock period is usually measured on "like" clock
edges;
i.e.: Rising-Edge to Rising-Edge, or
n
Falling-Edge to Falling Edge.
n
Clock Period
t
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 23
8254 COUNTER / TIMER
14.318 MHz
÷12
Timer
Control
OUT/IN 43
ISA BUS
84OSC=
14.318 MHz
CLK
"1"
Counter 0
ENA
IRQ0
OUT/IN 40
(Time of Day Counter - 18.2 Hz)
Refresh
1.19MHz
CLK
"1"
Counter 1
ENA
OUT/IN 41
÷2
4
5
IN 61
CLK
Counter 2
0
1
ENA
Speaker Data
OUT/IN 42
OUT 61
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 24
THE 8254 PROGRAMMABLE INTERVAL TIMER (PIT)
l
The 8254 contains three functionally independent
counter/timers.
l
Each CT (Counter/Timer) consists of the following:
a 16-bit down-counter
n
a CLK input pin to trigger the down-counter
n
a GATE control input to gate the counting on/off
n
an OUT pin producing a square-wave or periodic pulse
(in PC/AT)
n
l
In the PC/AT, all three CLK inputs are tied to a 1.19
MHz input frequency.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 25
COUNTER/TIMER FUNCTIONS
l
The three Counter/Timers (CT0, CT1, CT2) are
initialized by BIOS to perform the following functions:
CT0--(TOD) interrupt.
n
3
Output is a square-wave with a 55 ms period.
CT1--A high output initiates a DRAM refresh cycle.
n
3
n
Output is a pulse with a 15.6 usec period.
CT2--Speaker Frequency
3
Generates Tone for Speaker (BEEP, BELL, etc)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 26
CONTROL WORD FORMAT (Port 43H)
D7
D6
D5
D4
D3
SC1 SC0 RW1 RW0 M2
D2
M1
D1
M0
D0
BCD
BCD
0
1
16 Bit Binary
BCD 4-Decades
Mode
0
0
X
X
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Mode 0 INT on TC
Mode 1 R-One Shot
Mode 2 Rate Gen.
Mode 3 Square Wave
Mode 4 S/W Strobe
Mode 5 H/W Strobe
Read / Write
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Latch Counter Value
Read/Write LSB ONLY
Read/Write MSB ONLY
Read/Write LSB then MSB
Select Counter
Counter 0 "Time-Of-Day" 55ms
Counter 1 "Refresh Timer" 15.6us
Counter 2 "Speaker Tone"
Read Back Specific Counter Value
CONTROL WORD FORMAT: A1.A0=11; CS*=0; RD*=1; WR*=0
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 27
8254 COUNTER #0 Time Of Day
1.19 MHz
Command Address
Data /8
Counter #0 (p/o 8254)
MSB
LSB
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
S/C R/W Mode BCD
TO IRQ0
TOD Interrupt
0 0 1 1 0110
55ms
+VCC
Write 36H to Port 43H
Write FFFFH to Port 40H
S/C=00=> Counter #0
FFFFH = 65,535t
Mode= 011y => Mode 3
(1/1.19Mhz) * 65,535 = 55ms
(Square Wave- Symmetric)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 28
COUNTER/TIMER FUNCTIONS
l
CT0--Time Of Day Interrupt.
3
GATE tied high, always counting.
3
Output is a square-wave with a 55 ms period (18.2 Hz).
3
Tied to 8259 PIC IRQ0. A rising-edge on the output causes
an INTERRUPT TYPE 8, the Time Of Day Interrupt.
3
Interrupt Service Routine for IRQ0 increments a dword
counter in BIOS Data Area at 40:6c.
» Maintains count of how many timer ticks have elapsed since
midnight.
» Can be set or read by BIOS INT 1AH in the PC/AT.
3
Interrupt Service Routine for IRQ0 also decrements byte at
40:40H in BIOS Data Area.
» If the count reaches zero, the Interrupt Service Routine issues
a command to shut off the disk drive motor if it is on.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 29
8254 COUNTER #1 REFRESH
1.19 MHz
Command Address
Data /8
Counter #1 (p/o 8254)
MSB
LSB
0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
S/C R/W Mode BCD
0 1 0 1 0100
+VCC
12H = 18t
TO REFRESH
CONTROLLER
15.6us
Write 54H to Port 43H
Write 12H to Port 41H
S/C=01=> Counter #1
12H = 18t
Mode= 010y => Mode 2
(1.19Mhz /18) => 15.6 usec
(Period Pulse - Asymmetric)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 30
COUNTER/TIMER FUNCTIONS
l
CT1--A high output initiates a DRAM refresh cycle.
GATE tied high, always counting.
n
Output is a period pulse (asymmetric) with a 15.6 usec
period to the Refresh Controller.
n
This Refresh Request signal triggers the DRAM Refresh
Logic to refresh (dummy read) another Row in DRAM
memory every 15.6 microseconds.
n
The output also toggles bit 4 in Port 61 (Port B)
n
3
A program can check this bit to see if Refresh is active.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 31
8254 COUNTER #2 SPEAKER
1.19 MHz
Command Address
Data /8
Counter #2 (p/o 8254)
MSB
LSB
0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1
S/C R/W Mode BCD
1 0 1 1 0110
TO
SPEAKER
PORT 61H
R R R R
Write 0B6H to Port 43H
Write 0533H to Port 42H
S/C=02=> Counter #2
0533H = 1331t
Mode= 011y => Mode 3
(1/1.19Mhz) * 1331 =>~897 Hz
(Square Wave- Symmetric)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 32
COUNTER/TIMER FUNCTIONS
l
CT2--Speaker Frequency
The output from CT2 passes through a Speaker Gate to
the speaker where the square-wave produces a tone.
n
Speaker Gate controlled by BIT0, PORT B (PORT 61H).
n
3
BIT1 = 0 , CT2 output disabled
3
BIT1 = 1 , CT2 output enabled, square-wave output.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 33
I/O Addr 61H Bit Assignments (Port B)
BIT/VALUE
FUNCTION
ACCESS
BIT 7
1 = ONBOARD PARITY ERROR
READ ONLY
BIT 6
1 = ISA PARITY ERROR
READ ONLY
BIT 5
1 = SPEAKER SIGNAL ON
READ ONLY
BIT 4
TOGGLES WITH EACH REFRESH.
READ ONLY
BIT 3
1 = ISA PARITY ERROR
DISABLED
READ / WRITE
BIT 2
1 = ONBOARD MEMORY
PARITY ERROR DISABLED
READ / WRITE
BIT 1
1 = SPEAKER DATA ON
READ / WRITE
BIT 0
1=SPEAKER ENABLED
READ / WRITE
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 34
COUNTER/TIMER FUNCTIONS
n
Optional Watchdog Timer (Fail-safe Timer)
3
Some systems also implement an additional Timer located
at I/O Port 44H.
3
An additional 8254 with only Counter #0 used.
3
This is Timer 3 in PS/2 & EISA systems.
3
The timer watches IRQ0, and if interrupt recognition has
been disabled for an extended period of time (NO IRQ0), an
NMI is generated.
3
The NMI Interrupt Service Routine checks to see if this was
caused by a Parity Error or Watchdog Timer and the
Operating System can take appropriate action.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 35
8254 COUNTER / TIMER REVIEW
14.318 MHz
÷12
Timer
Control
OUT/IN 43
ISA BUS
84OSC=
14.318 MHz
CLK
"1"
Counter 0
ENA
IRQ0
OUT/IN 40
(Time of Day Counter - 18.2 Hz)
Refresh (15.6 us)
1.19MHz
CLK
"1"
Counter 1
ENA
OUT/IN 41
÷2
4
5
IN 61
CLK
Counter 2
0
1
ENA
Speaker Data
OUT/IN 42
OUT 61
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 36
8742 Keyboard
Controller
Description
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 37
8742 KEYBOARD CONTROLLER
COLOR*
MGTEST
KEYLOCK
ROMBIOS
Translate Scan
Code to give
ASCII Character
(IRQ1 I.S.R).
Data Bus
8
KEYCLK
Buffer
KEYDAT
Buffer
8742
system
keyboard
u controller
IOWC*
IORC*
8742CS*
A2
RESET*
KBIRQ
DETURBO
KB-RESET
KB-A20GATE
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 38
8742 KEYBOARD CONTROLLER
l
The INTEL 8042 OR 8742 MICROCONTROLLER is a
functional microcomputer on a single chip that requires
only a 12 MHz clock input.
l
The Microcontroller contains:
A CPU Core with an instruction set of more than 90
instructions.
n
2K of ROM
n
256 byte of RAM
n
Two I/O Ports
n
An 8 bit bi-directional Data Bus to interface to a CPU.
n
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 39
8742 KEYBOARD CONTROLLER
l
The 8742 Keyboard Controller interfaces the Keyboard
to the PC System Board.
It converts the Serial Data SCAN CODES received from
the Keyboard & Mouse to 8-Bit parallel data and sends
them to the PC System Board.
n
3
Keyboard & Mouse use 2 independent Serial Interfaces.
It is the Interface for sending commands and receiving
status from the Keyboard.
n
It provides additional I/O Ports for miscellaneous
functions such as generating the Keyboard Interrupt &
and reading the KeyLock Status.
n
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 40
8742 KEYBOARD CONTROLLER
l
The Keyboard Controller communicates with the
Keyboard using a Serial Interface:
1 line for Key Clock
n
1 line for Key Data
n
l
The Keyboard Data is in a properly formatted 11 BIT
serial stream to/from another microcontroller in the
Keyboard.
Start (Logic 0), 8 Data, Parity (Odd), Stop (Logic 1).
n
l
NOTE: A detailed discussion of the communication
with the 8042 is beyond the scope of this course.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 41
8742
CONTROLLER
PORTS
PC Architecture For Technicians Level-1
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Technical Excellence Development Series
Ch 6 - Page 42
8742 CONTROLLER PORTS
KEYBOARD
CONTROLLER
OUT 64
Controller
Command
IN 64
Controller
Status
OUT 60
IN 60
8742 Cmd Data
& Keyboard Data
Keyboard Scan Codes
& Kybd Cmd Results
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 43
7 6 5 4 3 2 1 0
Input buffer full
Output buffer full
Self test flag
Keyboard unlocked
Last input: Cmd/Data
Receive time-out
Transmit time-out
20h:3Fh Read Cmd byte
60h:7Fh Write Cmd byte
AAh Self test
ABh Test interface
ACh NO-OP
ADh Disable keyboard
C0h Read input port
D0h Read output port
D1h Write output port
E0h Read test input port
E1h:EFh Reserved
F0h:FFh Output pulse
Parity error
8742 CONTROLLER PORTS
7 6 5 4 3 2 1 0
PORT 64 Write: Command Register
PORT 64 Read: Status Register
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 44
8742 CONTROLLER PORTS
l
The 8742 uses two ports in the PC/AT I/O space:
PORT 64H and PORT 60H.
PORT 64H is used as both a COMMAND Port (Writes)
and STATUS Port (Reads) for the 8742.
n
3
Reads from Port 64H provide the current state of the
keyboard controller.
3
Writes to Port 64H are interpreted as Commands by the
microcontroller and go to a write only Register in the 8042.
» Writes to Port 64H set the CMD/DATA Bit (Port 64 BIT 3) to 1.
3
Examples of common commands:
» AAH - Self Test: 55 is placed in the Output Buffer (Port 60) if
PASS.
» D1H - Writes the next byte sent to Port 60 to the Local Output
Port.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 45
8742 CONTROLLER PORTS (cont.)
l
PORT 60H is the data port and is used for:
Reading the Keyboard Scan Code information
n
3
Should only be read from after status port bit 0 (OBF) = 1
3
Normally read by the IRQ1 Interrupt Service Routine.
Sending Data & Commands to the Keyboard.
n
3
Writes to Port 60H set the CMD/DATA Bit (Port 64H BIT 3)
to 0 & pass the Data through the keyboard controller to the
Keyboard
» Unless the 8742 is expecting a Data Byte following a command
to Port 64H.
Cont. next page
n
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 46
8742 CONTROLLER PORTS (cont.)
l
PORT 60H is the data port and is used for:(Cont.)
Reading & Writing the the Local Ports.
n
Write: After sending the appropriate command to Port
64 (e.g. D1H), the 8742 transfers the next byte written
to Port 60 to the Local Port.
»Should only be written to if status port bit 1(IBF) = 0
3
Read: After sending the appropriate command to Port
64 (e.g. COH, DOH), the 8742 transfers the contents of
the Local Port to the Input Buffer which can be read at
Port 60.
»Should only be read from after status port bit 0
(OBF) = 1
3
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 47
KEYBOARD
CONTROLLER
Status REG
Port 64 READ
Local Port 1
8742 KEYBOARD CONTROLLER
8
Output Data BFR
Port 60 READ
12 MHZ
XTAL
Local Port 2
Input Data BFR
Port 60/64 Write
Test Port
Kybd Data In
Mse Data In
Passwd En
MFG Test
Color/Mono
Kybd Lock
Hot Reset
A20 Gate
Kybd IRQ
Kybd Clock Out
Kybd Data Out
Kybd Clock In
Mse Clock In
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 48
8742 KEYBOARD CONTROLLER
l
The 8042 microcontroller contains two extra I/O Ports.
One Input Port (Local Port 1):
n
3
Gets Kybd Data From Kybd, Reads KeyLock Status, etc.
3
Read at Port 60 by first sending the “Read Input Port” (C0H)
Command to Port 64.
One Output Port (Local Port 2).
n
3
Sends Keyboard Data From 8742 to Keyboard
3
Generates IRQ1, A20 Gate, Hot Reset, etc
3
Data written at Port 60 after first sending the “Write Output
Port” (D1H) Command to Port 64.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 49
MISC. KYBD
CONTROLLER
SIGNALS
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 50
MISC. KYBD CONTROLLER SIGNALS
KBD IRQ:
l
Generated when the Keyboard sends a scan code to
the 8742 Keyboard Controller.
l
When the 8742 receives a data byte from the
keyboard, the 8742 ROM code:
Places the data byte in it’s Output Buffer (Port 60).
n
Sets the Output Buffer Full flag
n
3
A Read of Port 64 Bit 0 will see a 1.
3
The OBF Flag is Reset when Data is read from Port 60.
Cont. next page
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 51
MISC. KYBD CONTROLLER SIGNALS
l
KBD IRQ: When the 8742 receives a data byte from
the keyboard, the 8742 ROM code: (Cont.):
Automatically generates an Interrupt to the PC System
Board (tied to PIC IRQ1).
n
3
Generates IRQ by setting Bit 4 of Local Port 2 (KBD IRQ)
3
The IRQ1 Interrupt Service Routine reads keyboard
controller data port to get key pressed.
» The data read is stored in the 16 word Keyboard Circular
Buffer in BIOS DATA Area.
» Both a Scan Code & ASCII Code are stored at one of the 16
locations starting at 40:1E.
» BIOS INT 16 can access the “Key Pressed” from the BIOS
DATA Area.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 52
MISC. KYBD CONTROLLER SIGNALS
l
A20 Gate:
Inhibits Generation of the A20 Address Line in Real
Mode making the 80286 and higher processors
compatible with the 8088.
n
The 8088 only had A19:0 and could not assert A20.
n
3
8088 code that generated an address above 1 MB wrapped
around to low memory.
Also know as A20MASK, PASSA20, FORCEA20, etc
n
Can be controlled by Software:
n
3
HIMEM.SYS, WINA20.386, etc.
A “FAST A20” is often implemented in chipsets.
n
3
PS/2 Port “A” (Port 92) or Port 78 (Not PC/AT Compatible)
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 53
MISC. KYBD CONTROLLER SIGNALS
l
Hot Reset: Causes a CPU only reset (System Board
not reset).
Originally used to change the 80286 from Protected
Mode to Real Mode.
n
Generated when “CTL-ALT-DEL” keys are depressed.
n
3
Also know as Warm Boot, Soft Reset
Can be generated by writing “FEH” to Port 64.
n
l
Turbo/Deturbo:
Deturbo slows down the System and emulates the 8
MHz PC/AT.
n
l
MFG TEST: Used to enable special test functions in
the manufacturing process (Optional Use).
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 54
Keyboard Controller Review
RESET#
12Mhz Clock
Num
Lock
CE#
ROMBIOS
WR#
RD#
1
8042
Keyboard
Translate Scan
Code to give
ASCII Character
(IRQ1 I.S.R).
Kbd Clock
Caps
Lock
1
2
3
4
5
Q
W
E
R
T
Etc.
2
Kbd Data
Etc.
Controller
Keyboard Switch Matrix
produces SCAN CODE
X-Bus
8 Bit
IRQ1
KEYLOCK#
COLOR#
Misc.
InputsOutputs
A20GATE#
KBDRST# (To CPU INIT Pin)
NOTE: Port A is PS/2 Port 92
Fast A20 - Port A BIT 1
Fast Hot Reset - Port A BIT 0
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 55
SUMMARY
WE HAVE DISCUSSED THE FOLLOWING:
l
The Real-Time CMOS Clock Chip description.
l
The CMOS Address Map.
l
Accessing the CMOS RAM.
l
The 8254 Programmable Interval Timer description.
l
The functions of the three Counter/Timers.
l
The 8742 Keyboard Controller description.
l
The functions of the Keyboard Controller.
l
The I/O Ports associated with the 8742.
l
The Misc. Keyboard Controller Signals.
PC Architecture For Technicians Level-1
Rev. 1.0 Sys MFG T/ED 4/25/2003
Technical Excellence Development Series
Ch 6 - Page 56