FYSE420 DIGITAL ELECTRONICS
Lecture2
1
[1] DIGITAL LOGIC
CIRCUIT ANALYSIS
& DESIGN
Nelson, Nagle, Irvin, Carrol
ISBN 0-13-463894-8
[2] DIGITAL DESIGN
Morris Mano
Fourth edition
ISBN 0-13-198924-3
[3] Digital Design
Principles and Practices
Fourth edition
Wakerly John F.
ISBN 0-13-186389-4
2
Asynchronous Sequential Logic
The design of an asynchronous sequential circuits
Design specification
Primitive state diagram
Primitive flow table
Reduced flow table
Minimized number of states
Reduced state diagram
Transition table
Boolean functions of all exitation variables Yi
Or exitation functions of unclocked FF (SR latch)
Circuit diagram
3
©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
Latch has two inputs : S , R
one output : Q
Sn Rn
0 0
1 0
0 1
1 1
Qn+1
Qn
1
0
--
Function table
Output state depends on previous
output
No state transition when input SR=00
Latch goes to the state a when SR=01
Latch goes to the state b when SR=10
Primitive flow table
Reduced flow table
SR=11 input state is forbidden
Reduced state diagram
4
©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
Primitive flow table
SR
state
SR
C00
D00
A01
01
10
B10
11
11
Q
0 stable state C after state A
1 stable state D after state B
0 stable state A
1 -----0 -----1 stable state B
0 -----1 ------
a
b
00
01
11
10
A
C,-
A,0
-,-
-,-
B
D,-
-,-
-,-
B,1
C
C,0
A,-
-,-
B,-
D
D,1
A,-
-,-
B,-
STATE,Q
Reduced flow table
SR
00
01
a
a,0
a,0
b,-
b
b,-
a,-
b,1
state
11
10
STATE
5
©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
State diagram
SR
state
a
b
00
01
a,0
a,0
b,-
11
10
a,-
b,1
STATE
Circuit has two states a and b
SR=00
SR=00
b,-
SR=10
a,0
b,1
SR=01
SR=01
SR=10
ONE internal state variable
Secondary variable : y1
Exitation variable : Y1
The state of the output Q is state of the Y
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©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
Q=0 on the state a
Q=1 on the state b
Assign binary values to the states : a=0 , b=1
SR=00
SR=00
SR=10
a, 0
b, 1
SR=01
SR=01
Transition table
Flow table
SR=10
State diagram
SR
00
01
a
a
a
b
b
b
a
b
state
11
10
STATE
7
©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
SR
SR
00
state
a
11
a
a
b
01
b
10
0
b
a
1
b
0
1
01
11
10
0
d
1
d
0
Transition table
STATE
Flow table
00
y1
1
Y1
Undetermined state : we can use -1- during
minimization procedure.
Boolean function for the exitation variable
SR
00
01
11
10
0
0
0
1
1
1
1
0
1
1
y1
Y1 = S + y1 R
Y1
K-map
8
©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
S
Q
R
9
©Loberg
Asynchronous Sequential Logic
The design of an asynchronous sequential circuits
Design example3 :
SR latch (unclocked FF)
Simulation Circuit
S
Q
R
SR latch (unclocked FF)
Delay for generation of reset input R
10
©Loberg
Asynchronous Sequential Logic
Design example3 :
SR latch (unclocked FF)
The design of an asynchronous sequential circuits
Set SR=10
Reset SR=01
Set SR=10
S
R
Q
Simulated output sequence
Forbidden input 11
See transition table : Q=1 when SR=11
11
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
Circuit has two inputs x1 and x2
Circuit has one output Z
x1
x2
Z is -1- when x1 = x2 = -1- and x2 goes high before x1 .
Z
When Z=1 it goes to -0- only when x1 goes -0-
00/0
x1x2=00
x1x2=11
f,0
01/0
x1x2=01
x1x2=01
a,0
x1x2=00
x1x2=01
x1x2=10
x1x2=11
01/0
a
00/0
b,0
x1x2=00
11/0
x1x2=01
b
00/0
f
x1x2=11
x1x2=10
11/0
01/0
10/0
11/1
01/0
00/0
x1x2=00
x1x2=10
c,1
x1x2=11
c
10/0
e
e,0
11/1
10/1
11/1
x1x2=10
d,1
x1x2=10
x1x2=11
10/0
d
10/1
12
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
00/0
x1x2
01/0
11/0
00/0
f
11/0
b
00/0
01/0
10/0
11/1
01/0
00/0
c
10/0
11/1
10/1
e
00
01
11
10
a
a,0
b,0
-,-
e,0
b
a,0
b,0
c,1
-,-
c
-,-
b,0
c,1
d,1
d
a,0
-,-
c,1
d,1
e
a,0
-,-
f,0
e,0
f
-,-
b,0
f,0
e,0
state s
01/0
a
11/1
10/0
d
10/1
S,Z
Primitive flow table
13
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
x1x2
00
01
11
10
a
a,0
b,0
-,-
e,0
b
a,0
b,0
c,1
-,-
c
-,-
b,0
c,1
d,1
d
a,0
-,-
c,1
d,1
e
a,0
-,-
f,0
e,0
f
-,-
b,0
f,0
e,0
state s
S,Z
Primitive flow table
Two states l and k
One state variable y
x1x2
00
s
a,e,f
a,0
01
11
10
b,0
f,0
e,0
b,c,d
b,0
c,1
d,1
a,0
S,Z
x1x2
00
01
11
10
k
k,0
l,0
k,0
k,0
l
k,0
l,0
l,1
l,1
s
S,Z
Reduced flow table
On state k : y = 0
On state l : y = 1
14
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
On state k : y = 0
On state l : y = 1
Reduced flow table
Combined transition and output table
x1x2
00
01
11
10
k
k,0
l,0
k,0
k,0
l
k,0
l,0
l,1
l,1
s
x1x2
00
01
11
10
0
0,0
1,0
0,0
0,0
1
0,0
1,0
1,1
1,1
y
S,Z
Y,Z
x1x2
00
01
11
10
0
0
1
0
0
1
0
1
1
1
y
Implementation without
SR latch
Implementation with
SR latch
Y
Transition table
15
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
Implementation with SR latch
x1
x2
y
fS
S Q
fR
R Q
Y
This feedback may be not used
16
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
Implementation with SR latch
Exitation table of SR-latch
Transition table
q
0
0
1
1
Q
0
1
0
1
SR
q 00
SR
0X
10
01
X0
01 11
0
0
-
1
1
1
0
-
1
Q
x1x2
x1x2
01
11
10
0
0
1
0
0
1
0
1
1
1
y
10
0
Function table of SR-latch
00
Exitation functions fS and fR
00
01
11
10
0
0,X
1,0
0,X
0,X
1
0,1
X,0
X,0
X,0
y
Y
S,R
Map for exitation functions fS and fR
Transition table
17
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
Implementation with SR latch
x1x2
00
01
11
10
0
0,X
1,0
0,X
0,X
1
0,1
X,0
X,0
X,0
y
S,R
Map for exitation functions fS and fR
x1x2
y
x1x2
00
01 11
10
0
0
1
0
0
1
0
X
X
X
S=R=1
00
y
Note!
x1x2 is forbidden
S
01 11
10
0
X
0
X
X
1
1
0
0
0
R
K-map for input S
K-map for input R
S = x1 x2
R = x1 x2
18
©Loberg
Asynchronous Sequential Logic
Design example4
The design of an asynchronous sequential circuits
Implementation with SR latch
x1x2
x1x2
00
01
11
10
0
0,0
1,0
0,0
0,0
1
0,0
1,0
1,1
1,1
y
00
y
01 11
10
0
0
0
0
0
1
0
0
1
1
Y,Z
Z
Combined transition and output table
K-map for output Z
Z = yx1
Z
x1
x2
S = x1 x2
R = x1 x2
Z = yx1
S Q
R Q
19
©Loberg
Asynchronous Sequential Logic
Race Condition
The design of an asynchronous sequential circuits
Two or more binary state variables (yi) change value in
response to a change in an input variable (x)
[1] p. 660
Race Condition
01
00
11
10
Depends on delays
20
©Loberg
Asynchronous Sequential Logic
Race Condition
The design of an asynchronous sequential circuits
Noncritical race
y1
y2
Same final stable state
Present stable state
y1
y2
For proper operation critical races must be avoided
Critical race
y1
Different final stable state
y2
Present stable state
y1
y2
Different final stable state
21
©Loberg
Asynchronous Sequential Logic
Race Condition
The design of an asynchronous sequential circuits
Examples of noncritical race
Initial total stable state y1y2x = 000
y1y2
x
0
1
00 00
11
01
11
11
11
10
11
x:
Transition table A
Final total stable
state y1y2x = 111
Y1Y2
0
y1y2
1
Transition table B
Final total stable
state y1y2x = 011
(00
(00
11)
00
01
11
00
10
11
Possible transitions
x
0
1
00 00
11
01
01
11
01
10
11
Y1Y2
11
00
01
00
10
01)
11
01
22
©Loberg
Asynchronous Sequential Logic
Race Condition
The design of an asynchronous sequential circuits
Examples of critical race
Initial total stable state y1y2x = 000
x
y1y2
x:
0
1
00 00
11
01
01
11
11
10
10
0
1
Transition table C
y1y2
0
1
00 00
11
01
11
11
11
10
10
Transition table D
Final total stable
state y1y2x = (111),
011 or 101
Final total stable
state y1y2x = 111,
101
x
Y1Y2
(00
00
11)
01
00
10
Y1Y2
11)
01
(00
00
00
Possible transitions
11
10
23
©Loberg
Asynchronous Sequential Logic
Race Condition
The design of an asynchronous sequential circuits
Races may be avoided by making a proper binary assignment to the state variables.
Only one state variable can change at any one time when
a state transition occurs in the flow table.
y1y2
x
0
1
00 00
01
01
11
11
10
10
10
Initial total stable
state y1y2x = 000
x:
Modified
transition table C
01
11
10
1
Modified
transition table D
x
0
1
00 00
01
01
11
11
11
10
10
Final total stable
state y1y2x = 111
Final total stable
state y1y2x = 101
Y1Y2
00
0
y1y2
Cycle
Y1Y2
00
01
11
24
©Loberg
Asynchronous Sequential Logic
Race Condition
The design of an asynchronous sequential circuits
If a cycle does not terminate with a stable state, circuit will be unstable.
y1y2
x
0
1
00 00
01
01
11
11
10
10
01
Y1Y2
01
11
10
Example transition table
25
©Loberg
The End
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