Tutorial:
Flexible Clock: the Driving Force for Innovation in Future Electronic System Design
By: Liming Xiu
Clock signal is omnipresent in electronic system. It is the timekeeper and driver of everything inside a chip. Clock technology is one of the four
fundamental technologies (along with processor technology, memory technology and analog/RF technology) in the field of IC design. No circuit
designer, analog or digital, logical frontend or physical backend, can address any design issue without having clock signal included in the
consideration. In the field of clock signal study, there are three focuses: clock generation, clock distribution and clock usage (setup/hold check).
Within clock generation, there are two major concerns: high frequency and low noise. In the past several decades since clock was introduced into
circuit design, clock circuit researcher and designer have spent tremendous effort in pursuing the clock generator of highest frequency and lowest
phase noise/jitter. The resulting clock signal has played an important role in electronic systems. However, such clock signal is rigorous (or rigid). In
other words, for a particular design, the choice of clock frequency is limited and the switching of clock frequency is slow. On the other hand, from a
clock user’s (system designer, chip architect) perspective, the two features of arbitrary frequency generation and instantaneous frequency switching
are always preferred. Therefore, ample supply of frequency and fast frequency switching are the two emerging focuses of clock study. A clock
generator of such capability, which is termed flexible clock, is more demanded in future systems that targets at IoT, sensor network and big data
environment since these applications demands low power, low cost, miniature in size, data flow rates of a large variety and etc. In this tutorial, the
Time-Average- Frequency concept and theory that is the foundation for creating flexible clock will be first explained. The circuit architecture for
building a flexible clock generator will then be reviewed. Its impact, the route from component-level enabler to system level innovations, will be
illustrated through real application examples.
Keywords— Clock, frequency synthesis, phase-locked loop, time-average-frequency, flying-adder PLL.
Speaker’s Biography:
Liming Xiu earned his B.S. and M.S. degrees in physics from Tsinghua University, Beijing, China, in 1986 and 1988, respectively. Mr. Xiu earned
his second M.S. degree in electrical engineering from Texas A&M University, College Station, TX, USA, in 1995. In 1990-1993, he was a research
scientist of University of Houston, TX, USA. In 1995-2009, he worked for Texas Instruments Inc., Dallas, TX, USA (Senior Member Technical Staff).
In 2009- 2012, he was chief clock architect of Novatek Microelectronics Corp., Hsinchu, Taiwan. From 2012-2015, he was vice president of Kairos
Microsystems Inc, Dallas, TX. He will join Beijing Oriental Electronics Technology Group Company (BOE), Beijing, China. He has 20 granted and 8
pending US patents and has published numerous IEEE journal papers and three books: VLSI Circuit Design Methodology Demystified (Wiley-IEEE
Press), Nanometer Frequency Synthesis beyond Phase-Locked Loop (Wiley-IEEE Press, IEEE Press Series on Microelectronic Systems) and From
Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic system (Wiley-IEEE Press, IEEE Press Series on
Microelectronic Systems). He is also an invited author of a chapter in book “Mixed-Signal Circuits”. He is the inventor of Flying-Adder frequency
synthesis architecture (Flying-Adder PLL); the promoter of Time- Average-Frequency concept and theory. He served as vice president of IEEE
Circuit and Systems Society in years 2009 and 2010.