Computer Engineering Division
MS and PhD Programs
Computer Engineering Faculty by Area
Architecture
Annavaram, Murali
Dubois, Michel (Director, Computer Engineering
Hwang, Kai
Pinkston, Timothy (Vice Dean)
Prasanna, Viktor
Networks
Jain, Rahul
Krishnamachari, Bhaskar
Psounis, Konstantinos
Raghavendra, Cauligi (Vice Dean)
Silvester, John
VLSI/CAD
Beerel, Peter
Bogdan, Paul
Breuer, Melvin
Gupta, Sandeep (Department Head)
Parker, Alice
Pedram, Massoud
Teaching Eshaghian‐Winer, Mary
Nazarian, Shahin
Puvvada, Gandhi
Redekopp, Mark
Ung, Monte
Research Cho, Young
Draper, Jeff
Granacki, John
Simmhan, Yogesh
Who is a Computer Engineering student?
If most of the courses you are interested in appear in this list
Computer Architecture: EE 454L ‐ Introduction to System Design Using Microprocessors
EE 457 ‐ Computer Systems Organization
EE 532 ‐ Wireless Internet and Pervasive Computing
EE 557 ‐ Computer Systems Architecture
EE 653 ‐ Advanced Topics in Microarchitecture
EE 657 ‐ Parallel Processing
EE 659 ‐ Interconnection Networks
EE 677 ‐ VLSI Architectures and Algorithms
Computer Networks: EE 450 ‐ Introduction to Computer Networks
EE503‐ Probability for Electrical and Computer Engineers
EE 550 ‐ Design and Analysis of Computer Comm. Networks
EE 555 ‐ Broadband Network Architectures
EE 579 ‐ Wireless and Mobile Networks Design and Laboratory
EE 650 ‐ Advanced Topics in Computer Networks
EE 652 ‐ Wireless Sensor Networks
If most of the courses you are interested in appear in this list
CAD/VLSI: EE 477 – MOS‐VLSI Circuit Design
EE 536a&b – Mixed‐Signal Integrated Circuit design
EE 577a&b – VLSI Systems
EE 658 – Diagnosis and design of Reliable Digital Systems
EE552 – Asynchronous VLSI Design
EE 581 – Mathematical Foundations for Computer Aided Design
EE 681 – Computer Aided Design of Digital Systems
EE 677 ‐ VLSI Architectures and Algorithms
If you are enrolled in the following degree
programs with primary interest in …
Degree Primary area of interest
Architecture Networks
VLSI or CAD
MSEE x
x
x
MSCENG x
x
x
MSEECN x
MSEEVL x
PhDEE x
x
x
PhDCENG
x
x
x
An overview of degree programs
MSEE
A general degree which spans all areas in EE
MSEECN
A version of MSEE, specialized for Networks
MSEEVL A version of MSEE, specialized for VLSI or CAD
MSCENG
A degree for breadth across CEng and depth in one of its areas
PhDEE A doctoral degree which spans all areas in EE
PhDCENG A doctoral degree for those desiring a rigorous CEng program
MSEE - Master of Science in Electrical Engineering
A minimum cumulative grade point average (GPA) of 3.0 must be earned on all course work.
A minimum of 27 units of course work (400 level and above).
At least 18 units in EE.
At least 18 units at the 500 level or above
At least 21 units in the School of Engineering
No more than 3 (three) 400 Level courses may be counted towards the degree.
No more than 3 courses taken outside of the EE Department may be counted towards the degree. (Units taken outside of Electrical Engineering must be approved in advance and must be substantive in content and related to the degree objective.)
MSEE - Master of Science in Electrical Engineering
MSEE w/ Thesis Option
A minimum of 27 units of course work (400 level and above).
At least 16 units, not including thesis, must be at the 500 level or
above.
At least 18 units must be completed in EE.
At least 4 and not more than 8 units of research (590) and thesis
(594ab).
The minimum thesis requirement in 594a is two units; in 594b, two
units.
MSCENG - Master of Science in Computer Engineering
A minimum cumulative grade point average (GPA) of 3.0 must be earned on all course
work.
A minimum of 27 units of course work.
A minimum of 18 units must be taken in Electrical Engineering
ENTRANCE REQUIREMENT COURSES
CSCI 455 Introduction to Programming Systems Design
EE 357 Basic Organization of Computer Systems
FUNDAMENTAL COURSES
CSCI 402x Operating Systems
EE 450 Introduction to Computer Networks or EE 503 Probability for EE and Ceng
EE 457x Computer Systems Organization
EE 477 MOS VLSI Circuit Design
A Fundamental Course may be waived taking a Placement Exam. In case a Placement Exam is not offered, then a fundamental course may be waived by a designated faculty member.
MSCENG - Master of Science in Computer Engineering
CORE COURSES
EE 550 Design and Analysis of Computer Communication Networks or
EE 555 Broadband Network Architectures
EE 557 Computer Systems Architecture
EE 577a VLSI System Design
ELECTIVE COURSES
Students must take at least 6 units from the following list of elective courses
(cannot overlap with core courses):
Computer Science: CSCI 545, CSCI 546, CSCI 547, CSCI 551, CSCI 555, CSCI
558L, CSCI 561, CSCI 565, CSCI 570, CSCI 584, CSCI 585, CSCI 595
Electrical Engineering: EE 532, EE 536ab, EE 549, EE 550, EE 552, EE 554, EE 555, EE 557, EE 558, EE 560, EE 577ab, EE 579, EE 650, EE 652, EE 653, EE 657, EE 658, EE 659, EE 677, EE 680, EE 681
MSCENG - Master of Science in Computer Engineering
Thesis Option
The minimum requirement is 27 units; four of these units are to be thesis. At least 16 units, not including thesis, must be at the 500 level or higher,
and at least 18 units must be in the major department. A total of not less
than four nor more than eight units of 590 Research and 594ab Thesis must
be included in the program. The minimum thesis requirement in 594a is
two units; in 594b, two units.
MSEECN - Master of Science in Electrical Engineering
(Computer Networks)
Students are required to have a BS degree in Electrical Engineering, Computer Engineering, or Computer Science.
A minimum cumulative grade point average (GPA) of 3.0 must be earned on all course work.
A minimum of 27 units, including:
21 units in the School of Engineering
18 units at the 500 level
15 units in Electrical Engineering (cross‐listed courses are acceptable)
The following required courses: EE 549 or EE 550, EE 555 and CSCI 551.
It is expected that each student in this program will take or have taken the equivalent of the following fundamental courses:
FUNDAMENTAL COURSES
CSCI 402x
EE 450
EE 457Lx
EE 503
Students who have previously taken equivalent courses elsewhere should obtain a waiver by passing the placement exam at USC, as this will allow additional electives to be taken.
MSEECN - Master of Science in Electrical Engineering
(Computer Networks)
REQUIRED COURSES
CSCI 551
EE 549 or EE 550
EE 555
ELECTIVE COURSES
CSCI 530, CSCI 555, CSCI 558L, CSCI 570, CSCI 694ab, EE 532, EE 535, EE 554, EE 557, EE 558, EE 579, EE 590, EE 650, EE 652, EE 659. Any other course must be approved by a faculty advisor. Total units required for the degree is 27.
Thesis Option
The minimum requirement is 27 units; four of these units are to be thesis. At least 16
units, not including thesis, must be at the 500 level or higher, and at least 18 units must
be in the major department. A total of not less than four nor more than eight units of
590 Research and 594ab Thesis must be included in the program. The minimum thesis
requirement in 594a is two units; in 594b, two units.
MSEEVL - Master of Science in Electrical Engineering
(VLSI DESIGN)
A minimum cumulative grade point average (GPA) of 3.0 must be earned on
all course work.
Completing the normal requirements for the Master of Science in Electrical
Engineering, with the following additional required courses:
EE 536a; EE 577a; EE 577b or EE 536b; and EE 552.
If a student chooses to take EE 536b as well as EE 577b, the student may
either count EE 536b as one of the courses for Area 2 or EE 577b as one of
the courses for Area 1 or Area 3. (described below).
The student must also take two courses from one of the following areas and
one course from a second area:
Area 1: CSCI 455x, EE 560, EE 577b (see above), EE 658, EE 680 and EE 681.
Area 2: EE 448, EE 504L, EE 536b (see above), and EE 537. Area 3: CSCI 455x, CSCI 570, EE 557, EE 577b (see above), EE 659, EE 677.
MSEEVL - Master of Science in Electrical Engineering
(VLSI DESIGN)
Thesis Option
The minimum requirement is 27 units; four of these units are to be thesis.
At least 16 units, not including thesis, must be at the 500 level or higher,
and at least 18 units must be in the major department. A total of not less
than four nor more than eight units of 590 Research and 594ab Thesis must
be included in the program. The minimum thesis requirement in 594a is
two units; in 594b, two units.
PhD Programs: PhDEE and PhDCENG
GPA requirements: For taking screening exams and graduation.
Coursework: Required units with constraints on level and non‐departmental;
also a minor is required.
PhDCENG has more specific requirements
Research: Significant body or original research, under the supervision of
an advisor and a committee. Typically published as papers and as a
Doctoral Dissertation.
Exams:
Screening exams
Qualifying exam – dissertation proposal
Defense – dissertation defense
Residency requirements: Please see http://ee.usc.edu/academics/grad_degree_programs_phd/
and meet with your advisor.
Suggested priority for selecting courses
MS students
• First priority: 400‐level pre‐requisites to the 500‐level courses of your interest
‐Either enroll in, or pass the placement tests for
• Second priority: Core/required 500‐level courses of your area/program of interest
• Third priority: A coherent set of electives (see “flowcharts”)
PhD students
• Also focus on PhD Screening Exam (see advisor)
Placement tests
•
Who: If you have previously taken elsewhere a course that is nearly identical to a 400‐level USC course of your interest
•
Why: If you pass the test for a 400‐level course, then you
‐Do not have to enroll in that 400‐level course, and
‐Can enroll in any 500‐level course for which this course is a prerequisite
•
When: Friday, August 23, 2013, see
http://ee.usc.edu/students/graduate/academic‐dvisement/placement_exam_req.htm
Questions?
VLSI/CAD
Asynchronous VLSI
Peter A. Beerel • Asynchronous ASIC Flow
– Re-use standard tools for
synthesis/physical
Synthesis
– ClockFree – new asynchronous
optimization/ translation
– Target ultra high performance/
low-power
ClockFree
• CAD for Asynchronous Design
– Mathematical programming, graph
theory, Petri-nets
Physical Design
– Optimize pipeline structure - Slack
matching
Commercialized
– Optimize communication - restructuring
conditional communication
Async ASIC Flow
• Async Template and Library Design
– Advanced pipeline templates
– Static timing and noise analysis
• Application Drivers
– Turbo/Fano decoding
– Computational blocks
• Beyond Moore’s Law
– Robustness/reliability to process and
STFB 0.25um Test Chip
environment variability/faults
High-Level
Specification
CAST Definition
Clustering
pipeline stages
Place and route tool
Frequency @ 1.24GHz
Resilient and Specialized Computing
Jeff Draper
Resilient Computing
• Two trends coupled together greatly exacerbate system
reliability issues
• Extensive variability in device parameters at extreme
fabrication technology nodes
• Extreme-scale systems containing millions of cores
• Solutions needed at all levels: software, architecture, circuits
Resilient SRAM chips
Specialized Computing
• End of Moore’s Law will require value added in other ways for
computing to keep progressing
• Customized computer architectures are likely
• e.g., D.E. Shaw’s Anton molecular dynamics computer
8Mb SRAM
SRAM
SRAM
Node Processing Logic, Pbuf
Node Processing Logic,
SDRAM Interface, PiRC
Pbuf, DDR SDRAM
Interface, PiRC
Research Plan
• Currently exploring energy-resilience trade-offs, memory-oriented
computing, transactional memories, 3DIC-inspired architectures,
and networks-on-chips as part of solution space
Memory‐oriented computing chips
Design of Energy-Efficient Information Processing Systems
Massoud Pedram
Energy Efficiency and Our Digital Future
•
•
•
•
•
•
Moore’s law continues although it is increasingly more costly to stay on path (higher variability, lower supply voltages, less timing margins)
There is a move away from overclocking and performance‐driven design toward use of adaptive voltage supply levels, including near/sub‐threshold computing
Key figure of merit is the amount of useful work done per joule of energy dissipated in circuits (gigaflops/joule, MIPS/Watt, energy‐delay product)
Cost‐sensitive, heterogeneous, distributed computing platforms have emerged, operating under diverse requirements and targeting different markets
Future system architectures will be heterogeneous multi‐core designs, with integrated accelerator “sub‐
cores” connected via heterogeneous interconnect elements
Adaptability will also be a key requirement since it enables a system to provision and customize hardware to meet varying workload and performance requirements
Example Solutions
Cross‐layer Power Optimization Opportunities
Yield per Area Enhancement via Redundancy
The problem
Melvin A. Breuer
The yield of present (and future) technology nodes is (and will be) low. It starts
at about zero and during a learning period of several years gets to 85%. If
when the yield is at 35% we could, by re-design, enhance it to be 50% then
time to market can be drastically reduced. This can be achieved via
redundancy.
The solution
By duplicating of even triplicating non-memory modules on a die we increase
its area and to a greater extent its yield. Thus the wafer has less die but more
good ones and hence larger yield/area.
Findings
• We have developed several algorithms for identifying the optimal number
of spares per module.
• We have developed a system to partition a design in an optimal way to
form modules that will be replicated.
• We conjecture that replicating modules at the core level is not optimal;
such replication should be done at a finer level of granularity.
CYBER-PHYSICAL SYSTEMS GROUP
Paul Bogdan
Addressing challenges in medicine via bioinspired approaches
Detection of silent disease progression
Drug delivery to inaccessible body areas
Accurate modeling & steady interaction with
medical experts improves healthcare
Observation
Sensors
Output circuitry
Actuation
Steady interaction
with medical experts
Model
Parameter
Identification
Optimal Control
Algorithm
Computation,
Communication &
Control
The BioRC Biomimetic Real‐Time Cortex
Alice C. Parker
Spike
Analog Neuromorphic Circuits
Synapses with Plasticity*
Spiking Axon Hillocks Dendritic
Dendritic Computations branch
Stochastic Neurons*
Small Networks of Neurons
Structural Plasticity*
Retinal Circuits*
Neural-Astrocyte Interaction
Nanotechnology Implementations
Carbon Nanotube Synapse
Software Simulations
Retina*
Multi-Core Brain simulations
Bioinspired Algorithms
Stereo (binocular) vision*
No Spike
Both spatially- and temporally-clustered
inputs in our prototype dendritic branch
are required to initiate spikes
*Dissertation completed
Structural plasticity using synapse
Claiming by N2 as N1 lacks activity
27
Exploiting redundancy to maximize utility‐per‐wafer
•
•
Sandeep Gupta
Increasing percentage of fabricated chips imperfect due to increasing defect rates
Identify new types of redundancy to exploit
– Functional and control modules in modern high‐performance multi‐core processors (CPUs)
– Symmetry in modern highly‐parallel processors, e.g., GPUs, GP‐GPUs
– Flexibility in user needs – binning based on performance delivered by a chip to the user
•
Optimally exploit old and new redundancy to improve utility‐per‐wafer for CPUs
–
–
E.g., for last‐level cache in a modern CPU improve expected Giga Ops/sec (EGOPS) • By 1.5x compared to optimized versions of previous approaches
• By 2.5x in the near future
E.g., optimally add spare cores to 512‐core GPU and use processor binning to improve revenue per wafer to within 17% of an ideal process (zero defect density) for a process that has very high defect density
Computer Architecture
Computing Clouds, Internet of Things
and BigData Security Kai Hwang
Cloud Ecosystem for Internet of Things
• Cloud services, benchmarks and IoT/SN apps.
• Wireless and satellite Internet infrastructure
for mobile and pervasive computing
• RFID, sensor networks and assisted GPS
services in cyber-physical and IoT systems
Bigdata Integrity, Privacy, and
Analytics for Trusted Computing
• Community clouds with associative big-data
sharing over virtual disks
• Privileged access protocols based on roles and
attributed key management
• Reputation and accountability systems for
trusted P2P, grid and cloud Computing
Internet Computing with trusted clouds, IoT,
P2P networks and automated datacenters
Parallel and Distributed Computing
Viktor K. Prasanna
Multi-core/Heterogeneous
Architectures
• Multithreaded applications
• Software routers
• Graph analytics
• GPU computing
• Scalable parallel algorithms
Application Specific
Accelerators on FPGAs
• High-Speed networking
• Terabit IP forwarding
• Virtualized routers
• Security firewalls
• Data center networks
• Energy efficiency
Big Data Platforms
and Applications
• Time series graph analytics
• Cloud resource management
• Social network analysis
• Analytics for smart
infrastructure (smartgrid,
smart oil fields,..)
http://ceng.usc.edu/~prasanna
Cloud Computing & Energy Informatics
Yogesh Simmhan
 Scalable Software Frameworks for
Clouds & Distributed Systems
• Streaming dataflow & workflow models for
realtime data processing
• ‘Big Data’ analytics on Timeseries Graphs
 Algorithms, Scheduling, Programming
Abstractions, Resiliency, Data Mgmt.
 USC Center for Energy
Informatics cei.usc.edu
• Software Arch. for Smart
Grid Demand Response
• Big Data Integration &
Enterprise Social Networks
LADWP Smart Grid &
USC Micro Grid
Resilient & Efficient Systems
Murali Annavaram
Resilient Systems
Energy Efficient Systems
• PARMA/MACAU: Can a cache design survive 7
years with multi-bit soft errors?
S
Q(k) 
 q
l j k{ j}S
b, j
•
KnightShift: How much has your server
efficiency improved?
•
Warped Low Power GPU Design
(l j )
• WearMon: Detect failures before they occur?
• Warped-DMR: Error detection on a dime (nearly free)
36
SMART Interconnects Group
Timothy M. Pinkston
Power-Performance-Resource Efficiency
IBM Blue Gene Supercomputer
• Efficient communication among hundreds to many
storage computation
thousands of CMP cores is needed in near future:
 Network-on-chip architectures designed to
reduce power consumption, maximize
performance and require minimal resources
while remaining resilient in presence of faults
 Multi-scale system interconnects that satisfy
growing, diverse quality-of-service demands Intel Polaris 80‐core die communication
• Techniques: multi-objective optimization, proactive
power gating, performance-guarded/critical design
Holistic Design and Management
• Mutually aware processor-memory-interconnect
design and resource management (cross-cutting)
 Virtualization and coordinated management
Static energy (norm. to No_PG)
No_PG
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
Conv_PG
Conv_PG_OPT
NoRD
Microarchitecture, Multiprocessors, Reliability
Michel Dubois
Micro-architecture
•
Memory Protocols for Tools for Measuring
CMPs
Resilience to Soft
•
Better cache protocols for
Errors
transactional memory and bulk
OoO cores and caches have
unpredictable behavior.
• Idea: stabilize their MIPS rate
• Good for meeting deadlines, power,
consistency models
EPI
•
Speculative protocol
Use a PID control loop
transactions in TMs
•
•
Parallel Simulations of
CMPs on CMPs
•
How to exploit current chip
multiprocessors to simulate future
chip multiprocessors
•
Parma, Parma+: Estimate
reliability of caches under
Temporal and Spatial
MBEs
Extension to main Memory
Extremely Low cost
Error Correction in
Memories
CPPC: Correctable Parity
Protected Cache
CIEC: Chip-Independent Error
Correction (in DRAMs)
Network
Networked Systems Performance and Design Lab
Konstantinos Psounis
•
•
•
Modeling and analyzing the performance of a variety of wired and wireless networks
– including the Internet, WiFi, cellular, mobile, delay and disruptive tolerant, sensor,
mesh, and peer to peer networks, as well as the web
Designing algorithms and protocols to solve problems related to such systems
Implementing in software and hardware real-world testbeds to access performance in
practice
–
e.g. building and using software defined radios to experiment with advanced physical
layer techniques, such as distributed multiuser and massive MIMO, in order to address
the wireless bandwidth crunch
Networks, Big Data, and Machine Learning
Cauligi Raghavendra
Wireless and Sensor Networks
• Energy efficient algorithms and
protocols
• Body area sensor networks and
energy management
• Delay tolerant networks – routing, congestion
control, and applications
Failure Prediction in Oil Fields
• Predictive analytics for smart oil fields
• Failure prediction in oil wells in large fields
• Application of machine learning techniques to oil
field problems
Big Data – Time Series Event Graphs
• Data layouts and storage for large graph data
• Graph partitioning, analytics on graphs
NETworks Control, Optimization & Games
Rahul Jain
•
ECON Layer
Internet as an economicallyviable eco-system
Network Market Design
Theory*
SERV Layer
Network Architectures for
QoS-provisioning & Security
Incentivized Network
Architecture Designs*
NET Layer
Distributed Control of LargeScale Networks
Network Utility Maximization
Theory+
PHY Layer
Increase Capacity through
Multi-user schemes
Non-cooperative Multi-User
Comm. Theory*
The economics of incentives for resource sharing, quality of service
provisioning, security and cooperation in networks, wireless and power
systems
–
Design of market mechanisms for bandwidth and spectrum sharing to enable Internet
and wireless networks as economically-viable eco-systems
–
Design of incentivized network architectures for quality of service provisioning and
security
–
Design and analysis of mechanisms for network utility maximization for distributed
control of large scale networks in competitive environments, including power systems
–
Implementation of cooperative communication schemes to increase network capacity
with non-cooperative users
High-Performance Computing and Networking
John Silvester
Areas of Interest: • High Performance Networking
• Software Defined Networking
Current Projects:
• “Condo‐of‐Condos” – a collaboration for sharing High Performance Computing (HPC) Resources among a set of 10+ Universities
• TEN‐II – Next Generation High Performance USC Campus Network ‐ On‐
demand 10G and 100G connectivity to the Researcher utilizing SDN Technology
• International Research Networking Collaboration – project to identify and support international research collaborations requiring high‐
performance networks
Autonomous Networks Research Group
Bhaskar Krishnamachari
Design, analysis and implementation of algorithms
and protocols for Next-Generation Wireless Networks
Low-Power Wireless Sensor Networks
Examples: Backpressure Collection Protocol (BCP), a novel
dynamic routing protocol; and Ecolocation, a sequence‐based
indoor localization algorithm that requires no prior calibration.
Vehicular Networks
In collaboration with General Motors Research, developing new
architecture and mechanisms for cars to talk to each other.
Cognitive Radio
Novel algorithms for opportunistic spectrum access using tools
from stochastic optimization theory, such as multi-armed bandits.
Robotic Networks
Investigating the use of robotic swarms to maintain connectivity
and high-quality of communication in wireless networks.
http://anrg.usc.edu
Power Generation/Measurement/Management
Young H. Cho
GENERATION
•
•
•
•
Multimodal Harvesting
Flexible and Scalable
Highly Efficient Conditioning
Industrial Wireless Sensor Network
MEASUREMENT
•
•
•
•
•
On-chip/On-board Measurement
High Accuracy and High Sampling Rate
Digital Instrumentation/Low Overhead
Account for Process Variation
In-Situ Dynamic and Static Power
Efficient Power
Harvesting for WSN
Sub-circuit power estimates w/error < 1.25%
MANAGEMENT
•
•
•
Scalable Smart Power Grid
Management
High Throughput/Low Latency
Software Defined Network Driven
Intelligently Managing Power Grid Network with Software