ML50x Reconfigurable platform with RT-XSG toolbox support from Opal-RT Technologies User Guide RTXSG-UG-11-02 OPAL-RT Technologies Inc. TABLE of CONTENTS CHAPTER 1: INTRODUCTION About the standalone Xilinx ML50x Platform with Opal-RT I/O interfaces. . . . . . . 1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Audience and Required Skills and Knowledge . . . . . . . . . . . . . . . . . . . 2 Hardware description language (HDL) and fixed-point numbering . . . 2 Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Organization of this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CHAPTER 2: REQUIREMENTS Software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Hardware requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 CHAPTER 3: INSTALLATION CHAPTER 4: HARDWARE DESCRIPTION AND SETUP ML50x Development boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Opal-RT Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Opal-RT Interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog conversion interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Digital conditioning modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CHAPTER 5: BUILDING MODELS WITH THE RT-XSG TOOLBOX Access to the Opal-RT interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data type and rate management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Inserting custom VHDL modules in design . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Generation of the programming file and target platform recompilation . . . . . . . 17 CHAPTER 6: BUILDING VHDL-ONLY USER MODELS User model definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Inserting conversion module controller cores . . . . . . . . . . . . . . . . . . . . . . . . . 21 Simulating a design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Generation of the programming file and target platform reconfiguration . . . . . . 23 Generation of the programming file . . . . . . . . . . . . . . . . . . . . . . . 24 Project setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programming the target platform . . . . . . . . . . . . . . . . . . . . . . . . 24 CHAPTER 7: TROUBLESHOOTING On-board LCD interface messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test example models and programming file. . . . . . . . . . . . . . . . . . . . . . . . . . 28 APPENDIX A: RT-XSG SIMULINK LIBRARY REFERENCE MANUAL © 2008 Opal-RT Technologies Inc. i OPAL-RT Technologies Inc. TABLE of CONTENTS ML50x Analog I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ML50x Digital I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OP5330 DAC I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 OP5340 ADC I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 APPENDIX B: INTERFACE BOARD SIGNAL DESCRIPTION © 2008 Opal-RT Technologies Inc. ii © 2007 Opal-RT Technologies Inc. All rights reserved for all countries. Information in this document is subject to change without notice, and does not represent a commitment on the part of OPAL-RT Technologies. The software and associated files described in this document are furnished under a license agreement, and can only be used or copied in accordance with the terms of the agreement. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or information and retrieval systems, for any purpose other than the purchaser's personal use, without express written permission of OPAL-RT Technologies Incorporated. Documents and information relating to or associated with OPAL-RT products, business, or activities, including but not limited to financial information; data or statements; trade secrets; product research and development; existing and future product designs and performance specifications; marketing plans or techniques, client lists, computer programs, processes, and know-how that have been clearly identified and properly marked by OPAL-RT as “proprietary information,” trade secrets, or company confidential information. The information must have been developed by OPAL-RT and is not made available to the public without the express consent of OPAL-RT or its legal counsel. ARTEMIS, RT-EVENTS, RT-LAB and DINAMO are trademarks of Opal-RT Technologies, Inc. MATLAB, Simulink, RealTime Workshop and SimPowerSystem are trademarks of The Mathworks, Inc. LabVIEW is a trademark of National Instruments, Inc. QNX is a trademark of QNX Software Systems Ltd. All other brand and product names are trademarks or service marks of their respective holders and are hereby acknowledged. We have done our best to ensure that the material found in this publication is both useful and accurate. However, please be aware that errors may exist in this publication, and that neither the authors nor OPAL-RT Technologies make any guarantees concerning the accuracy of the information found here or in the use to which it may be put. Published in Canada Contact Us For additional information you may contact the Customer Support team at Opal-RT at the following coordinates: Tool-Free (US and Canada) 1-877-935-2323 (08:30-17:30 EST) Phone 1-514-935-2323 Fax 1-514-935-4994 E-mail support@opal-rt.com info@opal-rt.com sales@opal-rt.com Mail 1751 Richardson Street Suite 2525 Montreal, Quebec H3K 1G6 Web www.opal-rt.com 1 Introduction 1.1 About the standalone Xilinx ML50x Platform with Opal-RT I/O interfaces ML50x is a family of FPGA development platforms manufactured by Xilinx Inc. corresponding to boards ML505, ML506, ML507 and XUPV5-LX110T. Each of these platforms include a high-capacity, very-highspeed FPGA reprogrammable device along with extended interface capability. The programmable chip for each member of the family is: • ML505: Virtex5 LXT xc5vlx50t (logic-optimized); • ML506: Virtex5 SXT xc5vsx50t (signal-processing-optimized); • ML507: Virtex5 FXT xc5vfx70t (high-speed connectivity); • XUPV5-LX110T : Virtex5 LXT xc5vlx110t (logic-optimized). The user has the freedom to generate a custom, application specific model to be implemented onto the FPGA device. Opal-RT provides signal conditioning and conversion modules to be attached into the custom model for real-time, hardware-in-the-loop data processing. The RT-XSG toolbox from Opal-RT provides a convenient, Simulink-based way to build the user model. Nevertheless, a user with appropriate knowledge has the possibility to configure the system with an all-VHDL user model. 1.2 Key Features Reconfigurability ML50x platform FPGA devices can be configured exactly as required by the user, not just with the board manufacturer default configuration. Integration with Simulink and the System Generator for DSP toolbox from Xilinx allows the transfer of Simulink submodels to the ML50x FPGA processor for distributed processing. In addition, standard and user-developed functions can be stored on the on-board Flash memory for instant start-up. All supported standalone products supported by the RT-XSG toolbox are configurable on-the-fly using a JTAG connection and the device vendor programming software. Performance ML50x series products enable update rates of 100 MHz, providing the capability to perform timestamped capture and generation of digital events for high precision switching of items such as PWM I/O signaling up to very high frequencies, as I/O scheduling is performed directly on the ML50x board. OP5300 family of conversion and conditioning modules provides real-time access to interface I/O signals. Channel Density Opal-RT interface card to ML50x products provides up to 22 Digital I/Os on a single device, along with up to 32 simultaneous 16-bit ADC and DAC channels. Digital conditioning modules provide a sampling rate of up to 100 MHz while analog conversion modules are configured with user-defined sampling rate, up to 500 kHz. RTXSG-UG-11-02 1 Intended Audience and Required Skills and Knowledge Introduction 1.3 Intended Audience and Required Skills and Knowledge The intended user of the Xilinx ML50x Platforms with Opal-RT I/O interfaces is a R&D, algorithm or Test Engineer that needs a reconfigurable, very-high-speed, portable and low-cost processing unit with good analog and/or digital I/O capabilities. 1.3.1 Hardware description language (HDL) and fixed-point numbering With the help of Xilinx’s System Generator for DSP Blockset, only minimal programmable logic technical knowledge is needed to use the Xilinx ML50x Platforms with Opal-RT I/O interfaces. This blockset is used to translate a Simulink design built using particular library blocks into HDL. This translated design is used by Opal-RT tools to give access to I/O interfaces and debugging facilities. However, the user should be familiar with the fixed-point numerical format and fixed-point data processing. The use of floating point numbers is very heavily resource consuming into FPGA processing devices and is not suitable in RT-XSG devices as the interface to the conversion modules is in a fixedpoint format. A minimal training on FPGA architecture is also recommended. 1.3.2 Simulink Simulink is a software package developed by the Mathworks that enables modeling, simulation and analysis of dynamic systems. Models are described graphically, following a precise format based on a library of blocks. RT-XSG uses Simulink to define models that will be executed by the reconfigurable platform. It is expected that the user has a clear understanding of Simulink operation, particularly regarding the model definition and simulation parameters. 1.4 Organization of this Guide This document is the user guide. The topics covered are: • Introduction on page 1- Provides an introduction to simulation and the principles behind the use of the ML50x platform with OpalRT I/O interfaces. • Requirements on page 5 - Software/hardware requirements for the use of the ML50x platform with Opal-RT I/O interfaces. • Installation on page 7 - Procedure to install the ML50x platform with Opal-RT I/O interfaces libraries and hardware. • Hardware description and setup on page 9 - Describes the hardware components related to the ML50x platform. • Building models with the RT-XSG toolbox on page 15 Describes the procedure to generate a configuration file for the ML50x Platform using the Simulink-based editor and simulator, RTXSG. • Building VHDL-only user models on page 19- Describes the procedure to generate a configuration file for the ML50x Platform without RT-XSG. • Troubleshooting on page 27 - Asserts some of the problems that may be encountered while developing using the ML50x Platform. 2 RTXSG-UG-11-02 Conventions 1.5 Conventions Opal-RT guides use the following conventions: Table 1: General and Typographical Conventions THIS CONVENTION Bold Note: INDICATES User interface elements, text that must be typed exactly as shown. Emphasizes or supplements parts of the text. You can disregard the information in a note and still complete a task. Warning: Describes an action that must be avoided or followed to obtain desired results. Recommendation: Describes an action that you may or may not follow and still complete a task. Code Sampel code. Italics Reference work titles. Blue Text Cross-references (internal or external) or hypertext links. RTXSG-UG-11-02 3 Introduction 4 Conventions RTXSG-UG-11-02 2 Requirements 2.1 Software requirements The Xilinx ML50x Platforms with Opal-RT I/O interfaces needs the following softwares in order to be able to generate a programming file for the reconfigurable device and to program the platform: Minimal configuration (all-VHDL projects): • Operating system: • Microsoft Windows XP (32/64-bit versions) or • Linux Red Hat Enterprise Linux 4 WS (32/64-bit) or • Linux Red Hat Enterprise Linux Desktop 5 (32/64-bit) or • Linux SUSE Linux Enterprise 10 (SLED) or Server (SLES) (32 and 64 bit); • Xilinx ISE design suite v10.1.03 with IP Update 3 or later1. Recommended configuration (with RT-XSG support): • Microsoft Windows XP (32-bit version); • Xilinx ISE design suite v10.1.03 with IP Update 3 or later (See footnote 1.); • Xilinx System Generator for DSP v10.1.03 or later (See footnote 1.); • Matlab R2007a, R2007b or R2008a. 2.2 Hardware requirements Minimal configuration • A Xilinx Download Cable, compatible with JTAG configuration using iMPACT; • One ML505, ML506, ML507 or XUPV5-LX110T development platform. It is recommended that this platform be in an Opal-RTprovided case, which provides adequate structure to hold the I/O interfaces; • Refer to the third-party software documentation for host computer minimal hardware configuration. 1.Xilinx ISE Design Suite, IP and System Generator for DSP should always correspond to the latest available update. In particular, compatibility issues require that the installed release of each component to match (e.g. ISE Design Suite 10.1.03 with IP Update 3 and System Generator 10.1.03, or any later matching release of all the subcomponents). Updating one of the Xilinx subcomponents is likely to require an update of all other Xilinx tools and libraries to ensure full software compatibility. OPXSG-UG-11-02 5 Requirements 6 Hardware requirements OPXSG-UG-11-02 3 Installation Three steps must be performed to install the product, assuming that all the required third-party softwares are already installed: 1. Install the RT-XSG toolbox by running the installer. Follow the on-sceen instructions. After the installation, the following folders are created: • <RTXSG_ROOT>/Docs: Documentation folder; • <RTXSG_ROOT>/Common/script: Contains script files used to generate the programming files and to program the platform from within ISE; • <RTXSG_ROOT>/Common/libfpga: Hardware description folder (contains files necessary for the synthesis of the base configuration of the board); • <RTXSG_ROOT>/Simulink: Opal-RT RT-XSG Toolbox folder; • <RTXSG_ROOT>/Examples: Contains example user models. The installation also added the toolbox folders to the Matlab path and added the following files in the Matlab toolbox directory: • <Matlab installation directory>/toolbox/local/startup.m • <Matlab installation directory>/toolbox/local/setup_rtxsg.m Finally, an environment variable is created in your operating system: • RTXSG_ROOT=<RTXSG_ROOT>, where <RTXSG_ROOT> is your installation directory. 2. Configure the ML50x board as described below: • Jumper J20 must be set to “3.3V” as illustrated by Figure 1 Figure 1:Jumper J20 position to ensure compatibility with Opal-RT interface signals voltages. RTXSG-UG-11-02 7 Installation • The configuration DIP switch SW3 must be set to “Slave SelectMAP” at the address “000”, as illustrated by Figure 2. Figure 2:Configuration DIP switch SW3 recommended position. • The Opal-RT passive interface card must be connected on top of the ML50x board. 3. Connect a JTAG download cable from the host computer to the J1 connector of the ML50x board. This connection is used to configure the board with the User configuration file. J1 is located on the left-hand side of the configuration DIP switch SW3. On Figure 2, 14-pin flat cable connects J1 to the Xilinx JTAG download cable. 8 RTXSG-UG-11-02 Hardware description and setup 4.1 4 ML50x Development boards ML505, ML506, ML507 and XUPV5-LX110T platforms (referred as ‘ML50x’ in this guide) are multipurpose evaluation platforms intended to investigate and experiment programmable device configuration with the feature-rich Virtex5 FPGA family from Xilinx. They provide extended I/O capabilities at a very affordable price. However, these boards are intended for evaluation purposes only and are not recommended for transceiver characterization. Please refer to Xilinx documentation1 for further details on these boards architecture. Their many features include: • Xilinx Virtex-5 FPGA; • Configuration using two Xilinx XCF32P Platform Flash PROMs (32 Mb each) for storing large device programming data; • Xilinx System ACE™ CompactFlash configuration controller with Type I CompactFlash connector; • 64-bit wide, 256-MB DDR2 small outline DIMM (SODIMM), compatible with EDK supported IP and software drivers; • Clocking (programmable clock generator, external or on-board oscillator clock); • General purpose DIP switches (8), LEDs (8), push buttons, and rotary encoder; • Expansion header with 32 single-ended I/O, 16 LVDS-capable differential pairs, 14 spare I/Os shared with buttons and LEDs, power, JTAG chain expansion capability, and IIC bus expansion; • RS-232 serial port, DB9 and header for second serial port; • 16-character x 2-line LCD display; • One 8-kb IIC EEPROM and other IIC capable devices; • Video input/output: • Video input (VGA); • Video output DVI connector (VGA supported with included adapter). • ZBT synchronous SRAM, 9 Mb on 32-bit data bus with four parity bits; • Intel P30 StrataFlash linear flash chip (32 MB); • 10/100/1000 tri-speed Ethernet PHY transceiver and RJ-45 with support for MII, GMII, RGMII, and SGMII Ethernet PHY interfaces; • USB interface chip with host and peripheral ports; • JTAG configuration port for use with Parallel Cable III, Parallel Cable IV, or Platform USB download cable; • GTP/GTX: PCI Express® (PCIe™) edge connector (x1 Endpoint); • GTP/GTX: SATA (dual host connections) with loopback cable. 1.See Xilinx ML505/ML506/ML507 Evaluation Platform User Guide, UG347 v.3.0.1, July 2008. RTXSG-UG-11-02 9 Opal-RT Connectivity Hardware description and setup 4.2 Opal-RT Connectivity Opal-RT provides an easy way to acquire and generate analog and digital signals. The two expansion headers of the ML50x are used to transfer digital data towards/from the analog conversion units and digital conditioning modules through a passive interface board. Opal-RT connectivity modules enables the ML50x programmable device to access: • Two analog signal banks, each of which attached to either: • 16 differential analog input signals or • 16 differential analog output signals; • Two digital signal banks, each of which attached to either: • 11 digital input lines or • 11 digital output lines. IMPORTANT: On the ML50x board, jumper J20 must be set in the ‘3V3’ position in order to use adequately the expansion headers in conjunction with the Opal-RT interface board. 4.2.1 Opal-RT Interface board An interface board is provided by Opal-RT to serve as a routing and identification interface for the I/O modules. It attaches the two ML50x expansion headers to the four analog and digital banks (Figure 3). Each of the two analog channel banks is associated to a distinct 40-pin flat cable connector (J7 and J8 for Banks A and B, respectively) while both digital channel banks are accessed using a single 40-pin connector, J9 (Figure 4). OP5330 Digital-to-analog Conversion Mezzanine Module Opal-RT Interface board to ML50x ML50x Virtex-5 Computational Node OP5340 Analog-to-digital Conversion Mezzanine Module Figure 3:Opal-RT Interface board layout. 10 RTXSG-UG-11-02 Opal-RT Interface board Alternatively to the two on-board conversion mezzanine connectors, these two connectors enable the conversion modules to be located on an external OP52xx carrier This connector gives access to the digital signal banks Figure 4:Opal-RT Interface board I/O connectivity. Note: Alternatively to the 40-pin flat cables, analog banks may also be located directly on the interface board using connectors P12-P13 for Bank A and P14-P15 for Bank B, as shown in Figure 3. In addition to routing, the interface board provides interface type identification via jumpers P6 to P11. This feature is added as a security item to prevent contention on interface signals if the modules expected by the user model are not compatible with the actual configuration of the platform. It is assumed that the interface board configuration would change on a rare basis. It is the responsibility of the user to verify that the jumper positions represent correctly the type of board attached to each signal bank. IMPORTANT: Jumpers P6-P11 MUST be set to match the signal conditioning or conversion module type physically attached to each corresponding bank (see Table 2). A mismatching interface configuration may prevent the user model to leave its reset state. The user model is allowed to run only if the expected boards, if any, are attached to the interface board using the appropriate banks. If no conditioning or conversion board is expected on a particular bank, the model is allowed to run, regardless of the jumper-specified identification of the configuration for that specific bank. Identification mismatches are displayed on the on-board LCD interface to help configuration troubleshooting. RTXSG-UG-11-02 11 Analog conversion interface Hardware description and setup Table 2: Jumper positions and correspondence to digital and analog banks. Jumper P6-P7 P8-P9 P10 P11 Bank Analog Bank A Analog Bank B Digital Bank B Digital Bank A Position Attached board Notes ADC-(center) OP5340 Interface signal direction is set to the OP5340 ADC settings DAC-(center) OP5330 Interface signal direction is set to the OP5330 DAC settings No jumper none All interface signals are put in high-impedance ADC-(center) OP5340 Interface signal direction is set to the OP5340 ADC settings DAC-(center) OP5330 Interface signal direction is set to the OP5330 DAC settings No jumper none All interface signals are put in high-impedance DI-(center) OP5311 Interface signal are all inbound DO-(center) OP5312 Interface signal are all outbound No jumper none All interface signals are put in high-impedance DI-(center) OP5311 Interface signal are all inbound DO-(center) OP5312 Interface signal are all outbound No jumper none All interface signals are put in high-impedance 4.2.2 Analog conversion interface Two types of analog conversion modules are available: the OP5340 is a bank of analog-to-digital converters and the OP5330 is a bank of digital-to-analog converters. Two banks of either type can be attached to the interface board. It is recommended to place the analog conversion banks onto an OP5220 passive carrier, thus providing an easy access to the modules on the front panel of the ML50x box. However, direct connection of the analog banks onto the interface board is possible via connectors P12-P13 for Bank A and P14-P15 for bank B. In this case, the analog channels are accessed via a port on the backplane of the box. OP5330 and OP5340 features are: • Up to 16 analog Input (OP5340) or Output (OP5330) channels; • One 16-bit ADC (OP5340) or DAC (5330) per channel; • Simultaneous sampling on all channels eliminates skew errors inherent in multiplexed channels; • Up to 500 kS/s update rate for every channel. Total throughput of up to 8 MS/s; • Dynamic range of ± 16V; • Accuracy of +/- 5mV; • Hardware configurable on-board signal conditioning and antialiasing filter; • On-board EEPROM memory for calibration parameters; • Library of drag-and-drop Opal-RT RT-XSG blocks for Simulink (see Chapter 5 ) and hardware cores for Xilinx ISE (see Chapter 6 ) firmware generation. Note: See Appendix B for more information on external port channel mapping. 12 RTXSG-UG-11-02 Digital conditioning modules 4.2.3 Digital conditioning modules Two types of digital conditioning modules are available to access the digital I/Os of the ML50x user model. The OP5311 is a 16-channel digital input conditioning module. The OP5312 is a 16-channel digital output conditioning module. Both types of conditioning modules include optocoupler-isolated lines that can accommodate I/O currents in the order of hundreds of milliamperes. It is recommended to place the digital conditioning banks onto an OP5210 passive carrier, thus providing an easy access to the modules on the front panel of the ML50x box. However, nonconditioned digital I/Os can be accessed directly from the interface board, via a port on the backplane of the box. Warning: Please note that signals connected directly to the interface board without passing through the conditioning modules are not isolated from the ML50x board and high input currents may cause the board to present functionality errors or induce defects. Note: Due to the ML50x expansion header limitation, the user model has access to the first 11 lines of the 16-line conditioning modules. See Appendix B for more information external port channel mapping. RTXSG-UG-11-02 13 Hardware description and setup 14 Digital conditioning modules RTXSG-UG-11-02 Building models with the RT-XSG toolbox 5 RT-XSG is a Matlab/Simulink toolbox developed by Opal-RT Technologies that enables a convenient way to create a programming file for the ML50x programmable device. It is used in conjunction with the System Generator for DSP toolbox from Xilinx. 5.1 Access to the Opal-RT interface board The I/O components available from the Opal-RT interface board can be accessed through a Simulink User model. Opal-RT Technologies provides an easy to use block set destined to communicate with the interface board (See Chapter 4 ), and thus with the external conditioning and conversion modules (see Figure 5). See the help file of each block for more information on how to interface them in the design, or refer to Appendix A. Adding an interface to an analog or digital bank is as easy as dragging-and-dropping a block from the library into the design and feeding it with a signal of appropriate numbering format. For ML50x platforms, the user has access to 32 analog I/Os, divided in two banks of 16 channels of either analogto-digital or digital-to-analog direction. In addition, 22 digital lines are available, divided into two banks of 11 channels of either inbound or outbound direction. Analog-to-digital and digital-to-analog controllers must be associated into the user design with analog banks. These controller modules are used to serialize/deserialize and encapsulate the control and data signals for the 16 16-bit channels associated to each bank and interface them to the 52-line connectors of the mezzanines (such as P12, P13, P14 and P15 on the interface board). An example of correct association between the interface block and a DAC controller is presented on Figure 6. RTXSG-UG-11-02 15 Access to the Opal-RT interface board Building models with the RT-XSG toolbox Figure 5:ML50x RT-XSG block set. Conversion trigger pulse train Convert DAC_ch1-0 DAC_ch3-2 MezOut DAC_ch5-4 Digital signal generators DAC_ch7-6 DAC_ch9-8 DAC_ch11-10 DAC_ch13 -12 MezA _IO_OUT MezA _IO_IN Mezzanine : OP 5330 DAC_ch15 -14 MezCtrlOut MezA _CtrlOUT MezIN MezA _CtrlIN ML 50 x Analog Bank A MezCtrlIN OP 5330 DAC IF Figure 6:An analog conversion interface block has to be looped to a controller block. In this example, the ML50x Analog Bank A block is associated to a DAC controller block. 16 RTXSG-UG-11-02 Data type and rate management 5.2 Data type and rate management Opal-RT RT-XSG library blocks have predefined input/output port fixed-point formats. These formats cannot be changed by the user as they must match the type expected from external modules ports, such as the ADC and DAC control signals. In addition, the clock frequency of the ML50x board is fixed to 100 MHz. Even if this frequency can be changed through a programmable chip on the board, user should not attempt to change the clock frequency. This clock is given by the “USR CLOCK” DIP crystal on the ML50x board. It is recommended that the user leave the original component in place at all time, as it ensures appropriate timing for the Opal-RT-supported devices. Slower processing rates can be achieved by using downsampling and upsampling blocks from the System Generator for DSP Blockset. Note that he clock distribution is absent from the Simulink RT-XSG design as it is managed by the Xilinx and Opal-RT toolboxes. However, it is important to keep in mind the importance of the clock in hardware computing. Note: Passing through a majority of blocks from the System Generator library induces a delay on the signals, ranging from picoseconds to tens of nanoseconds. It might be necessary to reduce the sampling rate of certain parts of the computation processes in order for that delay to become negligible. 5.3 Inserting custom VHDL modules in design The easiest way to include a VHDL user model into the system is to instantiate it as a “black box” into the Simulink RT-XSG design. This method may facilitate the interface with Opal-RT conversion module controllers (ADC and DAC interfaces). Refer to the ‘Black box’ block help from the System Generator for DSP Blockset for more informations on how to configure a black box. Nevertheless, it is possible to build all-VHDL user models without the help of Matlab and the System Generator toolbox. Details on how to perform manual user model compilation and synthesis can be found in Chapter 6 of this guide. 5.4 Generation of the programming file and target platform recompilation The ‘Opal-RT FPGA Synthesis Manager’ block includes all the functionalities needed to compile the RTXSG user model and to translate it into a programming file suitable for the reprogrammable device of the ML50x board. It also enables direct configuration of the board using a JTAG Platform cable. In order to generate the programming file, the following steps must be performed: • Verify the correctness of the design using the “Update Diagram” button (Ctrl-D) from the Simulink toolbar and correct the errors, if any; • Insert a ‘Opal-RT FPGA Synthesis Manager’ block into your design. In this block GUI (Figure 7), select the appropriate reprogrammable platform from the list and click the “Generate programming file” button. Programming file generation will take several minutes to complete. Note: For a programming file to be generated, the user must set the “Rebuild option” parameter to ‘Always’ or ‘Only if changes needed’. This requirement is included to prevent unwanted compilations, as this operation can take from several minutes to several hours to complete, depending on the system characteristics. After the generation of a valid programming file, the user can easily program the target platform by performing the following steps: RTXSG-UG-11-02 17 Building models with the RT-XSG toolbox Generation of the programming file and target platform recompilation • Connect a JTAG platform cable from the host computer to the target platform; • Power-up the target platform; • Click the “Program (JTAG)” button from the ‘Opal-RT FPGA Synthesis Manager’ block GUI (Figure 7); Note: The programming file generation log information is written to the file $Current_Directory/RT-XSG Reports/<path to current design>/xflow.result. Generation errors, including resource shortage or routing errors, can be found by parsing this file. Figure 7:Opal-RT FPGA Synthesis Manager graphical user interface. 18 RTXSG-UG-11-02 6 Building VHDL-only user models Opal-RT Technologies provides a basic core library that the user can use to create a complete design without the help of Matlab nor Simulink. The paradigm is the same as the one of RT-XSG Simulink models, but lower abstraction layers, that are transparent when working with Opal-RT RT-XSG Simulink toolbox, must be taken into account by the user. Specifically, the User model signals are attached to a “base configuration”, which is the top-level hierarchical entity of the reprogrammable device. The base configuration serves as an interface from the user model to the outside world (i.e. the components and ports on the target platform outside the programmable device). It manages signal routing and I/O configuration compatibility with the user model, along with the LCD user interface. Warning: Building VHDL-only user models, and inclusion of these models into the target platform base configuration without the help of Simulink System Generator for DSP and Opal-RT RT-XSG toolboxes is recommended only to experimented users. Basic knowledge of electronics and digital design is strongly advised. In addition, it is recommended for the user to familiarize with ISE Design Suite softwares before trying to use the Opal-RT core library within a system. Refer to Xilinx resources for tutorials and User Guides for the ISE Design Suite softwares. 6.1 User model definition The User model has a pre-defined interface definition for communicating with the Base configuration (see Figure 8). The user is responsible of building a VHDL high-level entity for its User model that is compatible with this interface. The content of the user model is free to the designer. However, the user must keep in mind that the limited FPGA resources may impose user optimization for complex designs. In this case, advanced knowledge of the particular FPGA device family architecture is suitable. Also, number format management must be performed by the designer, as all inputs and outputs of the user model are in binary, or binary vector format (std_logic or std_logic_vector standard signal types). bitstream_ver bitstream_minorid ov52_MezIO_A i_clk i_nRst i_ModelSync 52 52 12 12 iv52_MezIO_A iv52_MezIO_B iv12_EXT_A_IO iv12_EXT_B_IO i_MezCtrl_A i_MezCtrl_B ov52_MezIO_B ov12_EXT_A_IO ov2_EXT_A_IO_ExpectedBoardID ov12_EXT_B_IO ov2_EXT_B_IO_ExpectedBoardID ov3_MezCtrl_A ov3_MezCtrl_B ov2_MezExpectedID_A ov2_MezExpectedID_B 8 5 52 52 12 2 12 2 3 3 2 2 user_model Figure 8:User model highest-level interface ports. RTXSG-UG-11-02 19 User model definition Building VHDL-only user models Additionally, the user is allowed to include pre-synthesized cores into the design, as in any VHDL architecture. In particular, analog conversion module interfaces are part of the Opal-RT core library and must be instantiated into the user model in order to be able to communicate with the analog-to-digital and digital-to-analog conversion banks. The procedure described in Section 6.2 must be used to instantiate a conversion controller core into the user model. A similar procedure can be implemented for any other core. Note: A ‘Core’ is a precompiled, presynthesized subsystem of a design. The synthesis is often specific to a certain programmable device family. Thus, core generation must be performed again if the target platform is built around a different reprogrammable device. CoreGenerator, from the Xilinx ISE Design Suite, may be used to generate standard cores. The following table summarizes the interface signals description and type definition: Table 3: Interface signal description of the user model Signal Name Direction Width i_clk in 1 std_logic Clock signal. i_nRst in 1 std_logic Asynchronous reset. i_ModelSync in 1 std_logic Optional synchronization pulse train (fed by the user or a master device to pin 4 of the RTSI header on the interface board). std_logic_vector Input data bus for communication with the Analog conversion module (Bank A). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). iv52_MezIO_A 52 Description iv52_MezIO_B in 52 std_logic_vector Input data bus for communication with the Analog conversion module (Bank B). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). iv12_EXT_A_IO in 12 std_logic_vector Input interface with the Digital Conditioning module (Bank A). Used only if the corresponding bank expects inbound signals. iv12_EXT_B_IO in 12 std_logic_vector Input interface with the Digital Conditioning module (Bank B). Used only if the corresponding bank expects inbound signals. std_logic Input control bus for communication with the Analog conversion module (Bank A). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). i_MezCtrl_A in 1 in 1 std_logic Input control bus for communication with the Analog conversion module (Bank B). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). bitstream_ver out 8 std_logic_vector User-defined release (‘Version’) identification number of the current user model. bitstream_minorid out 5 std_logic_vector User-defined minor identification number for the current user model. ov12_EXT_A_IO out 12 std_logic_vector Output interface with the Digital Conditioning module (Bank A). Used only if the corresponding bank expects outbound signals. ov12_EXT_B_IO out 12 std_logic_vector Output interface with the Digital Conditioning module (Bank B). Used only if the corresponding bank expects outbound signals. i_MezCtrl_B 20 in Type RTXSG-UG-11-02 Inserting conversion module controller cores Signal Name Direction Width Type Description Expected configuration for the Digital Bank A: ov2_EXT_A_IO_ ExpectedBoardID out 2 std_logic_vector 00: 01: 10: 11: Digital input bank Reserved for future use No/unused interface Digital output bank Expected configuration for the Digital Bank B: ov2_EXT_B_IO_ ExpectedBoardID out ov52_MezIO_A out ov52_MezIO_B out 2 52 52 std_logic_vector 00: 01: 10: 11: Digital input bank Reserved for future use No/unused interface Digital output bank std_logic_vector Output data bus for communication with the Analog conversion module (Bank A). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). std_logic_vector Output data bus for communication with the Analog conversion module (Bank B). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). ov3_MezCtrl_A out 3 std_logic_vector Output control bus for communication with the Analog conversion module (Bank A). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). ov3_MezCtrl_B out 3 std_logic_vector Output control bus for communication with the Analog conversion module (Bank B). To use the bank, the user must connect this port to a Conversion module controller (see Section 6.2). Expected configuration for the Analog Bank A: ov2_MezExpectedID_A out 2 std_logic_vector 00: 01: 10: 11: Analog input bank (ADC) Reserved for future use No/unused interface Analog output bank (DAC) Expected configuration for the Analog Bank A: ov2_MezExpectedID_B 6.2 out 2 std_logic_vector 00: 01: 10: 11: Analog input bank (ADC) Reserved for future use No/unused interface Analog output bank (DAC) Inserting conversion module controller cores In order to instantiate a controller module core, as for any other core, the following procedure must be used: • Declare the core entity interface as a ‘Component’ into a reference VHDL package or in the instantiating entity architecture header. • Include a reference to the core in the instantiating entity architecture body and map its interface ports to signals/ports of the instantiating entity. In particular, the interface of the cores with the User model highest-level ports must include the connections of Table 4.Port description of the controller entities is detailed in Table 5 and Table 6. RTXSG-UG-11-02 21 Inserting conversion module controller cores Building VHDL-only user models Table 4: Port correspondence between analog convertion controllers and User model highest-level entity Core port User model porta MezIn iv52_MezIO_<bank> MezCtrlIn i_MezCtrl_<bank> MezOut ov52_MezIO_<bank> MezCtrlOut ov3_MezCtrl_<bank> a.<bank> refers to the letter of the corresponding analog bank, either {A,B} Table 5: Port description of the DAC controller entity 22 Core port Direction Width Description i_clk in 1 Clock signal. i_nrst in 1 Asynchronous negative reset signal. i_Convert in 1 Conversion start command. Send a 1-clock cycle pulse to request all channel to sample their input data. iv33_DAC_ch1_0 in 33 Data to be converted for channels 0 and 1: iv33_DAC_ch1_0(32): Reserved for future use; iv33_DAC_ch1_0(31:16): Channel 1 (binary position: 10); iv33_DAC_ch1_0(15:0): Channel 2 (binary position: 10). iv33_DAC_ch3_2 in 33 Data to be converted for channels 2 and 3 (see “iv33_DAC_ch1_0” pattern). iv33_DAC_ch5_4 in 33 Data to be converted for channels 4 and 5 (see “iv33_DAC_ch1_0” pattern). iv33_DAC_ch7_6 in 33 Data to be converted for channels 6 and 7 (see “iv33_DAC_ch1_0” pattern). iv33_DAC_ch9_8 in 33 Data to be converted for channels 8 and 9 (see “iv33_DAC_ch1_0” pattern). iv33_DAC_ch11_10 in 33 Data to be converted for channels 10 and 11 (see “iv33_DAC_ch1_0” pattern). iv33_DAC_ch13_12 in 33 Data to be converted for channels 12 and 13 (see “iv33_DAC_ch1_0” pattern). iv33_DAC_ch15_14 in 33 Data to be converted for channels 14 and 15 (see “iv33_DAC_ch1_0” pattern). MezIn in 52 Conversion board inbound data signals. MezCtrlIn in 1 Conversion board inbound control signals. MezOut out 52 Conversion board outbound data signals. MezCtrlOut out 3 Conversion board outbound control signals. RTXSG-UG-11-02 Simulating a design Table 6: Port description of the ADC controller entity 6.3 Core port Direction Width Description i_clk in 1 Clock signal. i_nrst in 1 Asynchronous negative reset signal. i_Convert in 1 Conversion start command. Send a 1-clock cycle pulse to request all channel to sample their input data. ov33_ADC_ch1_0 in 33 Converted data from channels 0 and 1: ov33_ADC_ch1_0(32): Reserved for future use; ov33_ADC_ch1_0(31:16): Channel 1 (binary position: 11); ov33_ADC_ch1_0(15:0): Channel 2 (binary position: 11). ov33_ADC_ch3_2 in 33 Converted data from channels 2 and 3 (see “ov33_ADC_ch1_0” pattern). ov33_ADC_ch5_4 in 33 Converted data from channels 4 and 5 (see “ov33_ADC_ch1_0” pattern). ov33_ADC_ch7_6 in 33 Converted data from channels 6 and 7 (see “ov33_ADC_ch1_0” pattern). ov33_ADC_ch9_8 in 33 Converted data from channels 8 and 9 (see “ov33_ADC_ch1_0” pattern). ov33_ADC_ch11_10 in 33 Converted data from channels 10 and 11 (see “ov33_ADC_ch1_0” pattern). ov33_ADC_ch13_12 in 33 Converted data from channels 12 and 13 (see “ov33_ADC_ch1_0” pattern). ov33_ADC_ch15_14 in 33 Converted data from channels 14 and 15 (see “ov33_ADC_ch1_0” pattern). MezIn in 52 Conversion board inbound data signals. MezCtrlIn in 1 Conversion board inbound control signals. MezOut out 52 Conversion board outbound data signals. MezCtrlOut out 3 Conversion board outbound control signals. Simulating a design To simulate a user model without using the System Generator toolbox, the user has to use a third-party HDL simulator, as Mentor Graphics ModelSim. A free version of ModelSim Xilinx Edition comes with the ML50x platform. This version of the popular simulator is performance and feature limited. In particular, the performance will decrease significantly for very large designs. It is strongly recommended to simulate separately every part of any design before attempting to use the configuration file with the target platform. 6.4 Generation of the programming file and target platform reconfiguration This section describes how to use the Xilinx ISE Design Suite softwares to generate a programming file for the target platform and how to configure the platform itself. RTXSG-UG-11-02 23 Building VHDL-only user models Generation of the programming file 6.4.1 Generation of the programming file This step is performed using Xilinx ISE Project Navigator. It assumes that the User model has been simulated and works correctly, and that the interface is compatible with the base configuration, as described in the previous sections. 6.4.1.1 Project setup In the project navigator, the user must build a VHDL project containing all the files necessary to the synthesis of the User model. Also, all custom cores generated by the user should be present in the current directory. Finally, the programmable device model must be set correctly (e.g. xc5vsx50t for the ML506 platform). Note: To verify part of the User model correctness, it is recommended to run the synthesis process (from the ISE GUI, by selecting “Synthesis - XST” or from command line) and to correct errors (if any) before proceeding to the following procedure. 6.4.1.2 Workflow In order to automate the generation of the programming file, a script is provided. In the ISE Project Navigator, open the TCL Shell tab from the Transcript window. Verify that the current directory corresponds to the project folder (use ‘pwd’ to check the current directory location and ‘cd’ to change it, if necessary). To generate the programming files, the user only has to write the following line of script, assuming the environment variable “RTXSG_ROOT” exists and points to the RT-LAB toolbox installation directory: On systems running Microsoft Windows operating system: source $env(RTXSG_ROOT)/Common/script/xilinx/win/ImplementDesign.tcl On systems running a Unix-compatible operating systems: source $env(RTXSG_ROOT)/Common/script/xilinx/unix/ImplementDesign.tcl Three Xilinx programs are successively invoked. At the end of the process, the log files are copied into the project directory. If the configuration file generation is successful, the files are located in the project directory, and has the format ‘S17-0101-XSR-XXX-YY-ZZ.bit’ and ‘S17-0101-XSR-XXX-YY-ZZ.mcs’. The *.bit file is the FPGA programming file and the *.mcs file is the target platform configuration Flash memory programming file. The first file is used for immediate FPGA reconfiguration. The latter is used on platform power-up and when the “PROG” button is pressed on the platform to configure the FPGA with the Flash memory content. YY and ZZ are respectively the firmware Version and Minor ID. These variables can be modified by the following TCL commands, where YY is a hexadecimal number chosen between {01, ... , 3F} and ZZ is a hexadecimal number chosen between {00, ... , FF}: set Version YY set MinorID ZZ The complete generation process may take from several minutes to several hours to complete, depending on design complexity and host computer performance. At the end of the process, a confirmation message is written on the TCL transcript. 6.4.2 Programming the target platform A script is provided for the target platform reconfiguration. In the ISE Project Navigator, open the TCL Shell tab of the Transcript window. Verify that the current directory corresponds to the project folder (use ‘pwd’ to check the current directory location and ‘cd’ to change it, if necessary). To program the 24 RTXSG-UG-11-02 Programming the target platform platform, the user only has to write the following line of script, assuming the environment variable “RTXSG_ROOT” exists and points to the installation directory: On systems running Microsoft Windows operating system: source $env(RTXSG_ROOT)/Common/script/xilinx/win/ProgramML50x.tcl On systems running a Unix-compatible operating systems: source $env(RTXSG_ROOT)/Common/script/xilinx/unix/ProgramML50x.tcl Note: The reconfiguration process takes several minutes to complete. At the end of the reconfiguration, a confirmation message is written on the TCL transcript. Note: Version and minor ID of the firmware can be switched by setting the Version and MinorID variables to appropriate values, as described in Section 6.4.1. Note: Before the reconfiguration of the target platform, the current configuration file of the on-board configuration Flash memory is read back named with the format ‘S17-0101-XSR-XXX-YY-ZZ-retrieved.mcs’. The target platform can be programmed back using this configuration by setting the Version and MinorID variables to YY and ZZ-retrieved, respectively. RTXSG-UG-11-02 25 Building VHDL-only user models 26 Programming the target platform RTXSG-UG-11-02 7 Troubleshooting 7.1 On-board LCD interface messages The standalone ML50x board includes a LCD interface that displays system messages. It provides informations on the detected on-board conversion and conditioning I/O interfaces along with information on the firmware version and minor ID. It also displays eventual mismatches between detected and expected conversion and conditioning I/O interfaces identification numbers. Figure 9 shows a typical sequence of messages that is displayed under normal operation of the board. Characteristics of the system described by this example sequence would be: • OP5340 ADC module is connected to the Analog Bank A; • OP5330 DAC module is connected to the Analog Bank A; • OP5312 Digital Out conditioning module is connected to the Digital Bank A; • No module is connected to the Digital Bank B; • The firmware Minor ID is 17 and its Release ID is 192. I V II VI III VII IV Figure 9:An example of a normal message sequence on the target platform LCD interface. If a identification mismatch is detected, a message of the format of Figure 10 is displayed. In this example a mismatch is detected between the expected and actual configuration related to the modules attached to Analog Bank B and Digital Bank A. Note: The version and minor ID information validity is verified only if the programming file is generated using Opal-RT RT-XSG Simulink toolbox. For VHDL-only designs, both variables written onto the LCD come from the variables written by the user in the ISE TCL shell, and is valid only if the variables represent hexadecimal numbers in the appropriate range. The ‘bitstream_version’ and ‘bitstream_minorid’ outputs of the User model are currently not used. RTXSG-UG-11-02 27 Test example models and programming file Troubleshooting Figure 10:Error messages display identification mismatches between expected and actual I/O configuration. This example show that there is an error in Analog/Bank B and Digital/Bank A. 7.2 Test example models and programming file In order to test the hardware setup of the system, a sample model is provided. Figure 11 presents the functional diagram of this system. The model can be accessed by typing >> demos on the Maltab prompt, or from the following folder: <RTXSG_ROOT>/Examples/Standalone/Xilinx/ML506/DigitalAnalogLoopback/ • The RT-XSG example model is the Simulink file: ./SystemGenerator/DigitalAnalogLoopback.mdl; • The VHDL-only model is found in the Xilinx ISE project ./VHDL/DigitalAnalogLoopback.ise. Important: For the example model to behave correctly, the hardware must be connected as illustrated on Figure 11. In addition, configuration jumpers P6-P11 must reflect the type of analog conversion or digital conditioning module connected to each bank. Note: Alternatively to the configuration shown on Figure 11, the following simplifications can be used if any hardware material is not available: • The digital conditioning modules can be omitted. In this case, digital signals can be accessed directly on J9. However, these lines are not electrically decoupled from the ML50x board. • If any of the digital or analog interface is not accessible, the user may set either the corresponding interface Simulink block(for the RT-XSG model) or the ExpectedID port (for the VHDL-only project) to the appropriate value. The configuration file generation for the example model must be generated by the user before reconfiguring the target platform with the procedure described in the preceding chapters. The system can be tested by applying an appropriate voltage on either Analog and Digital bank A and observing if the bank B signals react accordingly. 28 RTXSG-UG-11-02 Test example models and programming file OP5220 Analog passive carrier Base configuration Internal 16-channel analog loopback Opal-RT Interface board 16 J7 16 J8 Section A/Bank A: OP5340 16-Channel ADC Module Section A/Bank B: OP5330 16-Channel DAC Module User Model Section A/Bank B: 11 Internal 11-channel digital loopback OP5311 16-Channel DIn Module J9 11 Section D/Bank B: OP5312 16-Channel DOut Module OP5210 Digital passive carrier Figure 11:Example model functional diagram. RTXSG-UG-11-02 29 Troubleshooting 30 Test example models and programming file RTXSG-UG-11-02 Appendices RTXSG-UG-11-02 RT-XSG Simulink library reference manual A ML50x Analog I/Os Library RT-XSG/ML50x Block ML50x Analog I/Os Figure 12:ML50x Analog I/Os block Mask Figure 13:ML50x Analog I/Os mask. Description These blocks represent the access to the Analog conversion interfaces on the interface card of the reconfigurable ML50x FPGA card. Connector J7 on the interface board is represented by the ‘ML50x Analog Bank A’ block and connector J8 by the ‘ML50x Analog Bank B’ block. Both of these blocks are intended to be connected to either a OP5330 DAC IF block or a OP5340 ADC IF block. These blocks do not use any physical resource of the target board programmable chip. Their presence in the RT-XSG model is optional. If interface analog bank A or B is not used, the corresponding connectivity block can either be omitted from the RT-XSG model or be configured to an “Unconnected” interface type, its inputs being connected to System Appendix A 32 Generator constants of appropriate format and its outputs being connected to Simulink terminators. Parameters Interface Type: Determines the type of Analog conversion module expected to be attached to connector J7 or J8 of the interface card. After a type of interface is selected, the technical name of the Analog conversion card is indicated in the field under the Interface Type selection menu. Inputs Mez{A,B}_IO_OUT: Connect this port to the MezOut port of either a OP5330 DAC IF or OP5340 ADC IF block. This port is used for sample communication between the FPGA and the mezzanine analog cards. Mez{A,B}_CtrlOUT: Connect this port to the MezCtrlOut port of a OP5330 DAC IF or OP5340 ADC IF block. This port is used for accessing the calibration data from the mezzanine cards by the analog interface blocks. Outputs Mez{A,B}_IO_IN: Connect this port to the MezIN port of either a OP5330 DAC IF or OP5340 ADC IF block. This port is used for sample communication between the FPGA and the mezzanine analog cards. Mez{A,B}_CtrlIN: Connect this port to the MezCtrlIn port of a OP5330 DAC IF or OP5340 ADC IF block. This port is used used for accessing the calibration data from the mezzanine cards by the analog interface blocks. Characteristics and Limitations The expected analog conversion card defined by the parameter of this block MUST correspond to the boards attached to connectors J7 and J8. As an electrical compatibility security feature, the position of jumpers P6 and P7 MUST represent the type of mezzanine attached to Analog Bank A (connector J7). Parallely, the position of jumpers P8 and P9 MUST represent the type of mezzanine attached to Analog Bank B (connector J8). If the conversion card type given by the jumper P6 and the 'ML50x Analog Bank A' block are not compatible, an error will be shown on the ML506 LCD panel and the RT-XSG model will not run. The same behavior is implemented between the jumper P9 and the 'ML50x Analog Bank B' block. If no conversion card is expected to be attached to an analog bank, the error generated will not prevent the RT-XSG model to run. Direct Feedthrough Appendix A NO Discrete sample time NO XHP support N/A Work offline NO Opal-RT XSG BLOCKS 33 ML50x Digital I/Os Library RT-XSG/ML50x Block ML50x Digital I/Os Figure 14:ML50x Digital I/Os block Mask Figure 15:ML50x Digital I/Os mask. Appendix A Opal-RT XSG BLOCKS 34 Description The ‘ML50x Digital IOs’ block represent the access to the Digital conditioning banks attached to connector J9 on the interface card of the reconfigurable ML50x FPGA card. These digital banks are usually located on a passive carrier (OP5210) accessible from the target front panel. In order to drive the I/O lines of the modules installed on this carrier, the ML50x interface card must be connected to the backplane adaptor card of the carrier via a 40-pin flat cable. The ‘ML50x Digital IOs’ block supports different I/O modules configurations selectable via parameters of the block mask. Once the user has selected the hardware setup, the adaptor card to be connected to the backplane of the carrier is displayed in the block mask parameters, as well as on the block mask itself. The block inputs and outputs names are updated according to the hardware selected. Depending on the requested configuration, some inputs and outputs are disabled in the block. The names of the disabled ports start with 'NC' and should not be used by the user to provide data to the block. However, unused inputs need to be connected to a constant block of appropriate fixed-point format. Parameters Carrier: Select the type of carrier attached to the ML50x interface card connector J9. I/O type: Select the I/O configuration that matches the I/Os installed on the carrier. Mezzanine Section A: This parameter is not editable. It displays the part number of the module that must be installed on section A of the carrier according to the I/O type configuration selected. Note that some configurations do not require I/O modules to be installed on the carrier. Mezzanine Section B: This parameter is not editable. It displays the part number of the module that must be installed on section B of the carrier according to the I/O type configuration selected. Note that some configurations do not require I/O modules to be installed on the carrier. Adaptor type: This parameter is not editable. It displays the type of adaptor card to be connected to the backplane connector of the selected carrier. Inputs This block has two inputs. Their usage depends on the I/O configuration of the carrier. The inputs represent data to be applied to Digital Output modules. The block supports up to 22 output lines, split in two groups of 11. The first input represents the data to be applied to the first 11 lines, and the second input the data to be applied to the last 11 lines. If the I/O configuration does not include 22 lines of digital outputs, the unused port names are modified to start with 'NC'. In that case, the 'NC' ports must not be connected to model signals, but they must still be connected to a constant block of type UFIX_11_x to prevent configuration file compilation errors. Appendix A Opal-RT XSG BLOCKS 35 Outputs This block has two outputs. Their usage depends on the I/O configuration of the carrier. When the I/Os are digital I/Os, the outputs represent data read from Digital Input modules. The block supports up to 22 input lines, split in two groups of 11. The first output represents the data from the first 11 lines, and the second input the data from the last 11 lines. If the I/O configuration does not include 22 digital input lines, the port names are modified to start with 'NC'. In that case, the 'NC' ports must not be connected to model signals, and can be connected to terminator blocks. Characteristics and Limitations The expected digital conditioning card defined by the parameter of this block MUST correspond to the configuration of the carrier attached to connectors J9. As an electrical compatibility security feature, the position of jumpers P11 and P10 MUST represent the type of mezzanine attached to Digital Banks A and B (connector J9). If the conditioning card type given by the jumper P11 and the ‘ML50x Digital IOs’ block Mezzanine section A parameter are not compatible, an error will be shown on the ML50x LCD panel and the RT-XSG model will not run. The same behavior is implemented between the jumper P10 and the ‘ML50x Digital IOs’ block Mezzanine section B parameter. If no conditioning card is expected to be attached to a digital bank, the error generated will not prevent the RT-XSG model to run. Direct Feedthrough Appendix A NO Discrete sample time NO XHP support N/A Work offline NO Opal-RT XSG BLOCKS 36 OP5330 DAC I/F Library RT-XSG/Common Block OP5330 DAC I/F Figure 16:OP5330 DAC I/F block Mask Figure 17:OP5330 DAC I/F mask. Description The OP5330 DAC IF is used as an interface to the OP5330 16-channel analog output card. Refer to OP5330-Overview1 for more details on this product. This block can only be connected to a “ML50x Analog IOs” block from the RT-XSG library. 1.OP5330 overview is located at: http://www.opal-rt.com/productsservices/hardwarecomponents/op5000/op5330/ Appendix A Opal-RT XSG BLOCKS 37 Parameters None. Inputs Convert: Convert input signal. Connect this input to the ModelSync “From” for synchronization with an external master device or provide an asynchronous sync source. If an asynchronous source is provided, it must generate a 10-ns pulse (FPGA clock period) with a minimum period of 1µs between each pulse (maximum conversion speed of a channel). To have a synchronization of all the channels at the output of the OP5330 card, data samples should be presented in sync with the Convert signal. DAC_chX-Y: This port represents the data samples to be converted by the DAC. Each of the DAC_chX-Y ports represents two analog output channels. This port is of UFix33_0 type where the lower 16 bits represent the first channel (bits 15-0) and bits 31-16 represent the second channel. The 33rd bit is of no significance but must still be connected. The DAC_ch port is a concatenation of two Fix16_11 signals where the maximum output value is 15.9995 after quantization and the minimum is -16. MezIN: Mezzanine connector input. Connect this port to the Mez{A,B}_IO_IN port of the analog I/O connectivity block. This port is used for sample communication between the FPGA and the OP5330 card. MezCtrlIN: Connect this port to the Mez{A,B}_CtrlIN port of the analog I/O connectivity block. This port is used for calibration of the OP5330 card. Outputs MezOUT: Connect this port to the Mez{A,B}_IO_OUT port of the analog I/O connectivity block. This port is used for sample communication between the FPGA and the OP5330 card. MezCtrlOUT: Connect this port to the Mez{A,B}_CtrlOUT port of the analog I/O connectivity block. This port is used for calibration of the OP5330 card. Characteristics and Limitations This block has no special characteristics. Direct Feedthrough Appendix A NO Discrete sample time NO XHP support N/A Work offline NO Opal-RT XSG BLOCKS 38 OP5340 ADC I/F Library RT-XSG/Common Block OP5340 ADC I/F Figure 18:OP5340 ADC I/F block Mask Figure 19:OP5340 ADC I/F mask. Description The OP5340 ADC IF is used as an interface to the OP5340 16-channel analog input card. Refer to OP5340-Overview1 for more details on this product. This block can only be connected to a ML50x Analog IOs block from the RT-XSG library. 1.OP5340 overview is located at: http://www.opal-rt.com/productsservices/hardwarecomponents/op5000/op5340/ Appendix A Opal-RT XSG BLOCKS 39 Parameters None. Inputs Convert: Convert input signal. Connect this input to the ModelSync “From” for synchronization with an external master device or provide a asynchronous sync source. If an asynchronous source is used, it must generate a 10-ns pulse. The maximum period between two pulses is 2µs (maximum conversion speed of a channel). To have a synchronization of all the channels at the output of the OP5340 card, all data samples should be presented in sync with the ModelSync signal. MezIN: Mezzanine input connector. Connect this port to the Mez{A,B}_IO_IN port of the analog I/O connectivity block. This port is used for sample communication between the FPGA and the OP5340 card. MezCtrlIN: Mezzanine input connector. Connect this port to the Mez{A,B}_CtrlIN port of the analog I/O connectivity block. This port used is for calibration data communication between the FPGA and the OP5340 card. Outputs ADC_chX-Y: This port represents the data samples converted by the ADC. Each of the ADC_chX-Y port concatenates the data from two analog input channels. This port is of UFix33_0 type where the lower 16 bits represent the first channel (bits 15-0) and bits 31-16 represent the second channel. The 33rd bit indicates when the data samples are updated. There is a 2.2µs delay between the assertion of the Convert and the update of the samples on the ADC_chX-Y ports. MezOUT: Connect this port to the Mez{A,B}_IO_OUT port of the analog I/O connectivity block. This port is used for the FPGA and the OP5340 card data transmission. MezCtrlOUT: Connect this port to the Mez{A,B}_CtrlOUT port of the analog I/O connectivity block. This port is used for the FPGA and the OP5340 card calibration. Characteristics and Limitations This block has no special characteristics. Direct Feedthrough Appendix A NO Discrete sample time NO XHP support N/A Work offline NO Opal-RT XSG BLOCKS 40 B Interface board signal description This appendix documents the interface board connectors. Refer to Figure 20 to locate these connectors. 2 1 8 4 25 7 26 9 10 12 5 14 6 23 24 17 18 16 11 3 21 20 15 19 13 22 Figure 20:ML50x Opal-RT interface board connectors. Legend: # Name Description # Name Description 1 P16 Conversion modules power supply 14 J9 Digital I/Os, banks A and B 2 J10 Analog I/Os, bank A 15 P11 I/O selector, digital bank A 3 P6 I/O selector, analog bank A 16 P10 I/O selector, digital bank B 4 P7 I/O selector, analog bank A 17 P1 SPI Flash configuration JTAG connector 5 P13 Conversion bank A analog interface 18 J1 SPI Flash configuration JTAG connector 6 P12 Conversion bank A digital interface 19 P5 External JTAG connector 7 J7 External conversion module A interface 20 P4 I²C bus connector 8 J11 Analog I/Os, bank B 21 P3 I²C bus voltage selector 9 P8 I/O selector, analog bank B 22 P2 RTSI synchronization connector 10 P9 I/O selector, analog bank B 23 P17 LCD interface connector 11 P15 Conversion bank B analog interface 24 PROG Reconfiguration button (ML50x) 12 P14 Conversion bank B digital interface 25 P20/J15 Power supply (ML50x) 13 J8 External conversion module B interface 26 SW1 ML50x input power switch Appendix B 41 1. Conversion modules power supply This connector brings the ±18V power supply to the analog conversion modules. It must be connected to the Opal-RT ML50x power supply. 2. Analog I/Os, bank A This DB37 connector gives access to the Bank A analog inputs or outputs. The voltage dynamic range of the converters is ±16V. The following table gives the pinout of the connector: 19 1 37 20 # Pin Name Description # Pin Name Description 1 CHA_00P Analog/Bank A: Channel 0 (positive) 20 CHA_00N Analog/Bank A: Channel 0 (negative) 2 CHA_01P Analog/Bank A: Channel 1 (positive) 21 CHA_01N Analog/Bank A: Channel 1 (negative) 3 CHA_02P Analog/Bank A: Channel 2 (positive) 22 CHA_02N Analog/Bank A: Channel 2 (negative) 4 CHA_03P Analog/Bank A: Channel 3 (positive) 23 CHA_03N Analog/Bank A: Channel 3 (negative) 5 CHA_04P Analog/Bank A: Channel 4 (positive) 24 CHA_04N Analog/Bank A: Channel 4 (negative) 6 CHA_05P Analog/Bank A: Channel 5 (positive) 25 CHA_05N Analog/Bank A: Channel 5 (negative) 7 CHA_06P Analog/Bank A: Channel 6 (positive) 26 CHA_06N Analog/Bank A: Channel 6 (negative) 8 CHA_07P Analog/Bank A: Channel 7 (positive) 27 CHA_07N Analog/Bank A: Channel 7 (negative) 9 CHA_08P Analog/Bank A: Channel 8 (positive) 28 CHA_08N Analog/Bank A: Channel 8 (negative) 10 CHA_09P Analog/Bank A: Channel 9 (positive) 29 CHA_09N Analog/Bank A: Channel 9 (negative) 11 CHA_10P Analog/Bank A: Channel 10 (positive) 30 CHA_10N Analog/Bank A: Channel 10 (negative) 12 CHA_11P Analog/Bank A: Channel 11 (positive) 31 CHA_11N Analog/Bank A: Channel 11 (negative) 13 CHA_12P Analog/Bank A: Channel 12 (positive) 32 CHA_12N Analog/Bank A: Channel 12 (negative) 14 CHA_13P Analog/Bank A: Channel 13 (positive) 33 CHA_13N Analog/Bank A: Channel 13 (negative) 15 CHA_14P Analog/Bank A: Channel 14 (positive) 34 CHA_14N Analog/Bank A: Channel 14 (negative) 16 CHA_15P CHA_15N Analog/Bank A: Channel 15 (positive) 35 17 Not connected 36 Not connected 18 Not connected 37 Not connected 19 Not connected 3. Analog/Bank A: Channel 15 (negative) I/O selector, analog bank A This jumper is used to specify the type of analog conversion module attached to either the Analog/Bank A connectors (P12/P13 or J7). Its position MUST reflect the type of the actually connected module for the system to work. If no module is attached to the Bank A connectors or if the module is known to be unused, the jumper shall be removed from this selector. A mismatch between this jumper position and the expected module ID given by the User model prevents the user model to run. Appendix B Interface board signal description 42 3 DAC 2 1 Position 4. ADC Configuration Type 1-2 An A/D converter module is attached to Analog Bank A 2-3 A D/A converter module is attached to Analog Bank A No jumper No module is attached to Analog Bank A I/O selector, analog bank A This jumper MUST have the exact same position as jumper P6. 3 DAC 2 1 5. ADC Position Configuration Type 1-2 An A/D converter module is attached to Analog Bank A 2-3 A D/A converter module is attached to Analog Bank A No jumper No module is attached to Analog Bank A Conversion bank A analog interface This connector gives the Analog Bank A conversion module access to the input or output analog signals to/from connector J10. The user does not have access to these signals directly. 6. Conversion bank A digital interface This connector gives the Analog Bank A conversion module access to the data and control signals sent to/from the expansion headers of the ML50x board. The user does not have access to these signals directly. 7. External conversion module A interface This connector gives an external analog conversion module access to the data and control signals sent to/from the expansion headers signals related to the Analog Bank A of the ML50x board. The user does not have access to these signals directly. A 40-line flat cable enables the user to attach this connector with a passive interface (e.g. the OP5220 passive analog carrier) carrying the analog module. 8. Analog I/Os, bank B This DB37 connector gives access to the Bank B analog inputs or outputs. The voltage dynamic range of the converters is ±16V. The following table gives the pinout of the connector. Appendix B Interface board signal description 43 19 1 37 20 # Pin Name Description # Pin Name Description 1 CHB_00P Analog/Bank B: Channel 0 (positive) 20 CHB_00N Analog/Bank B: Channel 0 (negative) 2 CHB_01P Analog/Bank B: Channel 1 (positive) 21 CHB_01N Analog/Bank B: Channel 1 (negative) 3 CHB_02P Analog/Bank B: Channel 2 (positive) 22 CHB_02N Analog/Bank B: Channel 2 (negative) 4 CHB_03P Analog/Bank B: Channel 3 (positive) 23 CHB_03N Analog/Bank B: Channel 3 (negative) 5 CHB_04P Analog/Bank B: Channel 4 (positive) 24 CHB_04N Analog/Bank B: Channel 4 (negative) 6 CHB_05P Analog/Bank B: Channel 5 (positive) 25 CHB_05N Analog/Bank B: Channel 5 (negative) 7 CHB_06P Analog/Bank B: Channel 6 (positive) 26 CHB_06N Analog/Bank B: Channel 6 (negative) 8 CHB_07P Analog/Bank B: Channel 7 (positive) 27 CHB_07N Analog/Bank B: Channel 7 (negative) 9 CHB_08P Analog/Bank B: Channel 8 (positive) 28 CHB_08N Analog/Bank B: Channel 8 (negative) 10 CHB_09P Analog/Bank B: Channel 9 (positive) 29 CHB_09N Analog/Bank B: Channel 9 (negative) 11 CHB_10P Analog/Bank B: Channel 10(positive) 30 CHB_10N Analog/Bank B: Channel 10(negative) 12 CHB_11P Analog/Bank B: Channel 11 (positive) 31 CHB_11N Analog/Bank B: Channel 11 (negative) 13 CHB_12P Analog/Bank B: Channel 12 (positive) 32 CHB_12N Analog/Bank B: Channel 12 (negative) 14 CHB_13P Analog/Bank B: Channel 13 (positive) 33 CHB_13N Analog/Bank B: Channel 13 (negative) 15 CHB_14P Analog/Bank B: Channel 14 (positive) 34 CHB_14N Analog/Bank B: Channel 14 (negative) 16 CHB_15P CHB_15N Analog/Bank B: Channel 15 (positive) 35 17 Not connected 36 Not connected 18 Not connected 37 Not connected 19 Not connected 9. Analog/Bank B: Channel 15 (negative) I/O selector, analog bank B This jumper is used to specify the type of analog conversion module attached to either the Analog/Bank B connectors (P14/P15 or J8). Its position MUST reflect the type of the actually connected module for the system to work. If no module is attached to the Bank B connectors or if the module is known to be unused, the jumper shall be removed from this selector. A mismatch between this jumper position and the expected module ID given by the User model prevents the user model to run. 3 DAC 2 1 Appendix B ADC Position Configuration Type 1-2 An A/D converter module is attached to Analog Bank B 2-3 A D/A converter module is attached to Analog Bank B No jumper No module is attached to Analog Bank B Interface board signal description 44 10. I/O selector, analog bank B This jumper MUST have the exact same position as jumper P8. 3 DAC 2 1 Position 11. ADC Configuration Type 1-2 An A/D converter module is attached to Analog Bank B 2-3 A D/A converter module is attached to Analog Bank B No jumper No module is attached to Analog Bank B Conversion bank B analog interface This connector gives the Analog Bank B conversion module access to the input or output analog signals to/from connector J10. The user does not have access to these signals directly. 12. Conversion bank B digital interface This connector gives the Analog Bank B conversion module access to the data and control signals sent to/from the expansion headers of the ML50x board. The user does not have access to these signals directly. 13. External conversion module B interface This connector gives an external analog conversion module access to the data and control signals sent to/from the expansion headers signals related to the Analog Bank B of the ML50x board. The user does not have access to these signals directly. A 40-line flat cable enables the user to attach this connector with a passive interface (e.g. the OP5220 passive analog carrier) carrying the analog module. 14. Digital I/Os, banks A and B This connector gives access to the digital input and output signals of the User model. Two banks of 11 lines are implemented. Each bank can be configured to access inbound or outbound signals to/from the User model. All signals are digital, with positive voltage set to 3.3V. Although these digital lines can be accessed directly from the connector J9, it is recommended to attach the connector to a passive interface (e.g. the OP5210 digital passive carrier) using a 40-line flat cable. The passive carrier performs signal conditioning and decoupling between the ML50x platform and the external world. Appendix B Interface board signal description 45 1 39 # Pin Name Description 2 40 # Pin Name Description 1 A_CH00 Digital/BANK A channel 0 2 GND Ground 3 A_CH01 Digital/BANK A channel 1 4 A_CH02 Digital/BANK A channel 2 5 A_CH03 Digital/BANK A channel 3 6 A_CH04 Digital/BANK A channel 4 7 A_CH05 Digital/BANK A channel 5 8 A_CH06 Digital/BANK A channel 6 9 A_CH07 Digital/BANK A channel 7 10 A_CH08 Digital/BANK A channel 8 11 A_CH09 Digital/BANK A channel 9 12 A_CH10 Digital/BANK A channel 10 13 Not connected 14 Not connected 15 Not connected 16 Not connected 17 19 GND Not connected 18 Ground 20 B_CH00 Digital/BANK B channel 0 Not connected 21 B_CH01 Digital/BANK B channel 1 22 GND Ground 23 B_CH02 Digital/BANK B channel 2 24 GND Ground 25 B_CH03 Digital/BANK B channel 3 26 GND Ground 27 B_CH04 Digital/BANK B channel 4 28 B_CH05 Digital/BANK B channel 5 29 B_CH06 Digital/BANK B channel 6 30 GND Ground 31 B_CH07 Digital/BANK B channel 7 32 B_CH08 Digital/BANK B channel 8 33 B_CH09 Digital/BANK B channel 9 34 B_CH10 Digital/BANK B channel 10 Not connected 36 35 37 Not connected 38 39 Not connected 40 Appendix B Not connected Not connected GND Ground Interface board signal description 46 15. I/O selector, digital bank A This jumper is used to specify the direction of the digital signals (or the type of conditioning module attached to the Digital/Bank A connector if any). Its position MUST reflect the actual configuration of the board for the system to work correctly. If the Digital/Bank A signals are unused, the jumper shall be removed from this selector. A mismatch between this jumper position and the expected direction given by the User model prevents the user model to run. 3 DO 2 1 16. Position Configuration Type DI 1-2 Digital Bank A implements input channels 2-3 Digital Bank A implements output channels No jumper Digital Bank A is unused I/O selector, digital bank B This jumper is used to specify the direction of the digital signals (or the type of conditioning module attached to the Digital/Bank B connector if any). Its position MUST reflect the actual configuration of the board for the system to work correctly. If the Digital/Bank B signals are unused, the jumper shall be removed from this selector. A mismatch between this jumper position and the expected direction given by the User model prevents the user model to run. 3 DO 2 1 17. Position Configuration Type DI 1-2 Digital Bank B implements input channels 2-3 Digital Bank B implements output channels No jumper Digital Bank B is unused SPI Flash programmation JTAG connector This connector enables the programmation of the SPI flash via a JTAG download cable. The SPI Flash can hold configuration data (programming file for the FPGA) or user data. It is not recommended to use the SPI Flash to hold configuration data as no automated routine is provided with RT-XSG to manage such feature. To use the configuration data from the SPI flash for reprogrammation of the FPGA device, the user must set the configuration DIP switch SW3 accordingly (refer to the ML50x documentation). Appendix B Interface board signal description 47 18. 2 14 1 13 # Pin Name Description # Pin Name Description 1 GND Ground 2 +3V3 Supply voltage 3 GND Ground 4 TMS Test Mode Select 5 GND Ground 6 TCK Test Clock 7 GND Ground 8 TDO Test Data Input 9 GND Ground 10 TDI Test Data Output 11 GND Ground 12 Not connected 13 GND Ground 14 Not connected SPI Flash programmation JTAG connector with FPGA reprogrammation pin This connector implements the same JTAG signals as P1 with a different connector type. It is used to configure the SPI flash. Refer to the documentation of P1 for more information. In addition to JTAG standard signals, pin 1 of this connector can be used to force reprogrammation of the FPGA device, in the same way the SW5 push-button does. 1 # Pin Name Description 1 INIT 2 TMS Test Mode Select 3 TDI Test Data Input 4 TDO Test Data Output 5 TCK Test Clock 6 GND Ground 7 +3V3 Supply voltage 8 Appendix B 8 Active-low FPGA reprogrammation signal Not connected Interface board signal description 48 19. External JTAG connector The external JTAG connector enables the addition of an external device in the main JTAG chain (accessed via connector J1 of the ML50x board). If this connector is used, ML50x jumper J21 must be set to connect together pins 2 and 3, as illustrated on Figure 21. (a) (b) Figure 21:Position of the ML50x jumper J21 to enable an external device on the JTAG daisy chain. (a) The external JTAG loop is disabled [default]. (b) The external JTAG loop is enabled. Warning: The automatic programmation procedures may not work if an external device is added to the JTAG chain. Manual programmation using iMPACT will be necessary. Refer to iMPACT documentation for further details. iMPACT is a tool included in the ISE Design Suite. 2 14 1 13 # Pin Name Description # Pin Name Description 1 GND 2 +3V3 Supply voltage Ground 3 GND Ground 4 EXT_TMS External device Test Mode Select 5 GND Ground 6 EXT_TCK External device Test Clock 7 GND Ground 8 EXT_TDI External device Test Data Input 9 GND Ground 10 EXT_TDO External device Test Data Output 11 GND Ground 12 Not connected 13 GND Ground 14 Not connected Appendix B Interface board signal description 49 20. I²C bus connector I²C protocol is developed by Philips and is used to access a shared bus into the system. It can be used to access a 8-kbit EEPROM on the ML50x board in conjunction with an external controller. Refer to I²C bus protocol for more information on the implementation of the protocol. If more than one component is added on the I²C bus, each of the component must have a pull-up resistor connected to its SDA and SCL ports. 2 8 1 7 # Pin Name Description # 1 GND Ground 2 3 GND Ground 4 Pin Name Description Not connected SDA I²C bus data signal 5 GND Ground 6 SCL I²C bus clock signal 7 GND Ground 8 ExtRef External reference voltage 21. I²C bus voltage selector This jumper is used to select the reference voltage of the I²C bus. It can be set to 3.3V, 5V or to an externally sypplied voltage. IMPORTANT: the externally supplied voltage, if used, must be in the range 4.2V-5.5V. 1 2 ExtRef +3V3 +5V 5 22. 6 Position Configuration Type 1-2 External voltage ExtRef is used to pull the I²C signals 3-4 Supply voltage +3.3V is used to pull the I²C signals 5-6 Supply voltage +5V is used to pull the I²C signals No jumper Forbidden if the I²C bus is used RTSI synchronization connector The RTSI synchronization connector is used to transfer a synchronization pulse train to or from external devices. A master device, being either an external device or the ML50x platform itself, provides a pulse train to slave devices in order for the system to react synchronously with each other. Note: This feature must be handled by the user inside the User model. Implementation depends on the user needs. Appendix B Interface board signal description 50 6 # Pin 1 Description Name 1 Not connected 2 Not connected 3 Not connected 4 RTSI 5 6 23. Synchronization pulse train signal Not connected GND Ground LCD interface connector A LCD device is provided with the ML50x platform. It is used to display informations on the detected on-board conversion and conditioning I/O interfaces along with information on the firmware version and minor IDs. It also displays eventual mismatches between detected and expected conversion and conditioning I/O interfaces identification numbers. The LCD device is connected via a 14-pin flat cable to the interface board. The interface board routes the signals directly to connector J8 on the ML50x board. LCD contrast can be adjusted using the “CONTRAST” wheel (R86) on the ML50x board. 1 2 13 14 # Pin Name Description # Pin Name Description 1 DB7 LCD data bus (7) 2 DB6 LCD data bus (6) 3 DB5 LCD data bus (5) 4 DB4 LCD data bus (4) 5 DB3 Not connected 6 DB2 Not connected 7 DB1 Not connected 8 DB0 Not connected 9 E LCD Enable signal 10 RW LCD register read/!write signal 11 RS LCD register selection 12 VEE Crystal polarization voltage 13 GND Ground 14 VCC +5V supply voltage Appendix B Interface board signal description 51 24. Reconfiguration push-button (ML50x) This push-button is located directly on the ML50x board. It can be used to manually reprogram the FPGA with the configuration data. Configuration data is selected by the DIP switch SW3. Unless necessary, the user should set the SW3 to the configuration source “Slave SelectMAP” from the address “000”, as described in the Installation chapter. 25. Power supply (ML50x) These connectors are located directly on the ML50x board. The board can be powered by one of two 5V sources: P20, a 2.1 mm x 5.5 mm barrel type plug (center positive) and J15, a Personal Computer (PC) type disk drive connector. The barrel type plug connects to the 30W (5V @ 6A) power brick provided with the board while the PC disk drive connector is provided for users who want to power their board while it is installed inside a PC chassis. 26. ML50x input power switch (ML50x) This switch is located directly on the ML50x board. The power switch, SW1, turns the board on and off by controlling the 5V supply to the board. The switch can be used to force the reprogrammation of the board by turning successively the power ‘off’ and then ‘on’. Appendix B Interface board signal description 52