Journal of Information Display, Vol. 10, No. 1, March 2009 (ISSN 1598-0316)
© 2009 KIDS
A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology
Hyoungsik Nam*, Kwan Young Oh, Seon Ki Kim*, Nam Deog Kim*, and Sang Soo Kim*
Abstract
AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having
the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture
boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46” AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for miniLVDS. The measured maximum data rate per data pair is more than 800 Mbps.
Keywords : AiPi, Point-to-point, Embedded clock, Embedded control, Multi-level signalling, Variable clock level
These demands have led to the increase in the number
of interface lines in display systems due to higher data rates,
which has had negative impacts on cost, power consumption, and EMI.
In the area of system interfaces, which are the input interfaces of timing controllers, low-voltage differential signalling (LVDS) has been used. New high-speed serial interfaces such as DisplayPort™ and V-by-One™ have recently
been developed to reduce the number of interface lines [5, 6,
and 7]. DisplayPort™ specifically uses the embedded clock
scheme for efficient data transmission. It is considered an
industry-first attempt in that no other I/F scheme has used it
before in the LCD area. The main link of DisplayPort™ is
AC-coupled differential signalling, which supports up to 2.7
Gbps per lane. The link host automatically decides on the
number of lanes to be used based on the required BW (scalable link). Moreover, all the lanes carry data, which means
there is no dedicated channel for clock forwarding. The line
clock is extracted from the data stream itself that is encoded
with the ANSI-8B/10B coding rule (specified in ANSI
X3.230-1994, clause 11). The architecture of V-by-One™ is
similar to that of DisplayPort™. V-by-One™, however, can
adjust the data rate of the interface according to the input
data rate, whereas DisplayPortTM uses a fixed data rate for
any input data rate.
In the area of intra-panel interfaces, which are the interfaces between the timing controllers and the column
drivers, reduced swing differential signalling (RSDS) and
mini-low-voltage differential signalling (mini-LVDS) have
1. Introduction
LCD displays have provided end-users with outstanding performance, including marked brightness, high
contrast, a wide color gamut, and slim and light designs.
Still, display markets continue to demand more advanced
technologies such as higher resolution, higher driving frequency, and higher color bit depth.
For TV applications, some panel makers exhibited
large LCDs in 2007 with a resolution of 3,840 x 2,160
(QFHD or UD). For monitor applications, 3,200 x 2,400
(WQUXGA) displays were released in 2008. To achieve
higher motion picture quality, 120Hz driving technologies
have been applied to LCD TVs with motion estimation and
motion compensation (MEMC) algorithms [1 and 2]. These
schemes have improved motion blur characteristics, and
most panel or TV makers are adopting them. Furthermore,
because the display quality has become more important
with the increase in the display size and resolution, higherbit-depth displays have been studied [3]. Also, to adjust the
gammas of red, green, and blue pixels separately, higher bit
depths have been proposed with linear digital-to-analog
converter (DAC) column drivers [4].
Manuscript received December 10, 2008; Revised March 5, 2009; accepted
for publication March 23, 2009.
* Member, KIDS
Corresponding Author: Hyoungsik Nam
LCD Technology Center, LCD Business, Samsung Electronics Co., Ltd.
#200 Myeongam-Ri, Tangjeong-Myeon, Asan City, Choongchungnam-Do, Korea
E-mail : hyoungsik.nam@samsung.com
Tel : 041-535-5441 Fax : 041-535-4520
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Hyoungsik Nam, et al / A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology
as shown in Figure 2. The interface lines can be easily implemented on the printed circuit board (PCB), thus maintaining a 100-ohm impedance.
The number of lines between one TX and one RX is
determined according to the maximum required data rate. If
the data rate is over the maximum rate of an AiPi, more
AiPi data pairs should be implemented. For example, a
60Hz FHD needs one pair, and a 120Hz FHD requires two
pairs between one TX and one RX.
been the main interfaces in use until now [8 and 9]. As
shown in Figure 1 (a), the existing RSDS and mini-LVDS
interfaces have a multi-drop bus topology with several stubs,
which causes impedance mismatching. Because this mismatching reduces the timing margin of the transmitted and
received data due to signal reflection, high data rates can be
supported by means of the increased number of interface
lines. Furthermore, these multi-drop interfaces need separate clock and control signal lines.
To cope with this limitation, point-to-point interfaces
have recently been proposed and developed for use as the
intra-panel interface [4 and 10]. In general, a point-to-point
interface composed of one TX and one RX, as shown in
Figure 1 (b), can produce good impedance matching and a
faster data rate because there are no stubs on the interface
bus lines. The existing point-to-point interfaces forward the
clock separately, however, which can result in skew problems between the clock and data signals. At higher data
rates, the sampling window is narrower, and therefore, the
skew becomes more critical. Therefore, current point-topoint solutions require an additional complex circuitry to
adjust the phase of the sampling clock, which increases the
size and cost of the system; or alternatively, they use multiple data pairs for the point-to-point link. Moreover, existing
point-to-point interfaces require additional lines through
which to send the control signals.
This paper describes an advanced intra-panel interface
(AiPi) technology for use in LCD applications, which sends
the clock and control signals via the data lines. The key
concepts of this technology are presented in section 2, and
its implementation is explained in section 3. Section 4 deals
with additional technologies that improve the performance
of the AiPi interface. Section 5 presents the measurement
results, and section 6 concludes this paper.
2.2 Clock-embedded Data
The skew issue between the data and clock signals has
been a critical issue with respect to the previous point-topoint intra-panel interfaces, in terms of limiting the maximum data rate at the given number of interface lines. AiPi
eliminates this issue by means of the embedded clock scheme,
in which the clock signal is sent via the data line. Because
clock and data signals have the same path, there is no skew,
and therefore, an additional de-skewing circuitry is not nec-
(a) Multi-drop connection.
(b) Point-to-point connection.
Fig. 1. Bus topologies of the intra-panel interfaces.
2. Advanced Intra-panel Interface
AiPi establishes a cost-effective solution by means of a
point-to-point bus topology and an embedded clock and
control scheme.
2.1 Point-to-point Bus Topology
As explained previously, a point-to-point bus topology
has the advantage of good impedance matching, which produces a higher data rate at the given number of interface
lines. Therefore, AiPi adopts a point-to-point bus topology,
Fig. 2. Point-to-point bus topology of AiPi.
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Journal of Information Display, Vol. 10, No. 1, March 2009
last data bit in front of the clock. As shown in Figure 3, if
the last data bit is high, the clock pulse is at the Vcoh level;
and if the last data bit is low, the clock pulse is at the Vcol
level. This transition scheme guarantees that there are only
two kinds of voltage swings--from Vdoh to Vcoh and from
Vdol to Vcol, thereby reducing the jitter effect on the edges
of the clock pulses. The clock tail bit is inserted just after
the clock pulse to reduce the effect of the inter-symbol interference (ISI).
Clock pulses of high amplitude are added twice per serialized pixel data, as described in Figure 4, to reduce the
number of delay stages in the delay-locked loop (DLL). Ten
bits of red data and 4 MSBs of green data are first transmitted, after which the remaining data are sent between the
clock pulses. This embedded clock scheme also helps reduce the number of lines between the TCON and the column drivers, as there is no need for dedicated clock lines.
Fig. 3. Multi-level signalling for the embedded clock scheme.
Fig. 4. One-pixel data transmission on AiPi.
2.3 Control-embedded Data
In general, because column drivers need timing information on the beginning of each horizontal line, panel driving, and the pixel polarity, the interface of TCON to the
column drivers requires some additional lines. RSDS needs
three control signals--STH, CLK1 (or TP), and POL--which
are described in Figure 5, whereas mini-LVDS has two control signals--CLK1 and POL.
AiPi technology can generate the data stream, however,
including the control signals, without requiring additional
lines. A data-enabling (DE) signal, which follows the clock
tail bit, indicates whether or not the serialized data are image data. If the DE bit is high, the stream that follows it is
composed of pixel data; and if the DE bit is low, the blanking or control data are transferred, as shown in Figure 6.
The information on the beginning of a horizontal line is
extracted from the DE transition of 0 to 1, and the rising
edge timing and the pulse width of TP as well as the level
of POL are assigned to the first data of a low DE period, as
shown in Figure 7. Also, the column driver control signals
can be programmed separately due to the point-to-point bus
topology.
Fig. 5. Timing diagram of the control signals in RSDS.
Fig. 6. AiPi data mapping protocol.
essary. AiPi uses multi-level signalling, as shown in Figure 3.
This method can be implemented by a simple clock data recovery (CDR) circuit, which will be described in greater detail in section 3. CDR detects the signal as the clock when the
input level is higher than Vrefh or lower than Vrefl. The signal within the range of Vrefl to Vrefh is treated as data.
The clock polarity is set to follow the polarity of the
3. Implementation
3.1 AiPi Transmitter
The AiPi transmitter consists of channel drivers and a
phase-locked loop (PLL) for frequency synthesis. Figure 8
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Hyoungsik Nam, et al / A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology
Fig. 7. Control data mapping in AiPi
tion, it maintains the advantage of a low EMI emission.
shows the block diagram of the AiPi transmitter. Each
channel driver has its own serializer and driver. PLL generates two clock signals, CLKS and CLKP. CLKS and CLKP
are clock signals that are synchronized for the serial stream
and the parallel data, respectively. For example, in the typical case of a 60Hz FHD (1,920 x 1,080) with 10-bit column
drivers of 576 channel outputs, CLKS is 540 MHz, and
CLKP is 15 MHz. Using clock signals generated by PLL,
the parallel data are serialized and transmitted in an AiPi
signal format, as shown in Figure 9.
There are two drivers, the size ratio of which is 1:2.
During the data transmission, only the small driver is operated, and the large driver is turned off to reduce the power
consumption. It is turned on periodically, however, to
transmit the clock information. Two output currents are
summed up before they are transmitted. The AiPi driver has
a common mode rejection (CMR) circuit, which controls
the driver bias to keep the common mode voltage. Since the
common mode voltage does not change during the opera-
3.2 AiPi Receiver
The receiver detects multi-level signals and recovers
sampling clock and pixel data. The clock information can be
extracted from the data signals by comparing the level of the
data and the clock with the reference levels (Vrefh/Vrefl).
When the voltage level of the signals is out of the range of
Vrefh to Vrefl, the signal with the clock information is extracted; and when the voltage level of the data is between
Vrefh and Vrefl, the data are extracted.
The clock pulse that is extracted from the input stream
has half a period of one complete pixel data. For example,
the clock pulse has a duration of 18 bits in a 10-bit colordepth system. Using this pulse, a DLL generates a multiphase clock, which is used in a de-serializer (DES), as
shown in Figure 10.
Since AiPi adopts multi-level signalling, the performance of the input buffer is very important. Figure 11 shows
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Journal of Information Display, Vol. 10, No. 1, March 2009
Fig. 8. Block diagram of the AiPi TX.
Fig. 11. Input buffer block diagram.
Fig. 9. Timing diagram of the AiPi TX.
Fig. 12. Example of data and clock extraction.
the data length is 5 bits, even though the data length of an
8-bit color-depth system is 25 bits, including one DE bit.
This is a case of the transmission of two packets--101101
and 011001. The transmitted AiPi signals, IN and INB, have
different common mode voltages with reference levels. The
CMR buffer matches the common mode voltage between
the input signals and the reference levels. Using the CMR
buffer outputs, INO and INOB, the differential amplifier
recovers the clock and the data. Since the first packet has a
negative polarity and the second packet has a positive polarity, their clock pulses are generated from different amplifiers. Following this, the two clock pulses are mixed and
handed over to the DLL, which generates the CLKDLL.
Fig. 10. Block diagram of the AiPi RX.
the block diagram of an input buffer. In the front-end part of
the receiver, there is a common mode rejection circuit for
robust data and clock recovery. The output signals of the
CMR buffer have the same common mode voltage as that
of the reference voltages. Data can be extracted by simply
comparing the differential signals, and the clock can be
extracted by comparing the buffer output and the reference
voltages. To generate the clock for both data polarities,
there are two clock buffers, and they are mixed using the
OR circuit. In the example in Figure 12, it is supposed that
3.3 AiPi Column Driver
The prototype column driver was developed using 0.35um CMOS technology, based on a mini-LVDS column driver.
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Hyoungsik Nam, et al / A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology
(a) The polarity of the clock tail was the same as that of the clock.
Fig. 13. Block diagram of an AiPi column driver.
(b) The polarity of the clock tail was opposite that of the clock.
Fig. 15. Eye diagrams at the input of the column drivers.
(a) 8-bit color depth
(b) 6-bit color depth.
Fig. 14. AiPi waveforms for the 8-bit and 6-bit color depths.
It supports a 10-bit color depth and 576 outputs. The miniLVDS interface block was replaced with an AiPi block. Figure 13 shows the block diagram of an AiPi column driver.
Fig. 16. Photograph of the TCON board.
The polarities of clock pulses are fixed at high for positive AiPi signals and at low for negative AiPi signals. In
the case of the 10-bit AiPi, an AiPi RX needs four clock
buffers to detect high and low clock pulses for both positive
and negative AiPi signals. If, however, the single-ended
clock polarity is always high, only two clock buffers are
necessary, which reduces the power consumption and the
area of an AiPi RX. Especially, a 6-bit color depth needs
only one clock pulse per pixel data because of the small
number of bits in one pixel data.
4. Further Improvements
4.1 Multi-bit Color Depth Support
Up to now, there are still three main color depth applications: 6-bit, 8-bit, and 10-bit, which are common for
notebook PCs, monitors, and TVs, respectively. AiPi technology should be able to support all three applications.
Since 6-bit and 8-bit AiPi’s can have longer timing margins
than 10-bit AiPi’s, different schemes are applied to them, as
shown in Figure 14.
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Journal of Information Display, Vol. 10, No. 1, March 2009
4.2 Inter-symbol Interference
When the data rate is increased, the DE data cannot be
recovered appropriately due to an inter-symbol interference
(ISI), which limits the maximum data rate of an AiPi. To
solve this issue, the polarity of the clock tail bit is adjusted.
At low data rates, the clock tail has the same polarity as the
clock to reduce the transition voltage; and at high data rates,
the clock tail has a polarity opposite that of the clock to
reduce the ISI. Because the clock information is extracted at
the rising edge that crosses over to Vrefh and at the falling
edge that crosses over to Vrefl, the CDR performance is not
affected by the jitter caused by the polarity of the clock tail
bit. The polarity can be changed by setting the internal register of the AiPi transmitter.
Figure 15 shows the measured eye diagrams when the
polarity of the clock tail was the same as and opposite that of
the clock pulse. As explained previously, in the case of the
same polarity, the ISI component of the clock causes the deterioration of the DE bit, which results in an error. An opposite polarity, however, reduces the effect of the clock’s ISI
and helps the AiPi RX extract the correct value of the DE bit.
Fig. 17. Histogram of the measured maximum pixel frequency.
5. Measurement
The AiPi prototype was built on a 10-bit 60Hz 46”
FHD LCD. The AiPi column driver was fabricated based on
NECEL’s 0.35-um process by replacing the mini-LVDS RX
with the AiPi RX in an existing 10-bit, 576-ch mini-LVDS
column driver. Only one AiPi data pair was used in the column driver. The AiPi timing controller board is shown in
Figure 16. The total number of interface lines between the
TCON and the 10 column drivers was 20, compared to the
38 intra-panel interface lines for the mini-LVDS, as shown
in Table 1.
Recently, 720-ch and 960-ch AiPi column drivers have
been developed for 120Hz LCD panels, which produce only
64 and 48 interface lines, respectively, compared to 148
lines for mini-LVDS panels, as shown in Table 2. One AiPi
column driver makes use of two-pair AiPi interface lines.
The maximum pixel frequencies were measured over
30 column drivers, as shown in Figure 17, and the data rate
was determined using Eq. 1. These show that most column
drivers can support a pixel frequency higher than 220 MHz,
which is equivalent to a data rate higher than 800 Mbps for
one AiPi data pair. Figure 18 shows the 10-bit 46” FHD
display prototype.
Fig. 18. 10-bit 46” FHD display prototype.
(a) Mini-LVDS
(b) AiPi.
Fig. 19. EMI comparison between mini-LVDS and AiPi.
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Hyoungsik Nam, et al / A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology
Table 1. Comparison of Mini-LVDS and AiPi in a 60Hz FHD
Mini-LVDS
AiPi
Data
32 lines
20 lines
Clock
4 lines
0 lines
Control
2 lines
0 lines
Total
38 lines
20 lines
6. Conclusions
AiPi technology reduces the number of intra-panel interface lines using a point-to-point bus topology and the elimination of the clock and control signal lines. The 10-bit 46”
FHD LCD prototype reduced the interface lines between
the TCON and the column drivers to 20 lines, compared to
the 38 lines for the mini-LVDS. The measured maximum
data rate was higher than 800 Mbps, which means a pixel
clock frequency of up to 220 MHz can be supported. This
feature reduces the TCON and PCB costs, and improves the
EMI performance.
Table 2. Comparison of Mini-LVDS and AiPi in a 120Hz FHD
Mini-LVDS
AiPi
(720 ch)
AiPi
(960 ch)
Data
128 lines
64 lines
48 lines
Clock
16 lines
0 lines
0 lines
Control
4 lines
0 lines
0 lines
Total
148 lines
64 lines
48 lines
DataRateAiPi =
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[4]
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[6]
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G. Ward, SID Symposium Digest, 1046 (2007).
R. McCartney, et al., SID Symposium Digest, 1556 (2004).
T. Kim, et al., Proc IDW06, 1969 (2006).
A. Kobayashi, SID Symposium Digest, 1495 (2006).
THCV213 and THCV214: LVDS SerDes transmitter and
receiver, THCV213-THCV214 Rev1.3_E (2006).
[ 8 ] A. Lee, et al., SID Symposium Digest, 43 (2000).
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FreqPixelClock ⋅ ( BitDepth ⋅ 3 + 6)
# of Source Drivers
Eq. 1
Figure 19 shows the EMI comparison between the
mini-LVDS and AiPi with two-layer PCBs at a 60Hz FHD.
As expected, the AiPi technology, with its slim interface,
can dramatically improve the EMI performance.
※ Parts of this work were presented in Proceedings of IMID 2008
44