CSC 3210
Computer Organization
and Programming
Chapter 4
BINARY ARITHMETIC
D.M. Rasanjalee Himali
1
Outline
Introduction
Binary Numbers and Addition
Half and Full Adders
Modulus Arithmetic
Subtraction
Two’s Complement Number Branching Conditions
Unsigned Arithmetic
Unsigned Number Branching Conditions
Condition Code Test
Extended Precision Arithmetic
2
Introduction
Consider arithmetic: addition, subtraction,
multiplication, and division.
The use of two’s complement arithmetic
allows us to reduce subtraction to addition.
Multiplication is also reduced to addition, and
division is reduced to addition and subtraction.
Base two arithmetic is much simpler than
decimal arithmetic
3
Binary Numbers and Addition
Addition:
When two decimal digits are added, a sum and carry are produced.
Ex1: 7+5 produce a sum of 2 and a carry of 1.
Ex2: 3+4 produce a sum of 7 and the carry 0.
Procedure:
From right to left, we add each pair of digits
We write the sum, and add the carry to the next column on the left
0
1
1
+
0
0
1
2
Sum
1
0
0
1
Carry
0
1
1
1
9
8
+
2
6
4
Sum
4
6
0
1
Carry
4
Binary Numbers and Addition
Ex2: 377+419
First add the 9 to the 7, producing a sum of 6 and a carry of 1:
The carry of 1, left-shifted, is then added to the 1 and 7, producing a sum of 9
and a carry of 0.
The carry, left-shifted, is added to the 3 and 4 to produce a final sum of 7 with again a
0 carry and the process is complete.
5
Binary Numbers and Addition
There are four possible outcomes from the addition of two bits:
Sum bit of the addition of two bits is the exclusive or and that the carry
is simply the and of the two bits.
The process of addition may be represented in a C function as:
6
Binary Numbers and Addition
7
Binary Numbers and Addition
mov 0x45, %r1
mov 0xE7, %r2
add %r1, %r2, %r3
What values are in the registers after this?
0x45
=
0 0100 0101
0xE7
=
+ 0 1110 0111
1 0010 1100
=> 0x12C
so r1=0x45, r2=0xE7, r3=0x12C
8
Half and Full Adders
Half Adder:
The generation of the sum and carry bits may be performed by
very simple electronic circuits.
The generation of the sum and carry requires an and gate and an
xor gate. These may be obtained together in a circuit called a half
adder
9
Half and Full Adders
Full Adder:
Two half adders may then be
combined together with an or
gate to add two inputs, A and
B, with a carry in, to produce
a sum and a carry out.
Such a circuit is called a full
adder
10
Modulus Arithmetic
Modulus arithmetic considers only numbers in the range 0 <= n < M,
where M is the modulus.
A modulus operator % in C will force a number to be in the
appropriate range by performing an integer division by M and keeping
the remainder
Example: a car odometer
if a car has 99999 miles on it,
and you drive another mile,
the odometer will then read 00000
11
Modulus Arithmetic
Computers normally perform modulus arithmetic, as they have registers of
fixed size, like the car odometer
If we have an n-bit register and count up from 0, then when the number
reaches 2n - 1 (represented by all ones), the next increment returns the register
to all zeros.
A carry out of the MSB (most significant bit) has been lost.
12
Subtraction
Addition is fairly simple.
But, subtraction requires borrowing if the digit you are subtracting exceeds the
digit from which it is to be subtracted.
However, a neat hack can avoid these borrowing problems.
Consider the following expression with arithmetic performed modulus r where r
is the base and n the number of digits:
The addition of rn does not affect the result of the calculation, as the arithmetic
is performed modulus r
The subtraction of b from rn - 1 is simple and involves no borrowing.
Ex: decimal arithmetic r =10 and 2 digit registern=2
23-07 = 23+(102-1-07)+1 = 23+(99-07)+1 = 23+92+1 = 23+93 = 16
13
Complement Arithmetic
rn-1-b is called the diminished radix complement
“nine’s complement” if r=10
“one’s complement” if r=2
rn-1-b+1 is called the radix complement
“ten’s complement” if r=10
“two’s complement” if r=2
14
Subtraction
In binary, finding the one’s complement and the two’s complement are easy
One’s complement:
Replace every 0 with a 1,
and replace every 1 with a 0
Two’s complement:
Find the one’s complement,
and add 1
List all the four-bit two’s complement numbers:
15
Subtraction
Number Ranges:
A
signed number has the range
-2n-1 to 2n-1 –1
An
unsigned number has the range
0 to 2n -1
What
is the range of a SPARC register?
-2,147,483,648 to 2,147,483,647 (signed)
0 to 4,294,967,295 (unsigned)
16
Subtraction
The two’s complement system is an interpretation of negative
numbers in registers;
Hardware always performs binary addition.
To subtract, form the two’s complement of the number and then add;
There is then no need for a hardware subtractor
Ex: 4-2 = 4 +(-2)
17
Two’s Complement Number Branching
Conditions
Signed arithmetic branches are the appropriate branches when we are
interpreting the numbers in the machine as two’s complement
Branching conditions are based on the setting of the N (negative), Z (zero), and
V (overflow) bits.
The Z bit is set when all the bits of the result are zero.
The N bit is set when the most significant bit is 1.
The overflow V bit is set when the register is not long enough to hold the true
representation of the number
The conditions for signed branches are:
18
Two’s Complement Number Branching
Conditions
Shifting:
Three shift instructions are provided in the SPARC architecture to
compute the contents of a register shifted left or right by a number of
shifts.
There are two shifts, arithmetic and logical.
Arithmetic Shift:
Logical right shift:
Right Shift (sra)- sign bit is copied into the MSB position.
(srl)- zeros are copied into the most significant bit position.
Left shifts:
(sll)- identical in both cases with zeros shifted in from the right
19
Two’s Complement Number Branching Conditions
The shift instructions are as follows:
Shift count is low five bits of regrs2 or low five bits of the immediate
Thus largest shift possible is 25-1 or 31
Shifting a number left corresponds to multiplication by 2;
Shifting right arithmetic corresponds to division by 2.
Ex: o11)2 sll by 1 110)2
20
Unsigned Arithmetic
Number representations are always considered positive
Numbers have a range of 2n-1, twice that of signed numbers.
There is a set of unsigned branch instructions that makes the following
tests:
21
Condition Code Tests
There is also a set of branches that tests the
individual condition codes:
22
Question:
What would be the signed decimal
number in %o0 after executing these
instructions?
mov
sll
sra
not
inc
6, %o0
%o0, 30, %o0
%o0, 25, %o0
%o0
%o0
23
Answer:
mov 6, %o0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
30
sll %o0, 30, %o0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25
sra %o0, 25, %o0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
not %o0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
+1
Inc %o0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
%o0 = 64
24
Extended Precision
What if we need to work with data that are more than 32
bits wide?
Ex:
integer arithmetic with 96 bits numbers
Solution:
Store a 96-bit number in 3 sequential registers with MSB in
lowest of 3 registers.
Ex: if we store 96-bit number in %l0, %l1, %l2, sign bit would be
bit 31 of %l0 and LSB in 96-bit number would be bit 0 of %l2
25
Addition of Extended Precision
Numbers
There is no machine instruction to add three register
numbers;
Instead, we have to proceed by
adding the two low registers of both numbers, bits 0-31,
then adding the two registers containing bits 32-63, along with any
carry that was generated when the two low registers were added.
Finally, we add the two high registers containing bits 64-95 along
with any carry generated when the mid registers were added.
26
Addition of Extended Precision
Numbers
There is a machine instruction especially for this purpose that adds the
contents of two registers together plus one if the C, carry, bit is set.
A carry from the previous add will set the carry bit:
addx
addxcc
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
These mean:
regrd =regrs1 + reg_or_imm + C
Ex: suppose first number is in %l0-%l2, secon number is in %l3-%l5.
the result goes to %o0-%o2:
27
Subtraction of Extended Precision
Numbers
On subtraction we need to form the two’s complement of one of the
multiregister numbers.
We could do this by first forming the one’s complement of each
register, and then add one to the low register (propagating any carry).
We would then add the numbers as before:
28
Subtraction of Extended Precision
Numbers
We can reduce above to three instructions using
following extended precision instructions:
these mean:
subx
regrs1, reg_or_imm, regrd
subxcc regrs1, reg_or_imm, regrd
regrd =regrs1 - reg_or_imm – C
Ex:
29