Boston University
SC571: VLSI Design Principles
Electrical and Computer Engineering
Lab #2: Physical Design using Cadence
Due: 2/22/02
GOAL: The goal of this lab assignment is to introduce schematic capture, physical layout, and
simulation using the Cadence CAD tool suite.
DESIGN: Design a 1-bit adder circuit using fully complementary CMOS techniques. Hint:
designing with a basic CMOS NAND approach will allow repetitive use of a basic layout and
may save you work (and time) in the long run. You are going to use the tsmc025 (0.30 um)
technology library and transistor models for this design. (See the Cadence tutorial for the
procedure for selecting the technology library and model files.)
IMPLEMENTATION: Use Cadence Composer to build up your circuit schematic, starting
with individual basic circuit types, then defining symbols for the basic circuit building blocks
(e.g. inverter, 2-NAND, 3-NAND, etc.), and using these symbols to construct your complete
adder schematic. After the adder is constructed, simulate it in Analog Artist using the tsmc025
CMOS transistor models. Print out hard copies of your circuits, symbols, and output waveforms.
After completing the schematic simulation, layout the circuit using Virtuoso, perform design rule
checking (DRC), and do the logic versus schematic (LVS) check. Remember that once you have
completed a basic circuit layout and checked it with DRC, you can replicate it for all uses of the
same exact circuit! Optional: After successfully executing LVS on the completed adder circuit,
you may decide to extract a circuit model based on the layout and redo the simulation in Analog
Artist. (This last part is not required in Lab 2, but will become part of later labs.)
The physical design must meet all design rule constraints with no errors. Design for an N-well
process, meaning that you need to put all PFET’s within an N-well. NFET’s will be built
directly in the P substrate. Use numerous N-well contacts to Vdd (N+ contacts in N-wells) and
substrate contacts to Vss (P+ contacts in P substrate) so that no transistor is more than one square
away from a substrate or well contact. Make all NFET transistors with minimum L=0.3 um, and
W=1 um and make all PFET transistors with L=0.30 um and W=2 um. Try to use circuits
designed to be repetitive in order to save design layout effort. Attempt to come up with a
reasonably dense design layout. The GTF will put will put some qualitative value judgment on
the compactness of your design. We are using the MOSIS layout design rules with lambda=0.15
which will give minimum images of 0.3 um.
SIMULATION: As mentioned, verify the logic functionality and measure the circuit delay
using an Analog Artist transient simulation. Put a 200 fF load on all outputs (both SUM and
CARRY). Define input pulse voltage sources for A, B, and Cin with all logic combinations
included in the waveforms, using risetimes and falltimes of 0.1 ns, pulse cycle times of 5 ns, and
high/low values of 5V/0V. Assume Vdd = 5 volts.
OUTPUT: Demo your simulation results and layout to the GTF. In addition, make copies of
appropriate results for your report, as described below.
WRITEUP: Your writeup will be a hard copy report comprised of printed copies of your
individual basic circuits, circuit symbols, overall circuit schematic, simulation waveforms, and
layout. In addition, report the size of your physical implementation in um2. Indicate the delay
time for your circuit to evaluate to 90% of its final value for every input combination. The area x
delay is a sort of figure of merit which you will want to try to minimize.
TUTORIALS: (How to learn Cadence Composer, DRC, Virtuoso, LVS, Extract, and Analog
Artist?) First, try building a simple inverter using the Cadence tutorial, as covered in class.
After you feel confident in the use of all the Cadence tools, then follow a similar procedure to
build your 1-bit adder circuit. It’s not hard once you spend some time to “come up the learning
curve”!
HINTS FOR LEAF CELL LAYOUT STRATEGY:
1. Lay out leaf cells so that they are rectangular. This way they can be placed together in an
array and line up with each other, minimizing waste of space for interconnect.
2. Run Vdd and Vss (GND) in straight metal lines running to the edges of the layout rectangle.
When the cells line up against each other, the power and ground will be automatically
connected and passed on to the next cell.
3. Whenever possible, lay out cells so that they pack together using copies, rotations, and/or
mirroring. With a CAD tool, the geometric transformation can be used to create a copy of
the original cell with a rotation or mirrored image, which may aid in cell placement in an
array. For example, a RAM can be constructed easily in this manner.
4. Wires that pass through a cell should be straight. This applies to all wires that come in one
side of the cell and go out the other, like Vdd, GND, clocks, etc.
5. Run data lines in one direction (N/S) and control lines in the orthogonal direction (E/W).
This way the control goes to each cell while the data goes in the top and comes out the
bottom, for example.
6. Diffusion paths from Vdd to GND should be as straight as possible. Diffusion paths have
higher resistance, and minimizing resistance in a path is the goal, so straighter, shorter lines
have least resistance.
7. Choose ahead of time those signals that are to be routed in metal so that they run parallel to
Vdd and GND. These are the control lines that will be passed to every single cell. Plan and
layout these lines first since adding them in at the end is difficult.
8. Use Vdd/GND “cycles” (by using mirroring). In other words, layout the design so that two
cells connected to the bottom could share a rail for either Vdd or GND, and have the other
power line at the opposite end.
MOSIS Rules and Other Helpful Information:
MOSIS are CMOS design rules. The rules mandate specific physical requirements in layout of
the masks in CMOS design, namely POLY, NDIFF, PDIFF, METAL1, METAL2, and the cuts
used to connect layers together. All units are in lambda, which means that the rules are (in
theory) scalable to any size just by changing technology and lambda.
The rules are separated in 11 major areas. These are WELL (Nwell or Pwell), ACTIVE (Ndiff
and Pdiff), POLY, SELECT (N Select and P Select), CONNECT TO POLY (simple and dense
cut to poly), CONNECT TO ACTIVE (cuts to Ndiff and Pdiff), METAL1, VIA (to connect
from metal1 to metal2), METAL2, OVERGLASS, and EXPERIMENTAL.
Each area has subsections defining each rule that can apply to that mask level. Each subsection
has a name (width, for example) and a number (lambda) for that rule. Pictures in the MOSIS
manual serve to clarify rules; each is labeled with the design rule.
For example, area 2 is ACTIVE. The rule defining minimal width of a piece of ACTIVE is 2.1
(= 3 lambda). This means that when making a piece of active, it must be at least 3 lambdas
across in each dimension. The rule defining minimal spacing between 2 pieces of active is 2.2
(= 3 lambda). This means that when two pieces of active are near each other, there must be at
least 3 lambdas of space between them. The rule defining the minimal distance between active
and the well edge is 2.3 (= 5 lambda), which means that there must be at least 5 lambdas of
Well beyond any piece of active.
Another example is area 3 POLY. The rule defining minimal width of a piece of POLY is 3.1
(width = 2 lambda). Again, this means that a piece of poly must be at least 2 lambdas in each
dimension to pass. Rule 3.2 (space = 2 lambda) is the minimal space allowed between two
pieces of poly. Rule 3.3 (gate overlap of active = 2 lambda) is the minimal amount that the
gate poly must overlap past a piece of active. Rule 3.4 (active overlap of gate = 3 lambda) is
the minimal amount of active that must overlap a piece of poly. Rule 3.5 (field poly to active =
1 lambda) is the minimal distance between a piece of poly and active that are not forming a
gate.
It is easy to confuse these rules and get overwhelmed with the number of constraints placed
upon you as you design. But, once you use the design rule checker a few times and learn how
to read the manual with the pictures, you will find that it is easy to follow the rules and simply
to realize mistakes.
R. W. Knepper/A. E. Hubbard
February 11, 2002