Signal Integrity (SI) Overview
Reference: Eric Bogatin; Signal Integrity Simplified, Prentice-Hall.

Frequency increases:

Signal integrity (SI) problems get worse.

Physical and mechanical designs can affect SI.

Design cycle shortens.

Need to identify and eliminate SI problems at the early design stage.

We need to understand the basic principles of SI.

At low frequencies (< 10 MHz), interconnects are transparent to the signal.

High-frequency/high-speed regime (> 100 MHz) or t r
< 1 ns – Interconnects are no longer transparent to the signal.

SI: All the problems arise in high-speed (HS) products due to interconnects.

Timing

Noise

Electromagnetic interference (EMI)

Timing: SI affects the timing budget. We will deal with it later.

Noise: Ringing, ground bounce, reflection, cross-talk, switching noise, power bounce, attenuation, capacitive loading, …

All of the above are related to one of the 4 sources:

Signal quality on a single net

Cross-talk between nets

Rail collapse in the power and ground plane

EMI

These effects occur in all scales: from on-chip wires to I/O and peripheral.

SI on a single-net:

Both the signal-path and return-path must be considered.

Constant impedance (Z): Signal is undistorted.

Z-discontinuity will lead to signal distortion.

Z-discontinuities are usually unavoidable in a PCB environment.

Line-width change
 Layer change

Return-path gap

Connector

 Branch, tee, stub, …

End of a net (most common: Hi-Z load or lo-Z driver)

Three strategies:

Controlled Z (uniform transmission line). This should be done all the way down to the chip package level. If the chip package does not use controlled-Z then it is important to keep the leads as short as possible.

Use special routing rules (such as daisy chain) to maintain constant
Z down the trace.

Add discrete components (such as resistors) to match the Zs.

SI problem due to reflections gets worse as the rise time of the signal decreases.

SI due to X-talk between nets:

Signals can travel between separate nets via capacitive and/or inductive coupling.

Near-end and far-end coupling can have different effects.
 Key to reduce X-talk: Uniform return plane.

Controlled-Z with uniform return-path: Capacitive and inductive coupling effects are comparable.

If the return-path is shared by multiple signals, X-talk is usually severe and inductive effect will dominate.

Understanding the nature of the capacitive and inductive coupling effects allows us to optimize the physical design to minimize X-talk.

Increase spacing between nets.

Use low-

materials.

Keep interconnects short.

Decrease the gap between the trace and the ground plane (thin dielectric).

Rail collapse noise: Power/ground distribution network, which feeds every chip in the PCB.

As devices switch between logic states the transient current demand may cause the supply voltage to drop temporary. This will strive other chips in the supply net. Severe problems may result even if this effect may only last a short mount of time.

In HS systems higher currents are switched at higher rates and the supply voltages are usually lower.

Rail collapse becomes a significant problem.


A low-Z power distribution system (PDS) can mitigate this problem.

Decrease the spacing between the power and ground plane (thin dielectric).

Low-inductance decoupling capacitors

Multiple, short power/ground leads

On-chip decoupling capacitors

New technology: Ultra-thin, high-

substrate can reduce power /ground problems.

EMI: PCB frequency may have harmonics that are within the common communication bands.

EMI gets worse as frequency increases.

Common-mode:
 f

Differential-mode:
 f
2

Three components: Noise source – pathway – antenna

Sources: Usually come from power/ground nets.

Shielding will help.

Cables and connectors will leak EMI even with a good shield and they act as good antennas.

Ferrite bead can suppress rf noise.

Shielded cables will minimize leaking.
 Low-Z connectors will also help.

As frequency increases, EMI can leak through smaller openings (shorter wavelengths).

Two generalizations about SI problems

Rise/fall (transition) time: dv/dt
 Impedance

At high clock frequencies transition times must decrease. In general, they are about 1/(10 F).

Simulation: Predict performances at circuit/component/field level using numerical techniques.

EM simulators: Solve Maxwell equations to predict the electromagnetic fields in and around the unit – Expensive, time/resources consuming, and difficult to use.
 Circuit simulators: (SPICE, NEC, …) Predict I and V around the circuit based on component models and circuits laws (Ohm’s law, KCL/KVL,
Thevenin theorem, …).


Component models:

Analytical models: Based on the actual component characteristics and mathematical approximations. This model gives the best result and is easier to use. However, since it is directly related to the design and fabrication of the actual devices, companies are usually reluctant to provide such information.
 Behavioral models: Based on the V-I and V-t characteristics of the components. This model runs faster and companies are usually more willingly to provide such information since it does not reveal any proprietary information.

In addition to the component models, interconnect models are needed to simulate the circuit response at high-speed.

Accuracy is the main concern for both models: Device-to-device variations, version-to-version variations, …

Measurements: Validate design/simulation and create device models.

Scalar/vector measurements

Time/frequency domain measurements

Speed of Electrons vs. Speed of Signal Transmission
Reference: Eric Bogatin; Signal Integrity Simplified, Prentice-Hall (Section 7.4, P. 210).

False intuition: In a transmission line the speed signal depends on the speed of electrons traveling down the wire.

Truth: The signal speed is about several billion times of the speed of the electrons.

We can estimate the speed of an electron in a copper wire with a diameter of 1 mm and carrying 1 Amp of current.

Sine

I =

Q
  t = q n A v
 t
  t v = I

( q n A ) where v is the electron speed,
I is the current, q is the charge of one electron = 1.6

10
-19
Coulombs, n is the free electron density in copper

10
-19
/m
3
A is the cross-sectional area of the wire

10
-6
m
2
.
 v

1 cm/sec

The speed of signal transmission is usually less than but in the same order of magnitude of the speed of light c (

12 inches/ns).
 v sgl

12 /
 r
1/2
(inches/ns) for other non-magnetic materials.

For example, a commonly used substrate material FR4 has an
 r
1/2 of approximately 4 and thus the speed of signal transmission is about 50 % of c (

6 inches/ns).

In summary, signals travel at several inches per nanoseconds while free electrons travel less than an inch per second.

The speed of signal transmission an a transmission line can also be computed from the line parameters: v sgl
= ( L C )
-1/2 where L is inductance and C is the capacitance of the line.

Since Z
0
= ( L / C )
1/2
, We can also use: v sgl
= 1 / ( C Z
0
) = Z
0
/ L .

Now we can see that the speed of free electrons has almost nothing to do with the speed of signal transmission. As a result, the resistance of an interconnect is almost irrelevant when the speed of signal transmission is considered.

On the other hand, resistance plays an important role in the loss of signal amplitudes.

Transmission Lines and Characteristic Impedance
Reference: Eric Bogatin; Signal Integrity Simplified, Prentice-Hall (Chapter 7).

Spatial extent of the transition edge of a pulse (p. 215): d = t r
 v . For example, the leading edge of a pulse with a rise time of 1 ns traveling at 6 inches/ns has a spatial extent of 6 inches.

The characteristic impedance Z
0
of a line is:
Z
0
= ( L / C )
1/2
= 1/ C v = 83 (
 r
)
1/2
/ C , where C is the capacitance per unit length (pF/inch).

Now we can discuss Z
0
in terms of capacitance only:
 Increase the width of the signal trace will increase C

Decrease Z
0
.

Increase the spacing between the signal trace and the return plane will decrease C

Increase Z
0
.

Typical Z
0

Commonly used coaxial cables (with BNC or SMA connectors) have Z
0

50

(RG174, RG58), 75

(RG59), or 93

(RG62).

TV antenna cables have Z
0

75

(VHF-coaxial) or 300

(UHF-parallel pairs).

Twisted pairs have Z
0

100-300

.

Free space has Z
0

377

.

In general we want Z
0
to be low for H-S systems especially for the power/ground paths. Low Z
0
lines usually have better field confinement, which lead to less cross talk. The problem with low Z
0
lines is the power and voltage handling capability since the smaller spacing between the signal and return plane will decrease the breaking threshold.

At frequencies above 1 GHz, 50-

lines are the most popular choice since it represents a balance among different factors such as the ones discussed above (+ many others). It is a somewhat arbitrary standard.