Phone Call 5/22/2002, 11 AM - 12:30
Attendees
Bruce Wile, IBM (bwile@us.ibm.com) (original author of this document )
Steve Levitan, UPitt (steve@ee.pitt.edu)
Jason Boles, UPitt ( jmbst115@pitt.edu ) (notes/updates in blue)
Vijay Narayanan, PennState (vijay@cse.psu.edu)
John Goss, NCSU & IBM (gossman@us.ibm.com)
Janick Bergeron, Qualis (janick@bergeron.com)
Yaron Wolfsthal, IBM (wolfstal@il.ibm.com)
Matthew Morley, Verisity (matthew@verisity.com)
Faisal Haque, Cisco (fhaque@cisco.com)
Janick - power point is fine, notes overview is ok first. gets 15 miutes for each of his
sections he will be landing at 9 PM in New Orleans (Jun 8th)
Janick departs to catch flight.
Dress code - business casual
workshop is noon to 5:15. (sun Jun 9th) lunch at noon, Bruce to give introduction at 1.
Number pre-registered - 60
Q for Steve - what are their backgrounds? Industry, Universities, etc?
A: (later) Looked like mostly Universities, but will forward the group an
attendance list as soon as he can get one.
What instructors are concerned about:
Course outline SW info - What's the sw? Where? Support?
Add slide to show how to get licenses for the tools
Vijay - add list of other tools in the industry. Bruce will acknowledge others in
introduction s.t. it's not biased to Verisity, etc.
Web site updates - Vijay to coordinate
Statement that website is to be used for university education and not for industry's
internal training. For industry access (based on contributions), contact SteveL.
John's videos
ohe has the notes, but didn't follow up yet.
PSU, Pitt, and NCSU slides.
Goss Sections: Intro, tools, verification plans, randomization, regressions, coverage,
behavioral models, Rulebase, HVLs, stimulus vs. checking,
Vijay Q: Can I get a copy of the syllabus used in internal training ?
A: (multiple respondants) Yes, outlines of 3 day courses, syllabi, Sugar & FOCS
training course outlines, verisity public documents, IBM syllabus, NCSU syllabus, Pitt
syllabus.
Jason: provide scripts used for TA's to Vijay for website.
Need handouts, but not lots:
Web site pointers
Book titles and publishers
odo have these
contacts
Handouts
Vijay - put pointer to the web page (pdf)
intro slides, speaker contact info, blank sheets for notes.
b&w
All presentations for the workshop should be laptop!
all powerpoint
1 laptop - bruce volunteer, 2 backups
email Bruce before 6/5 (burn CD)
Intro?.Bruce
There's a science and methodology
There's an industry that dependent on it
Verification career path and lack of VE's
Resources and trailblazers at universities
Workshop goals
(Recognition for all slides should be maintained)
Web site picture and very quick overview
Textbook overviews:
Janick (30 min) & Faisal(15)?Focus on the philosophy, methodology, testbenches &
testplans. Language issues were not used in the course (VHDL/Verilog & VERA).
Examples in the text.
Janick's extra 15 minutes to focus on industry perspective
Q: Janick?.15 minutes of verification industry overview & Guild.
Course Organization:
Lab driven or lecture driven course?.PSU, Pitt as Lab driven. NCSU is lecture
driven.
Weeks in the semester?lab time vs. class time (total hours)
Need to have a TA or lab exercises will not work out?
Define the TA role?compiled code and answers for labs
Exams?mid-terms and finals (PSU and NCSU), all lab base in Pitt
Message boards for lab questions
Unix or Linux
Access to slides
Simulation engine
Methods used on each lab - first lab may be done using HDL as deterministic
testbenches, etc.
Lab experience: how many bugs were found (average); how long each lab took;
how many people worked on each team in lab3.
Genbuf lab experience (Steve to create a slide)
Divide talks between: Course Org(Vijay), mechanics of sw(Steve) , mechanics of the
labs(John)-mechanics of the labs section will be moved to after the lab description.
Schedule a telecon to iron out details.
Labs:
Caveat about specs?.it's not good to give students full spec because it's not realistic
and because a perfect spec writes its own testplan.
VHDL source code has been used and abused?it's good. Verilog has not been put
through the ropes?.but if your students aren't even going to see the HDL, then use
the VHDL.
Add spattering of bug descriptions after each calc explanation and why these are
typical bugs (typos, bad algorithms)
Slide at the end requesting further designs?.
Automated Testcase Gen:
Q: Verisity - Can the Verisity related University slides be shown and distributed on
the web-site?
oA: yes
Q: Verisity: Same deal for all universities as done for PSU and Pitt? Need to state
the deal at the workshop
oA: absolutely
Q: Verisity: Can we re-evaluate the verification advisor decision?
oA: " Vault " should be ok, but will double check
What does an automated trestbench do? Not "e", but general.
How e is used to solve this problem.
Statement that other tools (VERA, etc) are in this space as well.
How much automated testbenches speed up productivity (real data available on this?
oA: hard data ? may generate debate. very specific to customers'
setup/maturity. not much attention going to be paid here. John to make
comment.
Matthew - reactive tests/verification ?
Formal Verification:
How FV attacks the problem
Where FV fits into the industry usage (designer sim vs. chip level)
Typical kinds of bugs found using FV
How Sugar and Rulebase work
Don't hit on CTL and the history
focused on model checking.
workshop on what formal verification is, but emphasis on how to teach it.
Vijay - essence of the technique
Yaron- how much to cover the underlying algorithms ? not much emphasis in an
undergrad course.
languages / concepts
property specification
Vijay - check for overlap between presentations
Q : need intermediate revision of slides ?
A: no
Q: keep meeting this Friday?
A: no, cancel.
--end notes