Design Engineering Layout Guidelines
PCBxxxx Board Layout Guidelines
PN: xxxxxx-xxxx Rev XX
Revision 1.0
Author: Designer
Email: xxx@xxx.com
Tel: (xxx) xxx-xxxx
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Design Engineering Layout Guidelines
1 Introduction
This document provides a detailed layout (Placement and Routing) instructions to the PCB designer. It complements
the design schematic and netlist.
Schematic: xxx-xxxxxx-xxxx
Design is for: Reference / Test / High Volume Manufacturing (Pick One)
Make from PCB PN: xxxxxx-xxxx Rev xx, re-use circuits listed in Placement section
In-Circuit-Test Required: Yes/No (Pick one)
2 PCB Layer Stackup (Ex: Screen Shot from Schematic PDF)
Provide proposed stackup or attach requested stackup from Board Fab Vendor.
Provide Material requirements or attach requested stackup from Board Fab Vendor
Attach Stackup Link here:
Ex.
2.1 Controlled Impedance
All signals requiring Controlled Impedance should be placed in Rule Classes per the document located at:
(add your corporate internal Constraints Naming Convention document here)
Traces must be routed per the Table and Requirements below:
Single Ended: 57 ohms, XX ohms, …
Differential : 100 ohms, XXX ohms, …
Broadside: If required…
Co-plannar: If required…
Layer
TOP
INNER-1
INNER-2
BOTTOM
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57 ohms single ended
Trace width
Minimum
(W)
Spacing between
Traces
5 mils
15 mils
5 mils
15 mils
5 mils
15 mils
5mils
15 mils
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Trace width
(W)
6 mils
N/A
N/A
6 mils
100 ohms differential
Exact Spacing
Minimum
within a pair
Spacing between
pairs
10 mils
18.0 mils
N/A
N/A
N/A
N/A
10 mils
18.0 mils
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Design Engineering Layout Guidelines
3 Board Outline (Ex: Previous Design Screen Shot)
Please provide overall Mechanical dimension requirements for proposed PCB size, and critical mounting hole
locations
OR
Provide a DXF, IDF, or STEP File for input, OR
Reference PCB PN per Section 1
Attach Board Outline information here:
Ex.
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4 Placement (Ex: Visio Screen Shot)
Please refer to the attached drawing for general placement of major components. Also, mark any Critical component
or Circuit placements (Groups and/or Rooms) and dimension them to Pin 1 or the Center of the component.
Single Sided Assembly: Yes/No (Pick One)
Attach Placement Sketch here:
Ex.
4.1 Placement Keepouts
Please refer to the attached drawing for Keepout placement restrictions.
Max Height Primary Side Components: X.XXX
Max Height Secondary Side Components: X.XXX
4.2 Re-Use Circuits
Please provide information on circuits that can be copied from previous designs. Reference the PCB PN and a
series of reference designators when possible.
Ex.
Please use TX and RX circuits found in PN: xxxxxx-xxxx Rev XX, Ref: U100 and U200.
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5 Routing Constraints: Default Rules Class
Add new sub-sections for extra Classes as necessary. Examples are shown, modify as necessary…
All traces (except the differential pairs) on the board should be routed to have 57 ohms single ended impedance.
All traces on the board should have minimum of 3W spacing outlined in Controlled Impedance Section.
All traces on-board should be routed with the shortest trace possible. Nets should have minimum vias. The following
sections describe specific rules for the different interfaces on board.
All Rules after this section are specific Class Constraints and should be adhered to per their requirements.
5.1 Ethernet Differential pairs
TRD1_M3/TRD1_P3
TRD1_M2/TRD1_P2
TRD1_M1/TRD1_P1
TRD1_M0/TRD1_P0
TRD2_M3/TRD2_P3
TRD2_M2/TRD2_P2
TRD2_M1/TRD2_P1
TRD2_M0/TRD2_P0
1.
2.
3.
Must have a 100-ohms differential impedance routed on TOP or BOTTOM layer only.
Signals within a pair (i.e. TRDP and TRDM) should have a matched length with a +/- 0.050” tolerance. A
maximum of 0.5” total length difference between the two pairs is allowed.
Place the termination Resistors and Capacitors for TRDx signals close to U300.
5.2 PCI-E Differential pairs
PE_RXP0 / PE_RXN0
PE_RXP1 / PE_RXN1
PE_RXP2 / PE_RXN2
PE_RXP3 / PE_RXN3
PE_TXP0 / PE_TXN0
PE_TXP1 / PE_TXN1
PE_TXP2 / PE_TXN2
PE_TXP3 / PE_TXN3
PE_TP0 / PE_TN0
PE_TP1 / PE_TN1
PE_TP2 / PE_TN2
PE_TP3 / PE_TN3
PE_REFCLKP / PE_REFCLKN
1.
2.
3.
4.
Must have a 100-ohms differential impedance routed on TOP or BOTTOM layer only.
The Maximum allowed length for these signals is 2.5”.
Signals within a pair (i.e. PE_TXP and PE_TXN) should have a matched length with a +/- 0.005”
tolerance.
PE_TXx pairs should be matched within 0.2”. PE_RXx pairs should be matched within 0.2”.
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5.3 Power Nets: Routed or Small Fill Planes
The following are power planes/islands on the board:
V33_1
V25
V12
The following are filter power nets and require copper pours or at least 30mil trace width where copper
pour is not possible, place filter components (on page 4 of schematics) close to U300 :
DLL_VDD
EPBPLL_VDD
GPHY_PLLVDD
BCM_GPHYPLLVDD
PCIE_PLLVDD
5.4 Other Net Classes: IE. DDR, EBI, USB, etc (add as Required)
DDR
EBI
USB
6 Power planes

There is one dedicated power plane: Layer 5. Power plane should retract 0.100” from the digital ground
plane edges.
7 Ground planes

Ground plane should not have any cutout.
8 Current Requirements
Netname
XXX
XXX
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Current Amps @ 10 deg C
Current (Amp)
Minimum Trace Width
Internal/External
1.0
2.5
XXX mils / XXX mils
XXX mils / XXX mils
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9 Decoupling / Filter Placement and Connection






Please refer to items above and to the schematic to identify the decoupling capacitors placement
Decoupling capacitors must be placed as close as possible to the power pin/ball of the component
Trace from power pin/ball to capacitor pad and to power plane must be as short as possible and 0.020”
wide.
Decoupling capacitors’ connection to ground should be very short. Do not attempt to share ground vias by
routing long traces of ground
Decoupling capacitors under “Power Decoupling Grid” section in the schematic on sheet-5 must be placed
last on the board and should be distributed all over the board with about an inch spacing between them to
create a grid of decoupling on the board.
Please do not change the pre-via_fanout foot prints without consulting the engineer on a case-by-case basis.
10 EMI Requirements
Via Stitching required for Signal Nets: (Add Nets Here)
Special Clearances required: (Add Nets Here)
11 Additional Silkscreen Requirements
Add the Corporate logo/board-info in the corner of the board on silkscreen top per PCB guidelines.
Crowded Reference Designations can be moved to another layer: Yes / No (Pick One)
Please provide Additional Silkscreen markings as listed on Schematic or attached information:
12 Solder Mask / Gold Mask / Board Finish
Board Finish is Immersion Silver (Standard)
Solder Mask Color: Green (Standard)
Secondary Gold Mask Required for Socket Board
13 Otherwise Specified
Additional Items not covered in the previous sections:
Ex.
Through Hole Via-In-Pad is acceptable
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14 Schematic Design Review
-
Have all CLOCK nets been suffixed with “_CLK”
Have all Diff Pair nets been suffixed with “_P” and “_N”
If rules were added to the schematic, were they added per the Constraints Naming Convention
Have all Critical Nets, requiring constraints, been given a Specific Netname
Have all Single Pin Nets been removed from the schematic
Have all Additional BOM (Non-Electrical) Items been added to the schematic from the Library to
facilitate the PLM BOM Upload
Have all CRITICAL parts been checked for proper attributes prior to BOM Upload
Have you verified a Clean (No Errors) Packager/Netlister run
Have all Local schematic symbols been updated from the Central Library
Has the Design been verified to the Central Library and verified for ALL Green Lights
Has the Native schematic design file been sent to the PCB Layout Manager for Verification
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