AGATA LLP
Digitiser
Digitiser specifications draft 2
Modified after Agata Week Legnaro 15/19 September
AGATA
DIGITISER
DRAFT 2.0
Fig1 Cluster of Digitisers
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Digitiser
Digitiser specifications draft 2
Modified after Agata Week Legnaro 15/19 September
A) INTRODUCTION
This document has been written following discussions in Munich ( June 2003 ) and with the
Preamplifier Team and the Detector Team and after the Agata Week in Legnaro 15/19
September. Some parts have been already discussed for the Agata Testbed electronics
specifications draft 3.
The objective is to create the best design ensuring good quality of the data to be sent to the
preprocessing card, and enabling easy maintainability of the system during the experiment
and in an electronics workshop.
In an annex, I will present a short background section about FADCs and some realistic
performance expectations.
B) OVERVIEW OF THE DIGITISER
1) System description
The principal goal of the digitiser card is to make the interface between the detectors and the
preprocessing module.
The Digitiser will do the following:
o
o
o
o
o
Receive the signals from 1 crystal, ( 36 segments + 1 core ).
Digitise the input signals at a rate of either 80 or 100 MHz, with 14 bits ADCs.
Send the signals coded by optical fibre by group of 6 or 12 ( to be defined ).
Provide spare channels and inspection lines for maintainability.
Provide an interface for re-programming, and control in an electronics workshop
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Digitiser
Digitiser specifications draft 2
Modified after Agata Week Legnaro 15/19 September
2) Block diagram
Fig2 Block diagram
FADC block:
The FADC cards contain 100 MHz ( or 80 MHz )ADC's producing 14 bit wide data.
The FADC card outputs pass through a serialiser circuit permitting the use of fiber-optic links
between the ADCs and the pre-processing cards to obtain adaptability for future upgrade of
pre-processing electronics and maximum electrical isolation. One transceiver fiber-optic link
will be used to send data to the pre-processing card for the core FADC and to receive clock
and offset control from the pre-processing card.
Monitoring block:
The Monitoring block provides control of the spare channels and inspection lines via a slow
control link to the GUI system control software. The temperature of the various parts of the
digitiser electronics will be accessible to this slow control link.
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Digitiser
Digitiser specifications draft 2
Modified after Agata Week Legnaro 15/19 September
C) DESCRIPTION
1) Monitoring block
Fig3 Block diagram for Control
a) Temperature Monitoring
This part will have to manage the monitoring of the temperature of both the digitiser box and
FADC and if necessary its regulation. For the final modules one could envisage simplifying it
but not for the first prototypes. The values of the temperatures will be recorded in a fifo in
order to enable their inspection over time.
b) Global clock receiver
The Global Clock function will have to reconstruct a clock of quality with a very small jitter
(<7pS). When used in an electronics workshop the digitiser will have to provide its own clock
signal for coding ( independent of an external system of clock).
c) Offset adjustment monitoring
The offset value required will be calculated by the pre-processing card to give as large as
possible an input dynamic range of coding. The monitoring block has to control each DAC.
There is one DAC per channel.
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Digitiser
Digitiser specifications draft 2
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d) Spare channel order


1 spare FADC input for the Core.
1 spare FADC input for each group of 6 inputs.
e) Inspections lines for monitoring
Each analog channel from the detector could be inspected before and after coding. Two
analogue lines will exist per group of 6 segments channels
f) Monitoring block optical interface
This link is for communicating with the VirtexIIPro which includes the data serialiser for the
optical fibre link to the pre-processor card. The Slow Control link will operate via this
interface. All the optical interface modules will include a monitoring function for the laser
diodes.
g) Loader ( USB2 interface )
The loader (USB2 interface) enables the VirtexIIpro to be re-programmed without
disassembling the digitiser module, and is used to implement the Slow Control link in an
electronics workshop with a portable PC.
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Digitiser
Digitiser specifications draft 2
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2) FADC block
2.1) Segments blocks
Fig4 Diagram for segment input
a) Buffer
The Buffer module provides impedance matching and separation of the signals between the
FADC, the spare channel, and inspection lines.The input signals are differential.
b) Offset
The offset value required will be dynamically calculated by the pre-processing card to give as
large as possible an input dynamic range.
c) Driver
The driver adds the offset signal. The anti-aliasing filter is included in the Driver before the
FADC.
d) FADC
The ADC must have 14 bits and 80 MHz or 100 MHz. 16 data bits are sent to the FPGA; bits
0 to 13 are data, bit 14 is the FADC overload and bit 15 could be used as a synchronisation
pulse. The overload bit could also be transmitted to the preamplifier for the Pole Zero reset
through the FPGA.
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e) LineDriver
It avoids capacitive loading of the data bus at the output of the FADC, and allows the FADC
data bus to be transmitted to the Laser card.
f) Clock
It receives the clock of GlobalClock and transmits it to the FADCs with a skew and a jitter as
small as possible.
g) FPGA/Serialiser
The FPGA receives the signals from the FADCs and dispatches them towards the serialisers
and the analog line of inspection after coding. Depending of the choice made the serialiser
will be or not integrated in the FPGA.
h) Laser Multifiber
An optical transmitter is used for the interface between the digitiser and pre-processing cards .
The number of channels per Multifiber has to be discussed in the Digitiser Team (modulo 6
with spares or 12 without spares)
2.2) Core blocks
Fig5 Diagram for Core input (with one spare channel)
Similar to the Segment.
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Digitiser
Digitiser specifications draft 2
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D) DETAILS
1) Monitoring block
a) Temperature monitoring.
The temperature control will be performed by a “1-wire-Digital Thermometer” family
component from Maxim (DS1822). A large number of channels can be connected using only
one wire. Some logical TTL signals (depending on how many pins are free on the FPGA) will
be connected to a logical output. They can be used for output commands for temperature
regulation for example. (Other components exist)
b) Global Clock.
Fig6 Global clock diagram
The global clock gives the time reference and is used to regenerate the clock for FADC ( The
connection to Global clock could be either direct or via the pre-processing card. The details
will be decided after discussions with the Global Clock Team )
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Digitiser
Digitiser specifications draft 2
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A Digital PLL is used to produce the coding clock. The frequency can be changed by software
control.
Methodology
Clock regeneration will be done using the clock distributed by the Receiver (SERDES) from
the global clock (or the local clock from the pre-processing cards).
The component is able to multiply the reference clock by a factor 4 to 20. The programming
of the component is performed through the FPGA.
The following signal qualities can be controlled:
 Output frequency to 48 bits Accuracy
 Output phase to 14 bits Accuracy
 Output Amplitude to 12 bits Accuracy
The component able to do this is the AD9852 from Analog Device.
Fig7 AD9852 Shema block diagram
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The AD9852 ( DDS) is able to produce a clock with a jitter around 7ps. Because the clock is
not differential a differential receiver from ON Semiconductor will be used. The reference is
MC100LVECL16. The output jitter from the receiver is less than 0,7 ps. One receiver is
associated with one FADC. (Read datasheet for more details)
The DDS has a 12 bit control DAC 100 MHz which could be used as a test generator.
For that purpose i propose to connect it at an output connector.
The DDS mode will be “Single-Tone”. In this mode the internal clock (System Clock )
is 4x-20x Reference Clock (Global Clock). In this case the value of the frequency tuning
world is determined using the equation:
FTW = (Desired Output Frequency x 2^n )/System Clock
The fundamental sine wave DAC output frequency ranges is from dc to ½ System Clock
c) Offset adjustement.
All the DAC are based on the same chip: PC56M. We have used it for a long time. It has a
low noise level, is bipolar and has a serial control.
d) Spare Channel.
The spare channel is enabled through an ultra low noise buffer from BB OP692.
e) Inspection line monitoring.
Inspection line is enabled through a ultra low noise buffer from BB OP692. The inpection line
output is in common mode. The common mode will be obtained with the same buffer from
BB OP692.
Fig8 Inspection line sum
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f) Optical interface monitoring.
Depending of component choice a serial line command must be connected for initialisation.
To be defined.
g) Loader/USB2 Interface.
The loader is necessary for at least two reasons:


We must be able to load the FPGA with a new configuration without disassembling.
USB2 Interface will be used for test in electronics workshop.
We can use the Serial or Parallel slave SelectMode Map
Block Diagram example for Parallel SelectMode using a SpartanIIE to drive the loading of
programs into the Virtex2Pro devices on the Laser boards.
Fig9 Loader block diagram
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2) FADC module
a) FADC line (Segment or Core)
Fig10 FADC diagram

Buffer input/Analog inspection line
For buffer input we use OPA692 with disable output command and low noise level and fixed
gain.
Fig11 Input segment diagram
If the spare channel is needed the ‘red’ buffers will be disabled and the white buffers will be
enabled. If we need to check the signal through the inspection line the ‘blue’ buffer will be
enabled.
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Digitiser
Digitiser specifications draft 2
Modified after Agata Week Legnaro 15/19 September

Range
In the Agata preamplifier Team Meeting in Milano ( 14/05/2003):
“ The group agrees that the analog chain should be designed so as to guarantee the best energy
resolution with the typical gain range selection ( 0-5MeV), giving the user the possibility to
amplify/attenuate the analog signal in front of the ADC so as to change the range.”
Normal Range
Extended Range

0 – 5 MeV
0 – 20 MeV
Driver /Offset ( This part must be discussed and tested )
For the FADC driver we will use the AD8138 from AD.
To conserve the advantage of the differential signal and after discussion with Preamplifier
Team I propose the following diagram:
The first buffer could be AD8056 or OP692.
The second stage could be the OPA 692.
Fig12 Driver Offset input
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
Line Driver
This design is for an ADC6645 with sample frequency 80 MHz.
Fig13 Line Driver block diagram

FPGA for communications
A small FPGA will be implementing to control communication from/to the Laser Board
and the Monitoring board. Signals like FADC offset; inspection line; spare channel;
Temperatures will be control trough this FPGA.
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b) Serialiser

Segments/Core
o Case of Virtex2Pro
The Application note from Xilinx ( White Paper WP160 ) details the advantages of
this component:
 Reduce the PCB footprint by integrating the external SERDES into the
FPGA.
 Fewer FPGA I/Os used
 Less complicated PCB layout
 Signal integrity issues limited to serial/differential I/O signals
Core Serialiser:
We need 3 serialiser. One+Spare for the FADC data. One for answer to slow control interface.
The number of pins are :
(16 bits FADC) x 2 lines + 16 bits (slow contol answer)= 48 I/O
Segment Serialiser:
For 7 Serialisers ( 6 FADCs + Spare ) the number of pins are :
(16 bits FADC) x 7 lines = 112 I/O
In this case the device for the FPGA ( VIRTEXII Pro ) for a group of 7 serialisers will be
a FG676 or FG672.
The choice for the serialiser will be the same as chosen by the pre-processing team.
c) Analog inspections lines after FADC
After sampling and setting offsets the segment signals can be inspected through a DAC. This
component will be AD9765 12bits 120 MSPS. The output will be driven through an AD8055.
d) Laser
 Laser interface for Segments.
Receives the data from the serialiser and transmits data to the Pre-processing hardware.
We must use 12 channels Transmitter or 2x12 channels Transmitter for a group of 6.
 Laser interface for Core/Global Clock.
It receives the data from the serialiser and transmits data to the Pre-processing hardware.
We must use 2 channels for core. And one channel for slow control answers.
Receives the clock and control from Pre-processing hardware and transmits data to
Deserialiser.
The choice must be done with Pre-processing Team.
The power dissipation will have to be studied carefully.
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Digitiser
Digitiser specifications draft 2
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E ) PARTITION GROUP
Fig15 PCB Block diagram Digitiser
Because of the large number of functionalities it is not possible build the digitiser in one PCB.
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3 types of PCBs will be use.

Monitoring board: ( could be divided in two parts if necessary )
o Core FADC with offset, one spare channel and Serialiser and Laser
Transmitter ( 2 fibers for core; 1 fiber for slow control answer ).
o Global Clock interface between the monitoring board and the Laser board.
o Laser Receiver ( 1 fiber for Global Clock )
o USB2 Interface.
o Inspection (logical/analog) lines
o Temperature monitoring / Fan control.
o DC supply:
 First stages for DC supply Segments Board.
 First stages for DC supply Lasers Board.
 First stage for Preamplifier Segments.
o Global Clock interface between the monitoring board and the Laser board.

3 x Segments Boards. ( Each board contains two blocks of 2)
o
o
o
o
o
o

7 FADC with offset and serialiser.
Inspection (logical/analog) lines for the 7 channels.
DC supply for FADC Segments.
Global Clock interface with slow control though the Laser Board
Temperature measurement
Small FPGA for communications.
3 x Lasers Boards.
o
o
o
o
o
o
Temperature monitoring for segments board and lasers boards.
2 Lasers Transmitter multifiber modules.
Temperature measurement
DC supply for Lasers Board
USB2 Interface.
Inspection (logical/analog) lines for the 7 (14) channels with 2(4)xDAC
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F) INTERCONNECTIONS BETWEEN BOARDS.
Fig16 PCB Communication inside the Digitiser
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Fig17 Communications links
The links will be done using “serializer/deserializer core” from xilinx.
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G) MECHANICAL HOUSING
Two problems have to be solved:
o To respect the maximum distance between the digitiser boards and the
preamplifiers (5m maxi)
o To be able to dissipate the power for all electronics
Fig18 Mechanical housing
The objective is to avoid a cooling system.
Prices of mechanical housing have been estimated to be of the order of 1500 Euros
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Fig 19 First mechanic design for temperature tests
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H) COSTING
Monitoring Board
FADC module
FADC 14 BITS 80MHz
relais
PCM56U
Temp
Buffer clock
Buffer Data
Buffer for Dry
AD 8138
Analog parts ( misc)
Total 1 channel
1 Channel + 1 Spare
Global Clock
AD9852
TCXO10MHz
Analog part
Total Global Clock
Inspections lines
Video buffers
Analog part
AD9765
Total inspections lines
Loader USB2 Interface
Cypress
memory cypress
Spartan2E
XC18V01
MemoryVirtex
Total loader
Logic Interface
Virtex2/pro
Laser Global clock
Laser Global core
HV control
Temperature
Total logic Interface
DC supply
DC supply monitoring board
DC laser
Total DC supply
PCB
PCB and electric tests
Mounting
Connectiques
TOTAL MONITORING BOARD
70
9
14
10
7
1,2
0,7
6
100
217,9
435,8
34
5
25
64
5
20
25
50
30
1
27
20
3
81
300
500
500
50
80
1430
200
50
250
1000
500
800
4610,8
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FADC Boards
FADC module
FADC 14 BITS 80MHz
relais
PCM56U
Temp
Buffer clock
Buffer Data
Buffer for Dry
AD 8138
Analog parts ( misc)
Total 1 channel
2 x (6 Channels + 1 Spare)
Inspections lines
Video buffers
Analog part
Total inspections lines (x 2)
70
9
14
10
7
1,2
0,7
6
100
217,9
3050,6
5
20
50
FPGA
Spartan2E
XC18V01
Total FPGA
27
20
47
DC supply
DC supply FADC board
200
PCB and electric tests
600
400
PCB
Mounting
TOTAL FADC BOARD
Total FADC 36 segments + Spare
4347,6
13042,8
Lasers Boards
Lasers Tranceiver
6 channels + 1 spare
6 channels + 1 spare
Analoq part
Temperature
500
500
100
30
1130
Inspections lines
Video buffers
Analog part
AD9765
Total inspections lines (x 2)
Loader USB2 Interface
Cypress
memory cypress
Spartan2E
XC18V01
5
20
25
100
30
1
27
20
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Digitiser specifications draft 2
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MemoryVirtex
Total loader
Logic Interface
6
84
Virtex2/pro
Total Interface
400
400
PCB
PCB and electric tests
Mounting
600
400
Total Laser Board
2714
Total Laser 36 channels + spare
8142
TOTAL COST : 26000 Euros ( 37+7 /channels/600 Euros )
I) ESTIMATION OF THE POWER
FADC module
Global Clock
Inspections lines
Loader USB2 Interface
Logic Interface Monitoring Board
Lasers Transceiver FADC
Logic Interface Laser Board
Logic Interface FADC Board
TOTAL
Power
4,895
2,9
0,58
1,85
6,1
5,2
3
1,1
Number
PowerPartial
42
205,59
1
2,9
7
4,06
4
7,4
1
6,1
3
15,6
3
9
3
3,3
253,95
Power dissipation ( Analog + Digital Supply ) : 330 W
J) REMARQUES
IN THIS DRAFT THE CONNECTIONS BETWEEN THE
DIGITISER AND THE PREAMPLIFIER IS NOT ANALYSE.
ARE MISSING:
POLE ZERO PREAMPLIFIER ADAPTATION
OPTO_COUPLING
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Digitiser specifications draft 2
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K) GUI AND CONTROL SOFTWARE
For test the digitiser use the TNT interface for GUI control based on USB2 interface will be
used.
L) PROCEDURE OF WORK
a) Design a prototype based on TNT architecture and readout to test analog electronics
design. (Start end September).This design is realised for other projects and will not be
for Agata but useful for tests. JOB DONE WAITING FOR PCB AND CABLING
b) Define dialog between boards inside the Digitiser. JOB IN PROGRESS
c) Define the mechanical housing to build a prototype. JOB IN PROGRESS WITH
THERMIC TESTS
d) Define the connections between Detector/Preamplifier and Digitiser
e) Define a dialog for slow control between Pre-processing Board and Digitiser.
f) Define PCB and build prototype; mounting components.
g) Start tests FADC Board alone.
h) Start tests Monitoring Board/Core FADC alone.
i) Start tests Laser Board and connections.
j) Start tests connections with Pre-processing Board
k) Start tests with Preamplifier + Digitiser + Pre-processing.
l) Drink a beer
m) If good results start production.
n) Drink Champagne at least.
The first prototype could be designed in 18 month from January 2004 to June 2005.
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ANNEXE ( Reference Testbed_specifications_draft3 written by
Ian Lazarus)
1) FADC AD 6645-80 MHz
The FADC is available in 80MHz now and 100MHz is just coming to the market. These
comments are based on the 80MHz version, but the plans assume that the 100MHz version
will be used and that its performance will be essentially the same as the 80MHz version.
a)
Some specifications :
o Resolution
o No missing codes
o DNL
o Temperature drift :
o Gain error
o SNR:
o ENOB:
15,5 MhZ
30,5 MhZ
14 bits
-1 < 0,25 < 1,5 LSB
48 ppm /1° C ( 1 channel for full scale )
ENOB = 12,12 bits
ENOB = [11,75 12] bits
o SNR / TEMPERATURE
For the total range of temperature T = [ -40°:+85°] the SNR = [74,7:75,2] and the ENOB
=[ 12: 12,2]. The temperature doesn’t have a significant effect on the SNR.
From the point of view of SNR it is not necessary to have cooling for this component. To
increase the stability of gain the best and simple choice will be to use a heat sink bonded
to the pcb. The principle has been presented by Ian at the Liverpool meeting.
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b)
Switching specifications
o Timing diagram
Analog device datasheet:
The timing diagram in correspondence with the parameters limits shows that the Data
are ready in regards with the DRY signal and not ENC/ENC.
The data bus must be synchronous with the DRY signal ( Data Ready Signal )
The time skew between different components could be enough big to create some
synchronisation problems. This is why each transceiver must use DRY for its own clock.
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c)
Clock jitter
Analog devices datasheet says:
The figure 12 shows clearly the effect of jitter. If we want the SNR as good as possible
then the clock must be as good as possible.
This is why the FADC clock must be built with specific components related to this
specific application. ( Digital PLL ). If we want at less the ENOB greater than 11 for
an analogue input signal bandwidth equal to 30 MHz we must have a jitter less than
1.5 ps
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d)
Layout
o Digital outputs
Analog devices datasheet says:
Because of the Serial Transfer we must put a serialiser at another part of the pcb. The
distance will be high so we must avoid the capacitive loading using serial resistors and IC
like 74CLX574. Of course it will create a new delay and it is important to delay the
control clock into the transceiver.
e) Grounding
Analog device datasheet:
To repeat ( Analog Devices’ advice)
“FOR OPTIMAL PERFORMANCE, IS IT HIGHLY RECOMMENDED THAT A COMMON
GROUND BE UTILIZED BETWEEN THE ANALOG AND DIGITAL POWER PLANS.”
“IN GENERAL, SPLITTING THE ANALOG AND DIGITAL GROUNDS CAN
FREQUENTLY CONTRIBUTE TO UNDESIRABLE EMI-RFI AND SHOULD THEREFORE
BE AVOIDED.”
The layout will use a common ground plane for both the analogue and digital part.
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