School of Electrical, Computer and Energy Engineering
M.S. Final Oral Defense
DC Optimizer for PV Module
by
Daniel Luster
17 November 2014
1:00 p.m.
GWC 303
Committee:
Dr. Raja Ayyanar (chair)
Dr. Bertan Bakkaloglu
Dr. Sayfe Kiaei
Abstract
As residential photovoltaic (PV) systems become more and more common and
widespread, their system architectures are being developed to maximize power extraction
while keeping the cost of associated electronics to a minimum. An architecture that has
become popular in recent years is the “DC optimizer” architecture, wherein one DC-DC
converter is connected to the output of each PV module. The DC optimizer architecture
has the advantage of performing maximum power-point tracking (MPPT) at the module
level, without the high cost of using an inverter on each module (the "micro-inverter"
architecture). This work details the design of a proposed DC optimizer. The design
incorporates a series-input parallel-output topology to implement MPPT at the submodule level. This topology has some advantages over the more common series-output
DC optimizer, including relaxed requirements for the system’s inverter. An autonomous
control scheme is proposed for the series-connected converters, so that no external
control signals are needed for the system to operate, other than sunlight.
The DC
optimizer in this work is designed with an emphasis on efficiency, and to that end it uses
GaN FETs and an active clamp technique to reduce switching and conduction losses. As
with any parallel-output converter, phase interleaving is essential to minimize output
RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to
achieve interleaving among the series-input converters.