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Last updated February 1, 2015
BIOGRAPHY
Melvin A. Breuer
Melvin A. Breuer received his Ph.D. in electrical engineering from the University of
California, Berkeley, and is the Charles Lee Powell Professor of Electrical Engineering
and Computer Science at the University of Southern California. He was Chairman of the
Department of Electrical Engineering-Systems from 1991-1994, and again from 20002003. He was Chair of the Faculty of the School of Engineering, USC, for the 1997-98
academic year. His main interests are in the area of computer-aided design of digital
systems, design-for-test and built-in self-test, and VLSI circuits.
Dr. Breuer is the editor and co-author of Design Automation of Digital Systems:
Theory and Techniques, Prentice-Hall; editor of Digital Systems Design Automation:
Languages, Simulation and Data Base, Computer Science Press; co-author of
Diagnosis and Reliable Design of Digital Systems, Computer Science Press; co-editor
of Computer Hardware Description Languages and their Applications, NorthHolland; co-editor and contributor to Knowledge Based Systems for Test and
Diagnosis, North-Holland; and co-author of Digital System Testing and Testable
Design, Computer Science Press 1990 and reprinted in 1995 by the IEEE Press. He has
published over 270 technical papers and was formerly the editor-in-chief of the Journal
of Design Automation and Fault Tolerant Computing, on the editorial board of the
Journal of Electronic Testing, the co-editor of the Journal of Digital Systems, and the
Program Chairman of the Fifth International IFIP Conference on Computer Hardware
Description Languages and Their Applications. He is a co-author of a paper that
received an honorable mention award at the 1997 International Test Conference, a coauthor of a paper nominated for the best paper award at the 1998 Design Automation and
Test in Europe Conf., a co-author of a paper published in the 1998 International Test
Conference that was selected to be in a compendium of significant papers over the last 35
years, and a co-author of the best paper at the 2000 Asian Test Symposium.
A few of his major achievements and awards are:
o Life Fellow of the IEEE
o Fulbright-Hays scholar (1972)
o 1991 Associates Award for Creativity in Research and Scholarship from the
University of Southern California
o 1991 USC School of Engineering Award for Exceptional Service
o 1993 IEEE Computer Society’s Taylor L. Booth Education Award
o 2003 Okawa Foundation Research Grant in support of research to “Increase the
effective yield of VLSI chips via design and test”
o The first (2000) Engineering Faculty Council Award for Outstanding Meritorious
Service to the USC School of Engineering.
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o 2011 European Design and Automation Association (EDAA) Lifetime
Achievement Award
o 2011 John J. Guarrera Engineering Educator of the Year Award
o 2011 IEEE Computer Society Test Technology Technical Council (TTTC)
Lifetime Achievement Award.
He was the keynote speaker at the Fourth Multimedia Technology and Applications
Symposium, 1999; the Ninth Asian Test Symposium, 2000; the International Conference
on Computer Design (ICCD), 2004; the Annual Symposium on VLSI (ISVLSI), 2005;
the IEEE VLSI Test Symp., 2008, and an invited speaker at the Thirteenth Asian Test
Symposium, 2004.
The Test Technology Technical Council of the IEEE Computer Society hosted a
forum on October 26, 2006 at the Hyatt Regency Hotel, Santa Clara, California to
“celebrate Professor Melvin A. Breuer’s illustrious career and recognize his contributions
to VLSI areas of design automation, design for testability, fault tolerance and test; and the
influence he had on the industry and academia as an educator and a mentor.”
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MELVIN A. BREUER
B.S.
Engineering, 1959,
University of California, Los Angeles
M.S.
Engineering, 1961,
University of California, Los Angeles
Ph.D. Electrical Engineering, 1965
University of California, Berkeley
1965-1969: Assistant Professor
Department of Electrical Engineering
University of Southern California
1969-1979: Associate Professor
Departments of Electrical Engineering and Computer Science
University of Southern California
1979-: Professor
Departments of Electrical Engineering and Computer Science
University of Southern California
1991-1994: Chairman, Electrical Engineering Systems Department
University of Southern California
1995-: Charles Lee Powell Professor of Electrical Engineering and Computer Science,
University of Southern California
2000-2003: Chairman, Electrical Engineering Systems Department
University of Southern California
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PUBLICATIONS
1.
The Borel-Tanner distribution, Biometrika, vol. 47, pp. 143-150, 1960, with F.A.
Height.
2.
A multiply-add operation for a serial digital computer, U.S. Patent, ThompsonRamo-Woolridge Corporation (1961), with L. Amdahl and J. Davis.
3.
The minimization of Boolean functions containing unequal and nonlinear cost
functions, ACM 1962 Conference Digest, September 7, 1962, Syracuse, New
York.
4.
Techniques for simulation of computer logic, Comm. of the ACM, pp. 443-446,
July 1964.
5.
Digitalization of continuous control systems, Simulation, vol. 5, no. 5, pp. 329337, November 1965.
6.
Implementation of threshold nets by integer linear programming, IEEE Trans. on
Electronic Computers, vol. EC-14, no. 6, pp. 950-952, December 1965.
7.
The formulation of some allocation and connection problems as integer programs,
Naval Research Logistics Quarterly, vol. 13, no. 1, pp. 83-95, March 1966.
8.
Coding the vertices of a graph, IEEE Trans. on Information Theory, vol. IT-13,
no. 2, pp. 148-153, April 1966.
9.
The application of integer programming in design automation, Proc. SHARE
Design Automation Workshop, May 1966.
10.
General survey of design automation of digital computers, Proc. of the IEEE, vol.
54, no. 12, pp. 1708-1721, December 1966.
11.
Adaptive computers, Information Control, vol. 11, no. 4, pp. 402-422, October
1967.
12.
An unexpected result in coding the vertices of a graph, Journal of Mathematical
Analysis and Applications, vol. 21, no. 3, pp. 583-600, December 1967, with J.
Folkman.
13.
Some properties of (0,1) circulant matrices, Proc. of the Hawaii Int’l Conference
on System Sciences, pp. 793-794, January 1968.
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14.
Heuristic switching expression simplification, Proc. 23rd National Conference of
the ACM, pp. 241-250, 1968.
15.
Fault detection in linear cascades of identical sequential machines, Proc. IEEE
Conf. on Switching and Automata Theory, pp. 235-244, 1968.
16.
Hardware fault detection, Proc. Fall Joint Computer Conference, vol. 33, pp.
1501-1503, 1968.
17.
Combinational equivalences of (0,1) circulant matrices, Journal of Computer and
System Science, vol. 3, no. 1, pp. 8-28, February 1969.
18.
Generation of optimal code for expressions via factorization, Comm. of the ACM,
vol. 12, no. 6, pp. 333-340, June 1969.
19.
Logic synthesis, Proc. Joint Conf. on Mathematical and Computer Aids to
Design, pp. 146-161, October 1969, IEEE Catalogue No. 69C 63-C.
20.
Simplification of the covering problem with applications to Boolean expression,
JACM, vol. 17, pp. 166-182, January 1970.
21.
Functional partitioning and simulation of digital circuits, IEEE Trans. on
Computers, vol. C-19, pp. 1038-1046, November 1970.
22.
Generation of fault detection tests for sequential circuits, Digest Int’l Symposium
on Fault-Tolerant Computing, pp. 18-21, March 1-3, 1971.
23.
An algorithm for generating a fault detection test for a class of sequential circuits,
presented at the Int’l Symposium on the Theory of Machines and Computations,
August 1971, Haifa, Israel; re-published in Theory of Machines and
Computations, Z. Kohavi (ed.), Academic Press, pp. 313-326, 1971.
24.
A random and an algorithmic technique for fault detection test generation for
sequential circuits, IEEE Trans. on Computers, vol. C-20, pp. 1364-1371,
November 1971.
25.
Generation of fault tests for linear logic networks, IEEE Trans. on Computers,
vol. C-21, pp. 79-83, January 1972.
26.
Recent developments in the automated design and analysis of digital systems,
Proc. of the IEEE, vol. 60, pp. 12-27, January 1972.
27.
A note on three-valued logic simulation, IEEE Trans. on Computers, vol. C-21,
pp. 399-402, April 1972.
28.
Recent developments in design automation, Computer, pp. 23-35, May/June 1972.
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29.
Generation of fault detection tests for intermittent faults in sequential machines,
Digest Int’l Symposium on Fault-Tolerant Computing, pp. 53-57, June 1972.
30.
Automatic test generation for sequential and combinational logic, Proc. of the
National Electronic Packaging Conference (NEPCON), pp. 109-117, 1972,
Anaheim, California.
31.
Automatic test generation for digital networks-some experimental results, Digest
Computer Simulation Conference, pp. 98-108, June 1972, San Diego, California,
with S.Y.H. Su.
32.
Design Automation of Digital Systems: Theory and Techniques, Prentice-Hall,
1972 (editor and co-author).
33.
Testing for intermittent faults in digital computers, IEEE Trans. on Computers,
vol. C-22, pp. 241-245, March 1973.
34.
The smallest many-valued logic for the treatment of complemented error signals,
1973 Int’l Symposium on Multiple-Valued Logic, pp. 29-37, May 24-25, 1973,
Toronto, Canada, with G. Epstein.
35.
Analysis of the detectability of faults by random test patterns in a special class of
NAND networks, Comput. and Elect. Engineering, vol. 1, pp. 171-186, 1973,
with H. Huang.
36.
Initial design concepts for an advanced design automation system, Proc. 11th
Design Automation Workshop, pp. 366-371, June 17-19, 1974, with A.D. Friedman.
37.
Modeling circuits for test generation, Proc. Int’l. Symposium on Fault-Tolerant
Computing, pp. 3-13 to 3-18, June 1974.
38.
Procedures for eliminating static and dynamic hazards in test generation, IEEE
Trans. on Computers, vol. C-23, pp. 1078-1092, October 1974.
39.
The effects of races, delays, and delay faults on test generation, IEEE Trans. on
Computers, vol. C-23, pp. 1078-1092, October 1974.
40.
Curriculum on design automation at the University of Southern California, Proc.
ACM National Conference, November 11-13, 1974.
41.
Why we need hardware descriptive languages, Computer, p. 19, December 1974,
with J. Hayes.
42.
Digital System Design Automation: Languages, Simulation and Data Base,
Computer Science Press, 1975 (editor).
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43.
Identification of multiple stuck-type faults in combinational networks, IEEE
Trans. on Computers, vol. C-25, no. 1, pp. 44-54, January 1976, with S.J. Chang
and S.Y.H. Su.
44.
Incremental processing in design automation, SIGDA Newsletter, vol. 6, pp. 2-9,
November 1976.
45.
Diagnosis and Reliable Design of Digital Systems, Computer Science Press,
1976, with A.D. Friedman.
46.
The smallest many-valued logic for the treatment of complemented and
uncomplemented error signals, in Computer Science and Multiple-Valued
Logic: Theory and Applications (D.C. Rine, editor), pp. 45-51, North-Holland
Publishing Company, 1977, with G. Epstein.
47.
Concurrent fault simulation and functional level modeling, Proc. 14th Design
Automation Conf., pp. 128-137, June 1977, with M. Abramovici and K. Kumar.
48.
Some theoretical aspects of algorithmic routing, Proc. 14th Design Automation
Conf., pp. 23-31, June 1977, with P. Agrawal.
49.
Generation of tests for digital circuits using generalized fault lists, Proc. 7th Int’l
Conference on Fault-Tolerant Computing, pp. 103-108, June 1977, with Y.
Levendel.
50.
A class of min-cut placement algorithms, Proc. 14th Design Automation Conf., pp.
284-290, June 1977. Also published in 25 Years of Electronic Design
Automation, by the Association for Computing Machinery, New York, NY, pp.
142-148, 1988.
51.
The design of self-checking multi-output combinational circuits, Proc. National
Computer Conf., pp. 711-721, 1977, with D.C. Ko.
52.
Min-cut placement, Journal Design Automation and Fault Tolerant Computing,
vol. 1, pp. 343-362, October 1977. Also republished in VLSI Circuit Layout:
Theory and Design, edited by T.C. Hu and E.S. Khu, IEEE Press, pp. 105-114,
1985.
53.
Self-checking of multi-output combinational circuits using extended parity
techniques, Journal Design Automation and Fault Tolerant Computing, vol. 2, pp.
29-62, January 1978, with D.C. Ko.
54.
Vector representation of switching and three valued functions, Proc. 8th Annual
Symp. on Multi-Valued Logic, May 1978, with Y. Levendel.
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55.
Mathematical properties of Boolean transforms, Proc. 8th Annual Symp. on MultiValued Logic, May 1978, with Y. Levendel.
56.
New concepts in automated testing of digital circuits, Proc. Symp. on Computer
Aided Design of Digital Electronic Circuits, November 27-29, 1978, Brussels,
Belgium.
57.
Experiments with a density router, IEEE Trans. on Computers, vol. C-28, pp.
262-267, March 1979, with P. Agrawal.
58.
Incremental processing applied to Steinberg’s placement procedure, Proc. Design
Automation Conf., pp. 26-31, June 1979, with H.W. Carter and Z.A. Syed.
59.
Deduction of internal signal values in combinational networks based upon test
results, Proc. 9th Int’l. Symp. on Fault Tolerant Computing, pp. 129-133, June
1979, with M. Abramovici.
60.
A forced directed component placement procedure for printed circuit boards,
IEEE Trans. on Circuits and Systems, vol. CAS-26, pp. 377-388, June 1979, with
N.R. Quinn, Jr.
61.
TEST/80-a proposal for an advanced automatic test generation system,
AUTOTESTCON ’79, pp. 305-312, September 1979, with A.D. Friedman.
62.
On redundancy and fault detection in sequential circuits, IEEE Trans. on
Computers, vol. C-28, pp. 864-865, November 1979, with M. Abramovici.
63.
A probabilistic model for the analysis of the routing process for circuits,
Networks, vol. 10, pp. 111-127, 1980, with P. Agrawal.
64.
Functional level primitives in test generation, IEEE Trans. on Computers, vol. C29, pp. 223-235, March 1980, with A.D. Friedman.
65.
Fault diagnosis based on effect-cause analysis: an introduction, Proc. Design
Automation Conf., pp. 69-76, June 1980 with M. Abramovici.
66.
Multiple fault diagnosis in combinational circuits based on an effect-cause
analysis, IEEE Trans. on Computers, vol. C-29, pp. 451-460, June 1980, with M.
Abramovici.
67.
Routing of undirectional point configurations with optimal solutions for minimum
wire length, congestion, and perturbation, Proc. IEEE Int’l. Conf. on Circuits and
Computers, pp. 286-289, October 1980, with H.W. Carter.
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68.
Fault diagnosis in sequential circuits based upon an effect-cause analysis, Digest
10th Int’l. Symp. on Fault-Tolerant Computing, pp. 313-318, October 1980, with
M. Abramovici.
69.
A hardware router, J. Digital Systems, vol. 4, pp. 393-408, Winter 1980, with K.
Shamsa.
70.
Digital systems simulation: Current status and future trends, Proc. 18th Design
Automation Conference, pp. 269-275, June 1981, with A. Parker.
71.
Probabilistic aspects of Boolean switching functions via a new transform, JACM,
vol. 28, pp. 502-520, July 1981, with S.K. Kumar.
72.
A survey of the state of the art of design automation, Computer, vol. 14, pp. 5875, October 1981, with A. Friedman and A. Iosupovicz.
73.
A fault collapsing analysis in sequential logic networks, BSTJ, vol. 60, no. 9, pp.
2259-2271, November 1981, with S-J Chang.
74.
Computer hardware description languages and their application, North
Holland Publishing Co., 1981, co-edited with R. Hartenstein.
75.
A survey of the state-of-the-art of design automation, Proc. 19th Design
Automation Conf., page 1, June 1982.
76.
On routing for custom integrated circuits, Proc. 19th Design Automation Conf.,
pp. 887-893, June 1982, with Z. Syed and A. El Gamal.
77.
Optimum placement of two rectangular blocks, Proc. 19th Design Automation
Conf., pp. 879-886, June 1982, with M.S. Chandrasekhar.
78.
Bounds on channel width and a routing algorithm for a classical channel
configuration, Proc. IEEE Int’l Conference on Circuits and Computers, pp. 250255, September 1982, with M.S. Chandrasekhar.
79.
VLSI routing, in Hardware and Software Concepts in VLSI, G. Rabbat
(editor), Van Nostrand, Chapter 15, pp. 368-405, 1983, with H.W. Carter.
80.
Fault diagnosis in sequential circuits based upon an effect-cause analysis, IEEE
Trans. on Computers, vol. C-31, pp. 1165-1172, December 1982, with M.
Abramovici.
81.
Test generation models for busses and tri-state drivers, Proc. IEEE ATPG
Workshop, pp. 53-58, March 1983, San Francisco, California.
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82.
The automatic design of testable circuits, Proc. IEEE ATPG Workshop, pp. 3-6,
March 1983, San Francisco, California.
83.
Row-column synthesis of VLSI macrocells, in Proc. IEEE Int’l Symp. on Circuits
and Systems, vol. 3, pp. 1220-1224, May 1983, with D.W. Knapp.
84.
A module interchange placement machine, Proc. 20th Design Automation
Conference, pp. 171-174, June 1983, with A. Iosupovicz and C. King.
85.
A placement algorithm for array processors, Proc. 20th Design Automation Conf.,
pp. 182-188, June 1983, with D-J Chyan.
86.
Roving emulation as a fault detection mechanism, Digest of Papers 13th Int’l
Symp. on Fault-Tolerant Computing, pp. 206-215, June 1983, with A. Ismaeel.
87.
A methodology for custom VLSI layout, IEEE Trans. on Circuits and Systems,
vol. CAS-30, pp. 358-364, June 1983; also in IEEE Trans. on Automatic Control,
vol. AC-28, pp. 671-677, June 1983; also in IEEE Trans. on Systems, Man and
Cybernetics, vol. SMC-13, July/August 1983, with A. Kumar. (This was a special
issue published by three IEEE technical societies).
88.
Efficient single layer routing along a line of points, IEEE Trans. on Computer
Aided Design of Integrated Circuits and Systems, vol. CAD-2, pp. 259-266,
October 1983, with H. Carter.
89.
Automatic design for testability based upon a cost measure, Proc.
AUTOTESTCON, pp. 130-143, November 1983.
90.
On area and yield considerations for fault-tolerant VLSI processor arrays, IEEE
Trans. on Computers, vol. C-33, pp. 21-27, January 1984, with I. Koren.
91.
An optimal testing algorithm for symmetric coherent systems, Journal of
Mathematical Analysis and Applications, vol. 101, no. 1, pp. 170-194, June 1984,
with S. Salloum.
92.
Automatic design for testability via testability measures, IEEE Trans. on
Computer-Aided Design of Integrated Circuits, vol. CAD-4, pp. 3-11, January
1985, with T-H Chen.
93.
Incremental processing applied to Munkre’s algorithm and its application in
Steinberg’s procedure, SIAM J. on Algebraic and Discrete Methods, vol. 6, no. 2,
pp. 210-219, April 1985, with H.W. Carter and Z.A. Syed.
94.
A knowledge based system for selecting a test methodology for a PLA, Proc. 22nd
Design Automation Conf., pp. 259-265, June 1985, with X-A Zhu.
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95.
The construction of minimal area power and ground nets for VLSI circuits, Proc.
22nd Design Automation Conf., pp. 794-797, June 1985, with S. Chowdhury.
96.
Constructing optimal test schedules for VLSI circuits having built-in test
hardware, Digest 15th Int’l. Symposium on Fault-Tolerant Computing, pp. 165170, June 1985, with M. Abadir.
97.
A knowledge based system for designing testable VLSI chips, IEEE Design and
Test of Computers, vol. 2, no. 4, pp. 56-68, August 1985, with M. Abadir.
98.
A methodology for the design of testable VLSI chips, Proc. IEEE Workshop on
Simulation and Test Generation Environments, pp. 7-38, Sept. 17-18, 1985.
99.
Test schedules for VLSI circuits, IEEE Trans. on Computers, vol. C-35, pp. 361367, April 1986, with M. Abadir.
100.
Minimal area sizing of power and ground nets for VLSI circuits, Proc. of the
Fourth MIT Conf. on Very Large Scale Integration, MIT Press, C. Leiserson
(editor), pp. 141-169, April 7-9, 1986, with S. Chowdhury.
101.
Scan path with look ahead shifting, Proc. Int’l. Test Conf., pp. 699-704,
September 1986, with M. Abadir.
102.
Roving emulation as a fault detection mechanism, IEEE Trans. on Computers,
vol. C-35, no. 11, pp. 933-939, November 1986, with A. Ismaeel.
103.
A knowledge based TDM selection system, Proc. Fall Joint Computer Conf.
(FJCC), pp. 854-863, November 1986, with X.A. Zhu.
104.
A roving emulator, Proc. 18th Annual Pittsburgh Conf. on Modeling and
Simulation, University of Pittsburgh School of Engineering, pp. 1745-1749, April
23-24, 1987, with F. Cohen.
105.
Built-in test for folded programmable logic arrays, Microprocessors and
Microsystems, vol. 11, no. 6, pp. 319-329, July/August 1987, with F. Saheban.
106.
Analysis of BIST techniques for CMOS stuck-open faults, Proc. Int’l Workshop
on Designing for Yield, University of Oxford, July 1-3, 1987, with S. Sastry.
Republished in Yield Modeling and Defect Tolerance in VLSI, edited by W.
Moore et al., Adam Hilger, Publ., Bristol and Philadelphia, pp. 249-259, 1988.
107.
Test schedules for VLSI circuits having built-in test hardware, Int’l. Journal of
Computers and Mathematics with Applications, vol. 13, no. 5-6, pp. 519-536,
1987, with M. Abadir.
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108.
An O(n) algorithm for width determination of power/ground routes for VLSI
circuits, Integration, The VLSI Journal, vol. 4, pp. 345-355, 1986, with S.
Chowdhury.
109.
Minimal area design of power/ground nets having graph topologies, IEEE Trans.
on Circuits and Systems, vol. CAS-34, no. 12, pp. 1441-1451, December 1987,
with S. Chowdhury.
110.
Fault tolerance in linear systolic arrays using time redundancy, Proc. 21st Annual
Hawaii Int’l Conf. on System Sciences, vol. I, pp. 311-320, January 5-8, 1988,
with A. Majumdar and C.S. Raghavendra.
111.
Optimization algorithms for a class of nonlinear programming problems, Int’l.
Journal of Computers and Mathematics with Applications, vol. 14, no. 3, pp. 175184, 1988, with S. Chowdhury.
112.
An object-oriented CAD database for VLSI circuits, Proc. of Vbase User’s Group
Meeting and Workshop on Object Oriented Databases, May 10-11, 1988, and
publ. by Ontologic Inc., 47 Manning, Billerical MA, with W. Cheng, R. Gupta, I.
Hardonag, E. Horowitz and S.Y. Lin.
113.
Optimal design of IC power/ground nets subject to reliability constraints, IEEE
Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no.
7, pp. 787-796, July 1988, with S. Chowdhury.
114.
A knowledge based selection system, presented at the Int’l Conf. on Applications
of Artificial Intelligence in Engineering (AIENG), August 1988, and publ. in
Artificial Intelligence in Engineering: Robotics and Processes, J.S. Gero,
editor, Elsevier Press, pp. 237-295, 1988, with X.A. Zhu.
115.
Analysis of testable PLA designs, IEEE Design and Test of Computers, vol. 5, no.
4, pp. 14-28, August 1988, with X.A. Zhu.
116.
Detectability of CMOS stuck-open faults using random and pseudo-random test
sequences, IEEE Trans. on Computer-Aided Design of Integrated Circuits and
Systems, vol. 7, no. 9, pp. 933-946, September 1988, with S. Sastry.
117.
AI Aspects of TEST: A system for designing testable VLSI chips, Proc. IFIP
Workshop on Knowledge Based Systems for Test and Diagnosis, Grenoble,
France, pp. 29-75, September 27-29, 1988, with Rajesh Gupta and Rajiv Gupta;
and republished in Knowledge based systems for test and diagnosis, G. Saucier,
A. Ambler and M.A. Breuer, editors, Elsevier Science Pub., North Holland Press
1989, pp. 31-76.
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118.
Knowledge based systems for test and diagnosis, Proc. IFIP Workshop on
Knowledge Based Systems for Test and Diagnosis, Grenoble, France, pp. 4-28,
September 27-29, 1988, with Rajesh Gupta, Rajiv Gupta, K.J. Lee and J.C. Lien;
and republished in Knowledge based systems for test and diagnosis, G. Saucier,
A. Ambler and M.A. Breuer editors, Elsevier Science Pub., North Holland Press
1989, pp. 31-76.
119.
Concurrent control of multiple BIT structures, Proc. Int’l Test Conf., pp. 431-442,
September 1988, with R. Gupta and J.C. Lien.
120.
A test and maintenance controller for a module containing testable chips, Proc.
Int’l Test Conf., pp. 502-513, September 1988, with J.C. Lien.
121.
A knowledge-based system for selecting test methodologies, IEEE Design and
Test of Computers, vol. 5, no. 5, pp. 41-59, October 1988, with X.A. Zhu.
122.
A methodology for the design of hierarchically testable and maintainable digital
systems, Proc. 8th Digital Avionics Systems Conference (DASC), pp. 40-47,
October 17-20, 1988, San Jose, CA, with J.C. Lien.
123.
The POTATO chip architecture: A study in tradeoffs for signal processing chip
design, Proc. IEEE Int’l Conf. on Computer Design (ICCD), pp. 508-513,
October, 1988, with R. Jain, A.C. Parker, C. Raghavendra, B. Sharma and C.Y.
Tseng.
124.
Fault tolerance and testing aspects of an architecture for a generalized sidelobe
cancellor, Proc. IEEE Int’l Conf. on Computer Design (ICCD), pp. 514-519,
October 1988, with A. Majumdar and C.S. Raghavendra.
125.
Cbase 1.0: A CAD database for VLSI circuits using object oriented technology,
Proc. IEEE Int’l Conf. on Computer Aided Design (ICCAD), pp. 392-395,
November 1988, with W. Cheng, R. Gupta, I. Hardonag, E. Horowitz and S.Y.
Lin.
126.
Test aspects of the JPL Viterbi decoder, The Telecommunications and Data
Acquisition Progress Report 42-96, October-December 1988, E.C. Pasner ed.,
JPL, pp. 59-79, February 5, 1989.
127.
Optimal routing of two rectangular blocks, IEEE Trans. on Computer-Aided
Design of Integrated Circuits and Systems, vol. 8, pp. 413-430, April 1989, with
M. Chandrasekhar.
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128.
An object-oriented VLSI CAD framework: A case study in rapid prototyping,
Computer, vol. 22, no. 5, pp. 28-37, May 1989, with W.H. Cheng, Rajiv Gupta,
Rajesh Gupta, and I. Hardonag. Reprinted in Object-Oriented Databases, edited
by E. Nahouraii and F. Petry, IEEE Computer Society Press, Los Alamitos, CA,
pp. 41-50, 1991.
129.
A universal test and maintenance controller for modules and boards, IEEE Trans.
on Industrial Electronics, vol. 36, no. 2, pp. 231-240, May 1989, with J.C. Lien.
Reprinted in The test access port and boundary-scan architecture, C. Maunder
and R. Tulloss, IEEE Computer Society Press, pp. 279-288, 1990.
130.
BALLAST: A methodology for partial scan design, Proc. Int’l. Symp. on FaultTolerant Computing, pp. 118-125, June 1989, with Rajesh Gupta and Rajiv
Gupta.
131.
An efficient implementation of the BALLAST partial scan architecture, IFIP
Int’l. Conf. on Very Large Scale Integration (VLSI 89), pp. 133-142, August 1618, 1989, with Rajesh Gupta and Rajiv Gupta.
132.
Knowledge based systems for test and diagnosis, Elsevier Science Publishers,
North Holland Press 1989, co-edited with G. Saucier and A. Ambler.
133.
Fault tolerance in linear systolic arrays using time redundancy, IEEE Trans. on
Computers, vol. 39, no. 2, pp. 269-276, February 1990, with A. Majumdar and
C.S. Raghavendra.
134.
The BALLAST methodology of structured partial scan design, IEEE Trans. on
Computers, vol. 39, no. 4, pp. 538-544, April 1990, with R. Gupta.
135.
An extensible user interface for an object-oriented VLSI CAD framework, Proc.
First Int’l Conf. on Systems Integration, Morristown, NJ., pp. 559-567, April 2326, 1990, with Rajiv Gupta.
136.
A universal test sequence for CMOS scan registers, Proc. Custom Integrated
Circuits Conf., May 1990, pp. 28.5.1-28.5.4, with K.J. Lee.
137.
On detecting single and multiple bridging faults in CMOS circuits using the
current supply monitoring method, Proc. Int’l. Symp. on Circuits and Systems, pp.
5-8, May 1990, with K.J. Lee.
138.
Obstacles and an approach towards concurrent engineering, Proc. Int’l. Test
Conf., pp. 260-261, September 1990.
139.
On the charge sharing problem in CMOS stuck-open fault testing, Proc. Int’l. Test
Conf., pp. 417-426, September 1990, with K.J. Lee.
14
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140.
SIESTA – Advanced serial scan design for testability, Proc. TECHCON ’90
(Semiconductor Research Corp.), pp. 403-406, October 1990, with Rajesh Gupta.
141.
A new method for assigning signal flow directions to MOS transistors, Proc. Int’l.
Conf. on Computer Aided Design, (ICCAD), pp. 492-495, November 1990, with
K.J. Lee and Rajiv Gupta.
142.
Digital System Testing and Testable Design, W.H. Freeman and Company,
New York, NY, 1990, with M. Abramovici and A.D. Friedman. Republished by
the IEEE Press, 1995.
143.
Applications of AI in TEST – A system for designing testable VLSI circuits, Int’l.
Journal of Computer Aided VLSI Design, vol. 3, no. 2, pp. 137-171, 1991, with
Rajesh Gupta and Rajiv Gupta.
144.
Maximal diagnosis for wiring networks, Proc. Int’l. Test Conf., pp. 96-105, 1991,
with J.C. Lien.
145.
The development of a framework for VLSI CAD, in Object-Oriented Databases
with Applications to CASE, Networks, and VLSI CAD, edited by Rajiv Gupta
and Ellis Horowitz, Prentice Hall, pp. 237-260, 1991, with Rajiv Gupta, Rajesh
Gupta, W. Cheng, I. Hardonag, S.P. Lin, E. Horowitz.
146.
The Handbook of Fault Simulation, Zycad Corporation (publisher), Menlo
Park, California, 1991, with S. Sapiro.
147.
Partitioning and reorganization of hierarchical circuits for DFT, Proc. Int’l. Symp.
on VLSI Design, New Delhi, pp. 106-111, January 1991, with Rajiv Gupta and R.
Srinivasan.
148.
The probability of error detection in sequential circuits using random test vectors,
Journal of Electronic Testing: Theory and Applications (JETTA), vol. 1, no. 4, pp.
245-256, January 1991, with A. Ismaeel.
149.
An optimal scheduling algorithm for testing board interconnect using boundary
scan, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 2, no.
1, pp. 117-130, March 1991, with J.C. Lien.
150.
A partitioning method for achieving maximal test concurrency in pseudoexhaustive testing, Proc. VLSI Test Symp., pp. 34-39, April 1991, with R.
Srinivasan and C.A. Njinda.
151.
Constraints for using IDDQ testing to detect CMOS bridging faults, Proc. VLSI
Test Symposium, pp. 303-308, April 1991, with K.J. Lee.
15
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152.
On applying circular self-test path (CSTP) technique to circuits, Proc. Custom
Integrated Circuits Conf., pp. 17.7.1-17.7.4, May 1991, with C.A. Njinda and R.
Srinivasan.
153.
A self-adaptive expert selection systems (SAESS) and its application to selection
problems, Proc. 3rd Int’l. Conf. on Software Engineering and Knowledge
Engineering, pp. 116-121, June 27-29, 1991, with S.P. Lin and C.A. Njinda.
154.
Reorganizing circuits to aid testability, IEEE Designs & Test of Computers, vol.
8, no. 3, pp. 49-57, September 1991, with R. Gupta and R. Srinivasan.
155.
A systematic approach for designing testable VLSI circuits, Int’l. Conf. on
Computer-Aided Design (ICCAD), pp. 496-499, November 1991, with S.P. Lin
and C.A. Njinda.
156.
Ordering storage elements in a single scan chain, Proc. Int’l. Conf. on ComputerAided Design (ICCAD), pp. 408-411, November 1991, with Rajesh Gupta.
157.
Synthesis of optimal 1-hot coded on-chip controllers, Int’l. Conf. Computer-Aided
Design (ICCAD), pp. 236-239, November 1991, with D. Mukherjee and C.
Njinda.
158.
Self-diagnosis of regular arrays of processors, Journal of Computer & Electrical
Engineering, vol. 18, no. 2, pp. 159-171, 1992, with F. Saheban.
159.
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging
faults, IEEE Trans. on Computer-Aided Design, vol. 11, no. 5, pp. 659-670, May
1992, with K.J. Lee.
160.
SWiTEST: A switch level test generation system for CMOS combinational
circuits, Proc. Design Automation Conf., pp. 26-129, June 1992, with K.J. Lee
and C.A. Njinda.
161.
Optimal sequencing of scan registers, Proc. Int’l. Test Conf., pp. 293-302,
September 1992, with S. Narayanan and C. Njinda.
162.
SIESTA: A multi-facet scan design system, Proc. European Design Automation
Conf., pp. 246-251, September 1991, with S. Narayanan, C. Njinda and R. Gupta.
163.
Minimal area merger of finite state machine controllers, Proc. European Design
Automation Conf., pp. 278-283, September 1992, with D. Mukherjee and M.
Pedram.
164.
A fully integrated CAD environment for designing testable VLSI circuits, Proc.
WESCON Technical Conf., pp. 224-230, November 1992, with C.A. Njinda and
S.L. Lee.
16
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165.
A partially distributed control scheme for DFT/BIST hardware, Proc. WESCON
Technical Conf., pp. 673-679, November 1992, with D. Mukherjee and C. Njinda.
166.
Configurating multiple scan chains for minimum test time, Proc. Int’l. Conf. on
Computer Aided Design, pp. 4-8, November 1992, with S. Narayanan and R.
Gupta.
167.
Testability properties of acyclic structures and applications to partial scan design,
Proc. IEEE VLSI Test Symp., pp. 49-54, April 1992, with R. Gupta.
168.
Teaching computer hardware using commercial CAD tools, IEEE Trans. on
Education, vol. 36, no. 1, pp. 158-163, February 1993, with G. Puvvada.
169.
Test program synthesis for modules and chips having boundary scan, J.
Electronic Testing: Theory and Applications (JETTA), vol. 4, pp. 159-180, 1993,
with J.C. Lien.
170.
Generating a family of testable designs using the BILBO methodology, J.
Electronic Testing: Theory and Applications (JETTA), vol. 4, pp. 71-89, 1993,
with S.P. Lin and C.A. Njinda.
171.
An efficient partitioning strategy for pseudo-exhaustive testing, Proc. Design
Automation Conf., pp. 242-248, June 1993, with R. Srinivasan and S. Gupta.
172.
Optimal configuration of multiple scan chains, IEEE Trans. on Computers, vol.
42, no. 9, pp. 1121-1131, September 1993, with S. Narayanan and R. Gupta.
173.
Novel test pattern generators for pseudo-exhaustive testing, Proc. Int’l Test Conf.,
pp. 1041-1050, October 1993, with R. Srinivasan and S. Gupta.
174.
Reconfigurable scan chains: A novel approach to reduce test application time,
Proc. Int’l. Conf. on Computer Aided Design (ICCAD), pp. 710-715, November
1993, with S. Narayanan.
175.
Merging multiple FSM controllers for DFT/BIST hardware, Proc. Int’l. Conf. on
Computer Aided Design (ICCAD), pp. 720-725, November 1993, with D.
Mukherjee and M. Pedram.
176.
Test embedding with discrete logarithms, IEEE VLSI Test Symp., pp. 74-80, April
1994, with M. Lempel and S.K. Gupta.
177.
Extraction of a high-level structural representation from circuit descriptions with
applications to DFT/BIST, Proc. Design Automation Conf., pp. 345-350, June
1994, with I. Parulkar and C.A. Njinda.
17
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178.
A low cost BIST methodology and a novel test pattern generator design, Proc.
European Design and Test Conf., pp. 106-112, February 1994, with S-P. Lin and
S.K. Gupta.
179.
SWiTEST: A switch level test generation system for CMOS combinational
circuits, IEEE Trans. on Computer Aided Design, vol. 13 pp. 625-637, May 1994,
with K.J. Lee and C.A. Njinda.
180.
Control strategies for chip-based DFT/BIST hardware, Proc. Int’l. Test Conf., pp.
893-902, October 1994, with D. Mukherjee and M. Pedram.
181.
BITS – an integrated CAD system to automate built-in self-test (BIST) of VLSI
circuits, Proc. Government Microcircuit Applications Conf. (GOMAC), pp. 43-46,
Nov. 1994, with S-P. Lin.
182.
Asynchronous multiple scan chains, 13th IEEE VLSI Test Symp., pp. 270-276,
April 1995, with S. Narayanan.
183.
Test embedding with discrete logarithms, IEEE Trans. on Computer-Aided
Design, vol. 14, no. 5, pp. 554-586, May 1995, with M. Lempel and S. Gupta.
184.
Reconfiguration techniques for a single scan chain, IEEE Trans. on Computer
Aided Design, vol. 14, no. 6, pp. 750-765, June 1995, with S. Narayanan.
185.
Partial scan design of register-transfer level circuits, J. Electronic Testing: Theory
and Applications, vol. 7, no. 1/2, pp. 25-46, Aug/Oct 1995, with Rajesh Gupta.
186.
An integrated system for assigning signal flow directions to CMOS transistors,
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.
14, no. 12, pp. 1445-1458, Dec. 1995, with K-J. Lee, C-N. Wang and R. Gupta.
187.
Data path allocation for synthesizing RTL design with low BIST area overhead,
Proc. Design Automation Conf., pp. 395-401, June 1995, with I. Parulkar and S.
Gupta.
188.
Lower bounds on test resources for scheduling data flow graphs, Proc. Design
Automation Conf., pp. 143-148, June 1996, with I. Parulkar and S. Gupta.
189.
Process aggravated noise (PAN): new validation and test problems, Proc. Int’l.
Test Conf., pp. 914-923, October 1996, with S.K. Gupta.
190.
High quality robust tests for path delay faults, IEEE VLSI Test Symp., pp. 88-93,
April 1997, with L-C. Chen and S.K. Gupta.
191.
Analysis of ground bounce in deep sub-micron circuits, IEEE VLSI Test Symp.,
pp. 110-116, April 1997 with Y-S. Chang and S.K. Gupta.
18
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192.
A unified approach for the synthesis of scalable and testable embedded
architectures, Proc. 2nd Annual Workshop on Fault-Tolerant Parallel and
Distributed Systems, pp. 34-53, April 5, 1997, with P. Bhat, C. Aktouf, V.
Prasanna and S. Gupta, and republished in Fault-Tolerant Parallel and
Distributed Systems, ed. D. Avresky and D. Kaeli, Kluwer Academic Publishers,
pp. 213-220, 1998.
193.
Fast optimal diagnosis procedures for k-out-of-n systems, IEEE Trans. on
Reliability, vol. 46, no. 2, pp. 283-290, June 1997, with S. Salloum.
194.
Analytic models for crosstalk delay and pulse analysis for non-ideal inputs, Proc.
Int’l. Test Conf., pp. 809-818, November 1997, with W-Y. Chen and S.K. Gupta.
195.
Introducing redundancy in RTL data paths to reduce BIST resources, Proc. IEEE
Int’l. High Level Design Validation and Test Workshop, pp. 53-59, Nov. 14-15,
1997, with I. Parulkar and S.K. Gupta.
196.
Scheduling and module assignment for reducing BIST resources, The Design
Automation and Test in Europe Conf. 1998, pp. 66-73, Feb. 23-26, 1998, with I.
Parulkar and S.K. Gupta. (Nominated for Best Paper Award)
197.
Introducing redundant computations in a behavior for reducing BIST resources,
Proc. Design Automation Conf., pp. 548-553, June 1998, with I. Parulkar and
S.K. Gupta.
198.
Testing a K-ary N-cube interconnection network, 4th IEEE Int’l. On-line Testing
Workshop, pp. 12-16, July 1998, Capri, Italy, with S. Kumarasamy and S.K.
Gupta.
199.
Bounds on pseudo-exhaustive test lengths, IEEE Trans. on VLSI Systems, vol. 6,
no. 3, pp. 420-431, September 1998, with R. Srinivasan and S.K. Gupta.
200.
Allocation techniques for reducing BIST area overhead of data paths, J.
Electronic Testing: Theory and Applications (JETTA), vol. 13, no. 2, pp. 149-166,
Oct. 1998, with I. Parulkar and S.K. Gupta.
201.
Test generation on VLSI circuits for crosstalk noise, Proc. Int’l. Test Conf., pp.
641-650, Nov. 1998, Washington, D.C., with W-Y. Chen and S.K. Gupta.
202.
Process variations and their impact on circuit operation, IEEE Int’l. Symp. on
Defects and Fault Tolerance in VLSI Systems (DET ’98), pp. 73-81, Nov. 2-4,
1998, Austin, TX, with S. Natarajan and S.K. Gupta.
19
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203.
An IEEE 1149.1 compliant test control architecture, J. Electronic Testing: Theory
and Applications (JETTA), vol. 13, no. 3, pp. 273-297, Dec. 1998, with D.
Mukherjee.
204.
Estimation of BIST resources during high-level synthesis, J. Electronic Testing:
Theory and Applications (JETTA), vol. 13, no. 3, pp. 221-237, Dec. 1998, with I.
Parulkar and S.K. Gupta.
205.
Test generation for ground bounce in internal logic circuitry, IEEE VLSI Test
Symposium, pp. 95-104, April 1999, with Y-S. Chang and S.K. Gupta.
206.
Test generation for crosstalk induced delay in integrated circuits, Proc. Int’l. Test
Conf., pp. 191-200, September 1999, with W-Y. Chen, S.K. Gupta.
207.
Switch-level delay test, Proc. Int’l. Test Conf., pp. 171-180, September 1999,
with S. Natarajan and S.K. Gupta.
208.
Intelligible testing, Proc. 4th Multimedia Technology and Applications Symp., pp
11-19, April 16, 1999, Kaohsuing, Taiwan.
209.
Intelligible testing in microprocessors, 2nd IEEE Int’l. Workshop on
Microprocessor Test and Verification, 11 pages, September 30-October 1, 1999,
with S.K. Gupta.
210.
Validation and test generation for oscillatory noise in VLSI interconnects, Proc.
Int’l Conf. on Computer-Aided Design (ICCAD), pp. 289-296, November 1999,
with A. Sinha and S.K. Gupta.
211.
Novel test pattern generators for pseudo-exhaustive testing, IEEE Trans. on
Computers, vol. 49, no. 11, pp. 1228-1240, November 2000, with R. Srinivasan
and S.K. Gupta.
212.
Fundamentals of CAD Algorithms, IEEE Trans. on Computer-Aided Design of
Integrated Circuits and Systems, vol. 19, no. 12, pp. 1449-1475, Dec. 2000, with
M. Sarrafzadeh and F. Somenzi.
213.
Test generation for crosstalk induced faults: framework and computational results,
Proc. Asian Test Symp. (ATS2000), Taipei, Taiwan, pp. 305-310, Dec. 2000, with
W-Y Chen and S.K. Gupta.
214.
A new framework for static timing analysis, incremental timing refinement, and
timing simulation, Proc. Asian Test Symp. (ATS2000), Taipei, Taiwan, pp. 329334, Dec. 2000, with L-C Chen and S.K. Gupta.
20
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215.
Test generation for maximizing ground bounce for internal circuitry with reconvergent fan-outs, IEEE Int’l. Test Symp. (VTS), pp. 358-366, April/May 2001,
with Y-S Chang and S.K. Gupta.
216.
A new gate delay model for simultaneous switching and its applications, Proc.
Design Automation Conf., pp 289-294, June 2001, with L-C Chen and S.K.
Gupta.
217.
Validation and test generation for inductance-induced noise on VLSI
interconnects, Proc. 5th IEEE Workshop on Signal Propagation on Interconnects,
May 2001, with A. Sinha and S.K. Gupta.
218.
Introducing redundant computation in RTL data paths for reducing BIST
resources, ACM Trans. on Design Automation of Electronic Systems (TODAES),
Vol. 6., No. 3, pages 423-445, July 2001,with I. Parulkar and S. K. Gupta.
219.
Crosstalk test generation on pseudo-industrial circuits: A case study, Proc. Int’l.
Test Conf., pp. 548-557, Oct. 30- Nov. 1, 2001, with L-C Chen, T. M. Mak, and
S. K. Gupta.
220.
Switch-level delay test of domino logic circuits, Proc. Int’l. Test Conf., pp. 367376, Oct. 30- Nov. 1, 2001, with S. Natarajan and S.K. Gupta.
221.
Test generation for crosstalk induced faults: framework and computational results,
Asian Test Symp., Taipei, Taiwan, pp. 305-310, Dec. 2000, with W-Y Chen and
S.K. Gupta. Republished in 10th Anniversary Compendium of Papers from Asian
Test Symposium: 1992-2001, pp. 311-316, Nov. 2001.
222.
A new framework for static timing analysis, Asian Test Symp., Taipei, Taiwan,
pp. 102-107, Dec. 2000, with L-C Chen and S.K. Gupta. Republished in 10th
Anniversary Compendium of Papers from Asian Test Symposium: 19922001, pp. 329-334, Nov. 2001.
223.
Test generation for crosstalk-induced faults: framework and computational
results, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18,
no. 1, pp. 17-28, February 2002, with W-Y Chen and S. K. Gupta.
224.
TA-PSV-Timing analysis for partially specified vectors, Journal of Electronic
Testing: Theory and Applications, vol. 18, no. 1, pp. 73-88, February 2002, with
L-C Chen and S. K. Gupta.
225.
Analytical models for crosstalk excitation and propagation in VLSI circuits, IEEE
Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21,
no. 10, pp. 1117-1131, October 2002, with W-Y Chen and S. K. Gupta.
21
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226.
Validation and test issues related to noise induced by parasitic inductance of VLSI
interconnects, IEEE Trans. on Advanced Packaging, vol. 25, no. 3, pp. 329-339,
August 2002, with A. Sinha and S. K. Gupta.
227.
Accurate and efficient static timing analysis with crosstalk, Int’l. Conf. on
Computer Design (ICCD), pp. 265-272, Sept. 2002, with I-De Hwang and S. K.
Gupta.
228.
XIDEN: Crosstalk target identification framework, Proc. Int’l. Test Conf., pp.
365-373, October 2002, with S. Nazarian, H. Huang, S. Natarajan, and S. K.
Gupta.
229.
Test generation for maximizing ground bounce considering circuit delay, IEEE
VLSI Test Symp., April-May 2003, pp. 151-157, with Y-S Chang and S. K. Gupta.
230.
Analyzing crosstalk in the presence of weak bridge defects, IEEE VLSI Test
Symp., April-May 2003, pp. 385-392, with S. Irajpour, S. Nazarian, L. Wang and
S. K. Gupta.
231.
An enhanced test generator for capacitance induced crosstalk delay faults, Proc.
Asian Test Conf., Nov. 2003, pp. 174-177, with A. Sinha and S. K. Gupta.
232.
Estimating error rate in error tolerant VLSI chips, IEEE Int’l. Workshop on
Electronic Design, Test and Applications (DELTA), January 28-30, 2004, Perth,
Australia, pp. 321-326.
233.
Defect and error-tolerance in the presence of massive numbers of defects, IEEE
Design and Test Magazine, May-June, 2004, pp. 216-227, with S. K. Gupta and
T. M. Mak.
234.
Timing-independent testing of crosstalk in the presence of delay producing
defects using surrogate fault models, Proc. Int’l. Test Conf., Oct. 2004, pp. 10241033, with S. Irajpour and S. K. Gupta.
235.
Intelligible test techniques to support error-tolerance, Asian Test Symp., Nov.
2004, pp. 386-393.
236.
Modeling and simulation for crosstalk aggravated by weak bridge defect between
on-chip interconnects, Asian Test Symp., Nov. 2004, pp. 440-447, with L. Wang
and S. K. Gupta.
237.
Efficient identification of crosstalk induced slowdown targets, Asian Test Symp.,
Nov. 2004, pp. 124-131, with S. Nazarian and S. K. Gupta.
238.
Let’s think analog, Annual Symp. on VLSI, pp. 2-5, March 2005.
22
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239.
Multi-media applications and imprecise computation, 8th Euromicro Conf. on
Digital System Design, August 30- Sept. 3, 2005, pp. 2-7. (This paper was
published in conjunction with a keynote address.)
240.
Multiple tests for each delay fault: higher coverage at lower test application costs,
Int’l. Test Conf. (ITC), Paper 47.2, 2005, with S. Irajpour and S. K. Gupta.
241.
Multiple tests for each delay fault: higher coverage at lower test application costs,
TECHCON, with S. Irajpour and S. K. Gupta. Only available on-line at:
http://www.src.org/member/event/E002364/E002364_proceedings.asp.
242.
A novel testing methodology based on error-rate to support error-tolerance, Int’l.
Test Conf. (ITC), paper 44.3, 2005, with K. J. Lee and T. Y. Hsieh.
243.
"STAX: Statistical crosstalk target set compaction," Proc. of Design Automation
and Test in Europe, Pages: 172 - 177, Mar. 2006, with S. Nazarian, M. Pedram
and S. K. Gupta.
244.
An error-oriented test methodology to improve yield with error-tolerance, VLSI
Test Symp., pp. 130–135, April 30-May 4, 2006, with T-Y Hsieh and K-J Lee.
245.
Diagnosis of delay faults due to resistive bridges, delay variations and defects,
Asian Test Symp., pp. 215-224, November 2006, with L. Wang and S. K. Gupta.
246.
Test generation for weak resistive bridges, Asian Test Symp., pp. 265-272,
November 2006, with S. Irajpour and S. K. Gupta.
247.
Error-tolerance and multi-media, IEEE Int’l. Conf. on Intelligent Information
Hiding and Multimedia Signal Processing, pp. 521-525, Dec. 18-20, 2006, with
H. Zhu.
248.
Reduction of detected acceptable faults for yield improvement via error-tolerance,
Proc. of Design Automation and Test in Europe (DATE), pp. 1599-1604, April
2007, with T.Y. Hsieh and K.J. Lee.
249.
Estimating error-rate in defective logic using signature analysis, IEEE Trans. on
Computers, vol. 56, no. 5, pp. 650-661, May 2007, with Z. Pan.
250.
Improving timing-independent testing of crosstalk using realistic assumptions on
delay faults, Asian Test Symp., pp. 57-64, October 2007, with S. Irajpour and S.K.
Gupta.
251.
Tesla and AND gates, IEEE Design and Test, page 62, Nov.-Dec. 2007.
23
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252.
Preventing over-detection of acceptable faults for yield enhancement, Int’l. J. of
Electrical Engineering, Vol. 14, No. 3, pp. 185-193, 2007, with T.Y. Hsieh and
K.J. Lee.
253.
An error-rate based test methodology to support error-tolerance, IEEE Trans. on
Reliability, vol. 57, no. 1, pp. 204-214, March 2008,with T.Y. Hsieh and K.J. Lee.
254.
Error tolerance: Why and how to use slightly defective digital systems, Proc.
IEEE Workshop on Silicon Errors in Logic and System Effects, March 26-27,
2008, Univ. of Texas, Austin, with K. Chugg, S.K. Gupta and A. Ortega.
255.
A framework for the analysis of error-tolerance, IEEE Design and Test Magazine,
vol. 25, no. 2, pp. 168-177, March/April 2008, with Haiyang Zhu.
256.
Basing acceptable error-tolerant performance on significance-based error-rate
(SBER), IEEE VLSI Test Symp., pp. 59-66, April/May 2008, , with Zhaoliang
Pan.
257.
A multi-valued algebra for capacitance induced crosstalk delay faults, Asian Test
Symp., 2008, pp. 89-96, November 2008, with A. Sinha and S.K. Gupta.
258.
Clarifying the record on testability cost functions, IEEE Design and Test of
Computers, vol. 25, no. 6, pp. 607-608, November/December 2008.
259.
An efficient multi-phase test technique to perfectly prevent over-detection of
acceptable faults for optimal yield improvement via error-tolerance, Proc. Int’l.
Symp. on VLSI Design, Automation and Test (DAT), April 27-30, 2009, Hsinchu,
Taiwan, with T.Y. Hsieh and K.J. Lee.
260.
Tolerance of performance degrading faults for effective yield improvement, Int'l.
Test Conf., Lecture paper 3.1, November 2009, with T-Y Hsieh, M. Annavaram,
S.K. Gupta and Kuen-Jong Lee.
261.
SIRUP: Switch insertion in redundant pipeline structures for yield and yield/area
improvement, Asian Test Symp., pp. 193-199, November 2009, with M. M.
Aghatabar and S.K. Gupta.
262.
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by
insertion of switches and redundant modules, Design Automation and Test in
Europe (DATE), Dresden, Germany, pp. 1249-1254, March 8-12, 2010, with M.
M. Aghatabar and S.K. Gupta.
263.
Hardware that produces bounded rather than exact results, Design Automation
Conf. (DAC), invited paper, pp. 871-876, June 13-18, 2010.
24
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264.
HYPER: a Heuristic for Yield/area imProvEment using Redundancy in SoC,
Asian Test Symp., Shanghai, China, pp. 249-254, Dec. 1-4, 2010, with M. M.
Aghatabar and S.K. Gupta.
265.
An error-tolerance-based test methodology to support product grading for yield
enhancement, IEEE Trans. Computer-Aided Design of Integrated Circuits and
Systems, Vol. 30, No. 6, pp. 930-934, June 2011, with T.-Y. Hsieh and K.-J. Lee.
266.
Theory of logical partitioning for yield/area maximization using redundancy,
IEEE Int’l. Workshop on Design for Manufacturing and Yield (DFM&Y 2011),
San Diego, CA, June 6, 2011, with M. M. Aghatabar and S. K. Gupta.
267.
Yield/area maximization of logic circuits: From theorem to implementation, IEEE
Int’l. Workshop on Defect and Adaptive Test Analysis (DATA-2011), Anaheim
CA, Sept. 22-23, 2011, with M. M. Aghatabar and S. K. Gupta.
268.
Data aware component salvaging in presence of microprocessor integer functional
unit delay faults, IEEE Int’l. Workshop on Defect and Adaptive Test Analysis
(DATA-2011), Anaheim CA, Sept. 22-23, 2011, with Y. Gao.
269.
Redundancy and partitioning for yield/area maximization, Int’l. Test Conf.,
(submitted 1/29/2011), with M.M. Aghatabar and S.K. Gupta.
270.
Theory of Redundancy for Logic Circuits to Maximize Yield/Area, Proc. of the
Int’l. Symp. on Quality Electronic Design (ISQED), Santa Clara, CA. March 1921, 2012, with M. M. Aghatabar, S. K. Gupta, and S. Nazarian.
271.
Efficient over-detection elimination of acceptable faults for yield improvement,
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.
31, No. 5, pp. 754-764, May 2012, with T.-Y. Hsieh and K.-J. Lee.
272.
Error rate estimation for defective circuits via ones counting, J. ACM Trans. on
Design Automation of Electronic Systems, Vol. 27, No. 1, Article #8, January
2012, with Z. Pan.
273.
A design flow to maximize yield/area of physical devices via redundancy, IEEE
Int’l. Test Conf. (ITC), 2012, with M. M. Aghatabar and S. K. Gupta.
274.
Theory of Redundancy for Logic Circuits to Maximize Yield/Area ", in Proc. of
the Int’l. Symp. on Quality Electronic Design (ISQED), pp. 663-671, March
2012, with M. Mirza-Aghatabar, S. K. Gupta and S. Nazarian.
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275.
Trading off area, yield and performance via hybrid redundancy in multi-core
architectures, IEEE VLSI Test Symposium, 2013, with Yue Gao, Yang Zhang,
and da Cheng.
276.
Using explicit output comparisons for fault tolerant scheduling (FTS) on modern
high-performance processors, Design Automation and Test in Europe (DATE),
2013, with Y. Gao and S. K. Gupta.
277.
A New Paradigm for Trading Off Yield, Area and Performance to Enhance
Performance per Wafer, in Proc. Design, Automation and Test in Europe
Conference (DATE), 2013, with Y. Gao and Yanzhi Wang.
278.
Using Explicit Output Comparisons for Fault Tolerant Scheduling on Modern
High-Performance Processors, in Proc. Design, Automation and Test in Europe
Conference (DATE) 2013, with Y. Gao and S.K. Gupta.
279.
ACCEPTED FOR PUBLICATION BUT NOT YET PUBLISHED
1. GLYFF: A Framework for Global Yield and Floorplan Aware Design
Optimization, 16th International Symposium on Quality Electronic Design
(ISQED),March 2015, with Shuo Wang and Yue Gao.
SUBMITTED FOR PUBLICATION
2. Performance Optimization and Analysis of Blade Designs under Delay
Variability, Dec. 2014, ASYNC Conference, with Dylan Hand, Benmao Cheng,
Yang Zhang, Matheus Trevisan Moreira, Hsin-Ho Huang, Ney Laert Vilar
Calazans and Peter Beerel,
3. Design and Analysis of Testable Mutual Exclusion Elements, Dec. 2014, ASYNC
Conference.
4. Blade - A Timing Violation Resilient Asynchronous Template, Dec. 2014, ASYNC
Conference. with Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei
Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Ney Laert Vilar
Calazans, and Peter Beerel.
26
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Poster Session
Theory of Logical Partitioning for Yield/Area Maximization using Redundancy,
submitted 3/21/2011 to DFM&Y 2011, with M.M. Aghatabar and S.K. Gupta.
Presentations
1. Let’s think analog, Keynote address, IEEE Computer Society Annual Symp. on
VLSI (ISVLSI 2005.)
2. Let’s address the right test problems, TTTC Technical Forum in Honor of
Professor Sudhakar Reddy, November 10-11, 2005, Austin TX.
3. Error tolerance: Why and how to use slightly defective digital systems, IEEE
Workshop on Silicon Errors in Logic and System Effects (SELSE 4), March 26,
2008, Univ. of Texas, Austin TX.
4. Error-tolerance, Keynote address, 26th IEEE VLSI Test Symp. (VTS), April 28,
2008, San Diego CA.
5. Performance degradation tolerance, Invited presentation, Int’l. Test Conf. (ITC),
October 28, 2008, San Jose, CA.
6. Tolerance of performance degrading faults for effective yield improvement, Int'l.
Test Conf. (ITC), Lecture paper 3.1, November 2009, San Jose, CA.
7. Algorithms to maximize yield and enhance yield/area of pipeline circuitry by
insertion of switches and redundant modules, Design Automation and Test in
Europe (DATE), March 11, 2010, Dresden, Germany.
8. Hardware that produces bounded rather than exact results, Design Automation
Conf. (DAC), invited paper, June 13-18, 2010, Anaheim CA.
9. Novel ways to use future SoC technologies, 8th Int’l. System-on-Chip (SoC),
November 3, 2010, Irvine CA.
10. HYPER: a Heuristic for Yield/area improvement using Redundancy in SoC,
Asian Test Symp. (ATS), Dec. 3, 2010, Shanghai, China.
11. The 3R’s: Reliability, redundancy and reconfiguration, 3rd Design for Reliability
and Variability Workshop, May 4, 2011, Dana Point CA.
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