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Design and Testing of a Self-Powered 3-D
Integrated SOI CMOS System
Zeynep Dilli, Student Member, IEEE, Neil Goldsman, Martin Peckerar and George Metze

Abstract—A self-powering 3-D integrated circuit built using a
SOI CMOS process is presented.
Design questions and
bottlenecks are discussed, with simulation results demonstrating
the circuit as a feasible proof-of-concept system. After a review
of measurement issues, test results are given, which demonstrate
the system operating as designed: A photodiode array powering
an oscillator.
Index Terms—CMOS wireless sensor networks, photocells,
photodiodes, self-powered devices, SOI.
I. INTRODUCTION
W
E present the design and testing of a three-dimensional
integrated circuit (3-DIC), incorporating energy
harvesting and storage units along with a functional block. In
the context of wireless sensor network technology, a vivid
question is how to power their individual nodes. Low-power
designs, and integrated power sources or self-powering, are
items of interest [1]. 3-D integration is promising for this
technology, with its possibilities of tighter system-level
integration, lower noise coupling between subsystems and
lower connection parasitics; thus we explore a 3-D
implementation.
Some approaches to power-harvesting from ambient energy
are thermoelectric generators, rectifying antennas and
photocells [2, 3]. Our system uses photocells, designed as
photodiode arrays with a charge-integrating capacitor. Our
power-harvesting structure does not take up active silicon
space meant for functional electronics thanks to chip stacking
by 3-D integration.
II. SYSTEM OVERVIEW
Figure 1 displays the placement of different elements in our
stack:
 The bottom tier: Functional elements; specifically a
local oscillator and an output buffer.
 The middle tier: Storage elements; specifically an
integrating capacitor.
 The top tier: Sensor elements; specifically an array
of photodiodes for power-harvesting.
We can visualize different implementations of these general
Zeynep Dilli, Neil Goldsman and Martin Peckerar are with the Department
of Electrical and Computer Engineering, University of Maryland College
Park, College Park, MD 20742 (e-mail: dilli@eng.umd.edu).
George Metze is with the Laboratory for Physical Sciences, College Park,
MD, 20740.
Fig. 1. A 3-D system design concept: Sensor, storage and electronics layers.
Elements in our specific design are shown here.
functions. Data sensors (e.g. photosensors or antenna circuitry)
as well as power harvesters could be placed on the top tier,
with data storage and preliminary/mixed-signal circuits (e.g.
A/D converters) on the second tier and back end/data
processing circuitry on the bottom layer.
Our design is intended for the novel three-tiered 3-DIC
process of MIT Lincoln Labs, based on their 0.18 μm fullydepleted silicon-on-insulator (FDSOI) process. Each tier is
individually fabricated as a planar IC. For the final assembly,
the top two tiers are flipped over for stacking, their handle
wafers removed. Dense tungsten vias through intertier oxide
layers provide tier-to-tier connections, with bonding pads
obtained by overglass cuts from the top tier backside to the
first metal layer.
III. PHOTODIODE DESIGN AND LAYOUT
The main concern in the design of the photodiode array in
our system is obtaining the maximum photocurrent within our
assigned design area of 250 μm by 250 μm. A theoretical
calculation [6] yields an expectable ~6.6 nA photocurrent
under red light with 1000 W/m2 intensity, the prominent
bottleneck being the 50 nm silicon depth of this SOI process,
allowing only about 1.7% absorption.
We designed two photodiode types with the available layers
in the process. The first type uses ``intrinsic'' (very low-doped
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Fig. 3. Simulation results. The inset depicts the beginning of the oscillation
(between 320 μs and 360 μs) and the main figure body shows full oscillation.
In both the inset and the main figure, the voltage scale is between -50 mC and
300 mV, and the dashed line is the rail voltage, which ha sreached a steady
state of about 242 mV in this simulation. The lighter solid line is the ring
oscillator output feeding the buffer and the thick solid line is buffer output.
IV. CIRCUIT ANALYSIS AND SIMULATIONS
Fig. 2. Top: The pin- (left) and pn- (right) diode layouts (not to scale).
Bottom: The fabricated chip, top layer microphotograph. To the left, top: The
VDD pad, bottom: the GND pad. The pin-diode array is next to the VDD
pad. To the right, the output pad. The rest is the annular pn-diode array. The
vertical via arrays from the VDD and GND pads to the lower layers are to
their right; the vertical via to the output pad from the lower layers is to its top.
Lower tiers are somewhat visible, but out of focus, at the edges of the bonding
pads, where there is no layout in the top tier.
p-type, NA1014 cm-3) silicon and the n-type threshold
adjustment implant, ND=51017 cm-3. This pin-diode depletion
region width is about 1.5 μm. Making the junction 10 μm wide
yields about 99.5 pA per diode. However, this ``intrinsic''
layer is not recommended for use [7]: Its regions are
vulnerable to surface accumulation or inversions, which would
alter diode operating characteristics. Thus, we do not rely
solely on this type of diode, although 52 are present in an array
in the final design.
The second type is formed by the junction between the nand p-type threshold adjust implants, NA=ND=51017 cm-3. We
use an annular layout to maximize junction area and total
diode number, 2062 in the final design. Fig. 2 displays the
diode layouts and the microphotograph of the fabricated chip.
After fabrication, total circuit volume is 250250700 μm3.
The functional block of our circuit is a three-stage local
oscillator, formed by inverters in a ring-oscillator
configuration. We chose minimum-size NMOS transistors to
minimize current requirements, the PMOS size set for a
midrange switching point. We also have a two stage output
buffer. The circuit is displayed in Fig. 1.
Fig. 3 shows a simulation of the circuit operation with the
output bonding pad as the load (~15 fF) [8]. The
photocurrent, charging the storage capacitor Cst, builds up the
inverters' rail voltage. Inverter output (and thus, input)
voltages follow; at a certain level, the local oscillator has
sufficient gain to amplify noise and start oscillation. From this
point on all inverters are drawing current, which increases with
rising rail voltage until the current consumption balances the
photocurrent charging Cst and rail voltage stabilizes. Higher
assumed photocurrents in the simulation yield higher rail
voltages.
In practice, two more factors affect operation. The first is
that the rail voltage forward-biasing the diodes too, which then
themselves sink some current. Our calculations indicate that
this will limit rail voltage, for normal illumination, to below
0.4 V. At the cost of harvested power per area, this problem
might be addressed by multiple photodiodes in series or
alternate current transfer circuits [9]. The second is the extra
load for measurements, discussed below.
V. MEASUREMENTS
Fabricated chips, received as bare dies, were wire-bonded to
open SOIC-type packages. Our layout allows for measuring
the rail voltage across the VDD/GND pads and the
oscillator/buffer output through the output pad.
A. Rail Voltage Measurements
Of the seven bonded samples, all exhibit some voltage
across Cst, although for some the level is higher than the
others. The high level is about 300 mV under the beam from a
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red laser pointer Pin <330 W/m2 and 40 to 80 mV under a
white LED flashlight. Steady voltages around 100 mV were
observed in a sunlit room. For the laser pointer Pin, the
calculated expected current would be ~5 nA, which in
simulations yields a lower rail voltage. The disparity is
probably due to multiple absorptions, as light is reflected back
from the lower tier metal layers.
It is possible to damage samples working at the higher level
so that they begin to yield lower voltages, sometimes by toobright illumination. A credible problem is contamination; the
more likely cause is pin-junction damage by the forwardbiasing effect and high currents.
3
the input of a non-inverting amplifier of gain $\sim$23,
equivalently a 1 pF load.
Fig. 4 displays scope screen captures of the amplifier output
when the 3-DIC is under low illumination (only fluorescent
room lights) and under a laser beam. In the former case, the
DC level of the observed noise signal is at about 40 mV. In
the latter case, the observed peak amplitude varies between 70130 mV, with the bottom level at ~39 mV. Taking the
amplifier gain into account, this indicates a 3-DIC buffer
output amplitude of the order of 4.3 mV, consistent with
simulation results for a 1 pF load. The oscillation frequency is
1.8 MHz. Thus we demonstrate that the oscillator is indeed
operating and the steady rail voltages presented in the previous
section are not merely the photocurrent discharging from Cst
through the voltmeter.
VI. CONCLUSION
We have demonstrated the operation of a self=powered
three-dimensional integrated circuit. In the design stage, our
simulations had shown this system as a feasible self-powered
system proof-of-concept. The 3-DIC functions satisfactorily
within the design limitations, the deviations from the expected
behavior being mainly favorable and explainable by using the
physical realities of the chip.
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Fig. 4. Top: Amplifier output with 3-DIC under low-level illumination. The
maximum signal amplitude is ~10 mV, with a ~40 mV DC component.
Bottom: With 3-DIC under laser pointer light. The maximum signal
amplitude is 130 mV, and dominant frequency is 1.8 MHz.
B. Oscillator Output
Inherent current limitations prohibited the design of a buffer
capable of driving high capacitive or low resistive loads. In
particular, our active scope probe specifies a load resistance of
20K and capacitance of 1 pF, which when included in
simulations allows no meaningful output voltage level.
Therefore, to be able to observe the self-powered circuit
operation, we added an external amplifier stage built around a
commercial low input bias current CMOS op-amp
(LMH6601). The oscillator buffer output was connected to
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