Instrumentation Laboratory Workshop
Les journées du Laboratoire Instrumentation
JLINS’2012, 30 et 31 Octobre 2012, USTHB, Algiers, Algeria
Preparation of Papers for JLINS’2012
Proceedings (IEEE Format)
First Author, Second Author and Third Author

Abstract
—
A
low-noise
and
high-bandwidth
Transimpedance Amplifier (TIA) at 2.75 GHz has been
implemented in 0.35 μm CMOS technology. The designed
amplifier is configured on three identical stages that use an
active load. This structure operates at 3.3V power supply
voltage, displays a transimpedance gain of 531 Ω, exhibits a
gain bandwidth product (GBW) of 1.46 THzΩ and a low-noise
level of about 12.8 pA Hz , while operating with a
photodiode capacitance of 0.4 pF. The predicted performance is
verified using simulations tools with 0.35 μm CMOS AMS
parameters.
Index Terms — Receiver, CMOS Technology, Layout.
loop gain of the amplifier, whereas when transmission
speed is increased, the number of stages composing the
amplifier as well as its open loop gain is necessarily
reduced [3]. The TIA must be designed carefully to avoid
stability problems associated to systems with negative
feedback [3].
Though the traditional TIA is designed using more
expensive IC technologies such as silicon bipolar or GaAs
MESFET, there has been an increasing interests in CMOS
based implementation because of the demand for the
lower cost and greater integration with digital circuits.
I. INTRODUCTION
II. DESIGN OF THE TRANSIMPEDANCE AMPLIFIER
T is challenging to design a good current to voltage
(transimpedance) amplifier for high transfer rate
optical transmission, such as LAN (Local Area Networks)
and FTTH (Fiber-To-The-Home). The performance of the
optical interconnection system depends on the receiver’s
gain, bandwidth, power consumption, and noise. These
four parameters tend to trade-off with each other [1]. The
front-end component of typical optical receiver generally
is a Voltage-Feedback Amplifier (VFA). The typical
amplifier generally requires a low-noise characteristic in
order to achieve a good noise figure performance and
should operate as high dynamics against the input signal.
To meet the noise requirement, two different types of
amplifier architectures are proposed [2]. The first one is a
low noise amplifier with high input impedance witch can
provide lower noise, but bandwidth can be reduced
significantly due to the longer input RC time constant.
The second one, so called the transimpedance amplifier
(TIA) use a resistive shunt-shunt feedback (Fig. 1.), where
CPD, CS, and CG are respectively the photodiode, parasitic
and gate capacitances that represent the total capacitance
at the input (CT). Instead of HIA, the TIA has more noise
due to feedback resistance but a wide bandwidth and the
designing circuit is simpler.
A push pull inverter at the input is used to maximize the
transconductance of the amplifier and increases its gain
bandwidth product (GBP) [4, 8]. An improved one stage
CMOS implementation of the TIA is presented in Fig. 2.
I
Fig. 1. Model of a closed loop TIA with photodiode
The bandwidth can be improved by increasing the open
Manuscript received January 25, 2010. This work was supported in
part by the MESRS Ministry under Grant J0200220090020. First
Author is with the Laboratory of Instrumentation, USTHB, PO.Box. 32,
Bab-Ezzouar, Algies, Phone: 213-24217912 (Ext. 804), Fax: 21321207664,
URL:
http://www.lins.usthb.dz,
Email:
attari.mo@gmail.com. Second Author is also with the Laboratory of
Instrumentation, USTHB, PO.Box.32, Bab-Ezzouar, Algies.
Fig. 2. The proposed CMOS TIA circuit
The TIA takes a current from the input and converts it
into a voltage signal. The transistors M1 and M3 form the
inverter while M2 is added to increase the bandwidth and
minimize the Miller effect. To design such an amplifier,
by knowing that the gain can be approximated by the
value of the feedback resistor, we evaluate RF while
estimating CT. These two parameters will be used as
starting point in the design. The gain of the inverter will
be exploited in addition to the negative feedback, which
will impose an increase in the gain. Thus, from the small
signal model, the expression of the gain will be,
V
g  gm3
AOL  out  m1
Vin
gm2
(1)
The cut-off frequency at 3 dB is increased by the
transconductance of M2 as long as the gain is
simultaneously reduced. The signal should be amplified
through subsequent amplifiers because of the low-gain of
the single amplifier stage. Then, we will have,
AOL   
where :

W1 L1
W2 L2
µp
µn
et
 1   

(2)
W3 L3
W2 L2
The complete improved transimpedance amplifier (Fig.
3.) consists of three identical cascaded stages. We can use
a resistor as a feedback or a PMOS transistor as an active
feedback resistor biased by the voltage source VG [4, 5].
The feedback resistor will be determined using,
RF 
1
W
µCox VGS  VT 
L
3
1  AOL
1  AG

2 RF CT 2 RF CT
Fig. 4. Capacitances involved in one amplifier stage
f1 
gm2
2C2
(5)
(3) By using Eq. 1, the cut-off frequency at node (2) will be
expressed as follow,
With taking into account the Miller Effect, the
bandwidth of the transimpedance is approximately equal
to,
f 3dB 
Fig. 3. The proposed TIA with three identical cascaded stages
f1 
gm1  gmp
(6)
2 A0C2
The gain bandwidth (GBP) product of the single-stage
amplifier will be,
(4)
Where AG is the total gain of the tree stages witch is
equal to cubic open loop gain AOL. The stability of the
system is related to A, and the total gain A of the system
must be strictly controlled.
A conceptual optimization has been considered by
taking the gain of a single stage of the TIA. An analysis
has been carried out by introducing the different intrinsic
capacitances at the level of each MOS transistor Fig.4.
By taking C1 and C2, the capacitances at nodes (1) and
(2) respectively, the cut-off frequency of the single
amplifier in the open loop configuration at node (2) is
given by,
GBW1 
gm1  gmp
2C2
(7)
and considering C2 = m.C1, we get,
GBW1 
gm1  gmp
2 mC1
f
 0
m
(8)
where f0 is the cut-off frequency at node (1).
The frequency f1 determines the second pole. To
ensure good stability, this pole must be located beyond the
dominant pole according to the following condition [5],
f1   f 3dB
(9)
where  is a factor ranging between 2 and 3 [5]. Under
these conditions AOL will be expressed as follows,
AOL 
f0
m f 3dB
(10)
In our case, the transimpedance structure consists of
three identical stages in cascade. Therefore, in the node
(2) the capacitance C1 is added and we obtain,
C2'  C2  C1  m  1 C1
(11)
The gain bandwidth product of each stage will be,
GBW3i 
gm1  gm3
f0

2 m  1 C1 m  1
(12)
To obtain the same phase margin as for a single stage,
the cutoff frequency of each stage will be equal to [6]:
f3i  nf 3dB
(13)
where n represents the number of stages and f3i the
cutoff frequency of the transimpedance structure. The gain
of each stage of our structure has the following
expression,
AOL 
f0
m  1 n fdB
(14)
The TIA uses a negative feedback to obtain a stable
transimpedance gain and a large bandwidth, but this
negative feedback can cause stability problems. A
compromise was already mentioned between the
bandwidth and the gain because it is known that
increasing bandwidth adversely affects the gain and vice
versa, so in first place we decreased the gain by playing
with the parameters of the feedback transistor by
increasing its width and decreasing its bias voltage Vg
(which provides a low resistance). We thought it was
sufficient but the simulation results have shown the
presence of a peak in the gain curve witch can gives
instability. For high-frequency applications, the dominant
pole of the open loop frequency response is located at the
input node, while the no dominant poles are those of the
amplifier. The poles of the amplifier can be located at
high frequencies, preferably above the cut-off frequency
f−3dB, to ensure good stability. Therefore, amplifier stages
with low gains and large bandwidths should be used. The
localization of the amplifier poles can be designed to yield
a stable response [5].
After locating the other pole of the amplifier we
started to increase the width of the two transistors Wn1 and
Wp (which are proportional to the cutoff frequency f-3db) to
remove it from the critical point.
We used a photodiode with capacitance of 0.4 pF, also
we estimated the total capacitance at 1 pF including
parasitic capacitance and the capacitance at the input
node. So by using Eq.3, Eq.4, and Eq.15, the estimated
equivalent feedback resistor is 531 Ω, and the 3 dB
bandwidth equal to 2.75 GHz.
II. NOISE ANALYSIS
which gives,
The equivalent noise power at the input node is given
by Eq.18 [4]. Where q is the electron charge, k is
gm1  gm3
Boltzmann’s constant, T is the absolute temperature, Idark
AOL 
(15)
is the dark current of the photo detector, IG is the gate
2 m  1 n C1f 3dB
current, CT is the total input capacitance, Rin the input
impedance and B indicates the useful bandwidth. If we
Knowing  (the PMOS/NMOS mobility ratio of the use a PMOS transistor as a feedback we eliminate the
Push-Pull inverter), the use of the term giving the open- factor 4kTB/RF. Thus,
loop gain of a single stage in the dimensions of the
transistors, we can evaluate the term gm1+gm3 and the
4k T
it2ot  2q Ida rk B 
B  2q IG B 
various capacitances depending on the gain. Indeed, from
RF
(18)
Eq.2 and using that giving , we estimate the lower limits
2 3
8k T  B
of the dimensions of the transistors constituting the

 2  2 CT  B 
3gm  Rin
inverter Push-Pull. After development, we get,

2
Wn1
AOL

Wn2 1  2AOL
(16)
gives the absolute minimum noise that can occur at the
input, assuming RF extremely high. However, the noise
performance is close to the optimum when [7],
and,
Wp
Wn2

2
 AOL
1  2AOL
The last term is the more prominent then the noise
power, depends mainly on B3 and CT2 g m . This last term
(17)
To have the widest bandwidth possible, the transistor
constituting the charge must has the smallest size possible.
This requires us to choose Wn2 in the limit of 0.35 µm
process technology.
0.2  CPD  CS   CGS  CGD   2  CPD  CS 
(19)
An increase in the capacitance (CGS + βCGD) in
extreme lower cases enables us to carry out this
optimization. This is obtained with a definite number M of
transistors connected in parallel. Thus, the capacitance of
the transistors of attack will be equal to Mx(CGS+βCGD),
the total transconductance however, will be equal to Mgm.
This allows us to assess CGS, CGD, and gm translated by
their respective relationship. In assessing Mx(CGS+βCGD)
at around the minimum value (so that CT =
CPD+CS+Mx(CGS+βCGD) = 1pF). Thus the value of M is
given by the following equation [3]:
  Ctot  C1
M  

C1
   1
These performances are required in most
communication standards, which make the TIA more
feasible to achieve a higher transmission speed. Table.3.
summarizes the results of designed TIA and gives
different results in comparison to previous works.
(20)
where δ is a factor which reflects the inequality given in
Eq. 19, it varies between 0.1 and 2.0, while respecting the
following constraints,
(21)
III. SIMULATION RESULTS
The TIA shown in Fig.1 is implemented with 0.35 μm
CMOS technology, and the power dissipation is 53.5 mW
with 3.3 V supply voltage. The Layout of the chip is
shown in Fig. 5. We obtain a chip size of about 1252 µm2.
Fig.6 shows the gain versus frequency response of the
TIA. As it is shown in Fig.6, the transimpedance gain is
about 531 Ω and the bandwidth is 2.75 GHz, which makes
the amplifier suitable for speed up to 5 Gb/s in
optoelectronics application. The simulated noise at the
input of the proposed topology is depicted in Fig. 7, which
shows a maximum at low frequencies, then it falls and
tends to zero at high frequencies along the desired
frequency range.
A DC analysis giving the output voltage versus the
photocurrent is shown in Fig. 8. This characteristic shows
a good linearity of the amplifier as well as a high dynamic
range along a high input current range.
The output signal shown in Fig.9 is a pulse signal
generated by the application of a pulse photocurrent
signal. It ensures a correct transfer rate of the designed
TIA.
IV. CONCLUSION
A low noise and high bandwidth TIA has been designed
and simulated in a standard 0.35 µm technology, The
proposed TIA achieve 2.75 GHz 3 dB bandwidth, 54.5
dBΩ transimpedance gain, with 53.5 mW of power
dissipation from a 3.3 V supply voltage.
The analytical illustrations as well as different
simulation results given by PSpice tool show that the
designed amplifier displays good optimized performances
that offers considerable gain, good dynamic range and,
particularly a relatively low-noise level at the input.
Fig. 5. Layout of the whole TIA
0.5
I-V Gain (k)
The introduction of a PMOS transistor connected in
resistance reduces the noise level of this structure
transimpedance. In addition to this advantage it reduced
considerably the surface during the integration of the
active resistance, carried out in poly, take a place in the
chip. Thus, this structure keeps the same performance as
with resistance.
0.4
0.3
0.2
0.1
0.0
100
102
104
106
108
1010
Frequency (Hz)
Fig.6 . Transimpedance gain (I-V gain) versus frequency
8
IiNx1000 (pA/Hz0.5)
CT  CPD  CS  M  C1  1pF
6
4
2
0
100
102
104
106
108
Frequency (Hz)
Fig.7. Input noise current of the whole TIA
1010
Vout (V)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
ACKNOWLEDGMENT
This work was supported by MESRS (Ministère de
l’Enseignement Supérieure et de la Recherche
Scientifique) under the supervising of the CNEPRU,
www.cnepru-mesrs.dz,
REFERENCES
1.
0
1
2
3
Iinx1000 (mA)
4
Fig. 8. Output voltage versus Input photo-current
Vout (V)
1.3084
1.3083
1.3082
1.3081
0.00
0.01
0.02
Times (s)
0.03
0.04
Fig. 9. Pulse response of the whole TIA
TABLE. I.
Performances summary of the proposed TIA:
Comparison with others works. *This Work
Ref
.
[9]
[10]
[11]
Tech.
0.35
µm
0.50
µm
0.18
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CPD
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BP
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Power
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0.6
1.20
64.0
0.6
115 (3.3V)
0.2
1.80
58.7
13.0
47 (31.8V)
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