Lab 7
Nand gate model
During this lab you are going to model NAND gate in SPICE language in simulator
eldorado from MentorGraphics. NAND model should be done for 180 nm technology
such way that positive-going slope’s time and negative-going slope’s time would be
equal for the output signal. You can change width of transistors leaving their length the
same 180nm.
You would simulate your model in eldorado simulator from MentorGraphics. In order to
compile files you need:
 With >cad command choose MentorGraphics;
 Typing >eldo [circuits names]compile your model;
 >ezwave would open graphical representation of your simulation, where you
can open your compiled model and see marked signals. Clicking on the plot with
the right button of the mouse you can add cursor, which would measure value of
the signal at certain point in time.
In order to practice using these tools a model of inverter with wire connected to the
inverter’s output is given to you. Schematic picture of this model is the following:
Figure 1 Schematic picture of inverter with wire at the output.
For this model P-MOS and N-MOS transistors of 180nm technology are used, therefore
the length of transistors is 180 nm and the width is 2 times bigger 360 nm (the smallest
possible). For wire model we have wire of width 2*180nm= 360nm and the length of it
10m, therefore we get resistance equals to 2,2  and capacity equals to 2fF. The model
written in SPICE is given to you in invWire.cir file. This model uses as sub-circuit wire
model, which is given in separate file wire.cir. Firstly, compile wire.cir, then invWire.cir.
To use the sub-circuit in your modules use the following SPICE syntax:
X[name] [connections] [name of sub-circuit]
Also you need to include sub-circuit file itself with:
.INCLUDE [file name]
Task:

compile and simulate model of inverter with wire at the output (files: invWire.cir,
wire.cir). Make sure the output is correct.
 Write the model of NAND gate with inverter on the output in SPICE language
according to the schematic picture (Figure 2). The skeleton of this model is given
in file nandInv.cir. We simulate the model with pulses of 100MGz and reference
voltage 1.5V. Sub-circuits of wire and inverter are given in separate files:
wire.cir, inv.cir. To describe MOS transistor in SPICE you need to declare it in
the following format:
M[name]
[drain node] [gate node] [source node]
[bulk/substrate
node]
[model
name]
[model
parameters
(length L, width W)]
 Find appropriate width of P-MOS and N-MOS transistors in order to get rising
and falling edges times of output signal equal. The length of transistors should
remain the same 180 nm, keep in mind that you can’t make the width smaller than
360 nm. Slope time is defined as time when signal value is logically undefined physical value being between 10% and 90% of reference voltage.
Figure 2 Schematic picture of NAND gate with inverter in the ouput.
Clue:
In order to find the ratio of width between N-MOS and P-MOS transistors they could be
approximated as resistors. Then we have the following:
R ~ -1, where  is mobility for N-MOS n=1250 cm2/V*sec, for P-MOS p=480
cm2/V*sec
R ~ L/W
Requirements:



Code with comments added to the report;
Output picture added to the report;
Description of the solution: parameters, slopes times;
Possible solution for the output: