Telecommunications Industry Association
(TIA)
Norcross, GA, 9-11 April 1997
TR30.1 Ad-hoc __N14____
COMMITTEE CONTRIBUTION
Technical Committee TR30 Meetings
SOURCE:
U.S. Robotics
CONTRIBUTOR:
Dale Walsh
TITLE:
Proposed Data Encoder Text
PROJECT:
PN:3838
DISTRIBUTION:
Meeting attendees
_________________________________
Attached is proposed text for the PCM Modem Data Encoder. Included are:
1. A frame based system with frame size 6 and speed increments of 1.33K
2. The Modulus encoder technique described earlier
3. The dc compensation scheme based on assigning sign bits to the codes. The
description here is a modification for the scheme described earlier
Copyright Statement
Contributor's company grants an irrevocable royalty-free and compensation-free license to the Telecommunications Industry
Association (TIA) to use the text of this contribution in any TIA
publication.
Intellectual Property Statement
The individual preparing this contribution knows of patents, the use of which, may be essential to a standard resulting in whole or
part from this contribution.
X. Data Encoder
X.1 Overview
The Data Encoder (see figure X.1) is a frame based modulus encode and mapping process that
converts D scrambled data input bits to six G.711 PCM codes (octets). Included is a DC null process that
assigns certain PCM code sign bits to shape the transmit spectrum.
Data Encoder inputs are D input data bits per frame. The outputs are six serially transmitted PCM code
octets that make up the transmitter mapping frame (see figure X.2), where PCM0 is first in time. Each of
the six frame positions is called a frame signaling interval. Table X.1 shows the relationship between
data signaling rate D, and S.
TABLE X.1
Mapping parameters D, N and S for different data rates
N, bits entering
modulus encoder
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
S, sign bits used
for user data
From:
To:
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
D, bits per
mapping frame
From:
To:
19
25
20
26
21
27
22
28
23
29
24
30
25
31
26
32
27
33
28
34
29
35
30
36
31
37
32
38
33
39
34
40
35
41
36
42
37
43
38
44
39
45
40
46
41
47
Data Signaling
Rate, kbps
From:
To:
25 1/3
33 1/3
26 2/3
34 2/3
28
36
29 1/3
37 1/3
30 2/3
38 2/3
32
40
33 1/3
41 1/3
34 2/3
42 2/3
36
44
37 1/3
45 1/3
38 2/3
46 2/3
40
48
41 1/3
49 1/3
42 2/3
50 2/3
44
52
45 1/3
53 1/3
46 2/3
54 2/3
48
56
49 1/3
57 1/3
50 2/3
58 2/3
52
60
53 1/3
61 1/3
54 2/3
62 2/3
Data Encoder parameters, established during training or rate switching procedures, are:
 six PCM code sets, one for each Mapper 0 through 5, where Mapper i has Mi members.
 Sdc , the number of PCM code sign bits per frame used to shape the transmitter spectrum.
N input data bits define the unsigned portion of the six PCM output codes.
S input data bits plus Sdc null compensation bits, where S+Sdc=6, define the six PCM code sign bits
according to a sign assignment procedure.
Figure X.1
Transmitter Frame Encoder
M1 M3 M5
M0 M2 M4
N1 N3 N5
N0 N2 N4
N5
M5-point
Map
U5
PCM5
N4
M4-point
Map
U4
PCM4
N3
M3-point
Map
U3
PCM3
Modulus
Converter
dD-1
Scrambled
Data
Bits
d0
Bit
Parser
Sign
Assignment
N2
M2-point
Map
U2
PCM2
bN-1
N1
M1-point
Map
U1
PCM1
b1
b0
N0
M0-point
Map
U0
PCM0
sS-1
dsS-1
PCMtoLinear
SDC
s0
Differential
Encoder
ds0
Serial
PCM
Octets
Mux
Running
Sum
Integrator
As part of this assignment rule, the Data Encoder computes a running sum of the linear signals
corresponding to the transmitted PCM codes, thereby anticipating the average voltage output of the
remote G.711 codec.
PCM0
PCM1
PCM2
PCM3
PCM4
PCM5
Figure X.2
Mapping Frame Structure
X.2 Input Bit Parsing
D serial input data bits, where d0 is first in time are passed into N modulus encoder input bits and S sign
bits. See Figure X.3
dD-1
…..
ds
ds-1
……
d0



bN-1
b0
sS-1

s0
Figure X.3
Input Parsing
X.3
Modulus Encoder
N bits enter the modulus encoder. The values of N for each data rate are tabulated in Table X.1. There
are six independent mapping moduli M0 through M5, which are the number of members in the PCM code
sets defined for Mapper0 through Mapper5 .
The modulus encoder converts N bits into six numbers (or indices) N0 through N5 by the following
algorithm:
Represent incoming N bits as an integer:
R0 = b0 + b1*21 + b2*22 + ... + bN-1*2N-1
Equation X.1
where b0 is LSB and bN-1 is MSB. Next, divide R0 by M0. The remainder of this division gives N0, the
quotient becomes R1 for the next signaling interval. Continue for all six intervals:
N0 = R0 modulo M0,
N1 = R1 modulo M1,
N2 = R2 modulo M2,
N3 = R3 modulo M3,
N4 = R4 modulo M4,
N5 = R5
where 0  N0 < M0
where 0  N1 < M1
where 0  N2 < M2
where 0  N3 < M3
where 0  N4 < M4
;
;
;
;
;
R1 = R0/ M0
R2 = R1/ M1
R3 = R2/ M2
R4 = R3/ M3
R5 = R4/ M4
Equation X.2
The numbers N0,…,N5 are the output of the modulus encoder, where N0 corresponds to first in time
signaling interval and N5 corresponds to last in time interval. See examples in appendix A.
X.4 Mapper
There are six independent mappers associated with the six PCM mapping intervals in figure X.2.
Mapperi is a tabulation of Mi PCM codes that make up the frame interval i constellation points.
The PCM code in G.7.11 that corresponds to the largest analog signal magnitude is herein called the
largest PCM code. The PCM code set members are numbered in descending order so that index Ni=0
corresponds to the largest PCM code in the mapper set, and Ni=Mi-1 corresponds to the smallest PCM
code in the mapper set.
X.5 Differential Sign Bit Encoding
Each of the S sign bit inputs shall be differentially encoded per table X.2,
Table X.2
Sign Bit Differential Encoding
sj
dsj-1
dsj
0
0
0
0
1
1
1
0
1
1
1
0
X.6 Sign Assignment
Six sign bits ds0-ds5 are attached to the six unsigned mapper outputs U0-U5 to complete the PCM0-PCM5
mapping frame indicated in figure X.2.
SDC sign bits (see section y.yy) are determined by monitoring the output of a Running Sum Integrator (RSI)
which is the sum of linear values corresponding to all previously transmitted PCM codes.
A PCM-to-linear convertor output (figure X.1) is a signal proportional to the output of a G.711
digital-to-analog convertor.
The sign assignment procedure is:
a. Determine the SDC frame intervals that will be used for DC compensation. The frame intervals
having the lowest Mapper (indices) shall be selected. In case of equal valued minimum
indices, higher frame number intervals (later in time) are selected before lower number frame
intervals.
b. Assign the S differentially encoded sign bits ds0-dss-1 to the S frame intervals not selected for
DC compensation. Sign bits shall be assigned in ascending order (ds0, ds1, etc.) to available
frame intervals in ascending order. That is, first-in-time differential sign bits shall be assigned
to first-in-time available frame intervals.
c. The PCM codes are sent sequentially beginning with PCM0. For each PCM code, PCMi:
 if frame interval i is not one of the DC compensation frame intervals selected in step a,
then PCMi is sent and RSI is updated
 if frame interval i is a DC compensation interval, then PCMi is assigned a sign opposite
the sign of the RSI output, PCMi is sent, and RSI is updated.
A. Appendix X - Modulus Encoder Examples
A.1 Example 1
M0 through M5 = 16; N = 24; bit stream = R0 = FFFFFF hex = 16777215
N0 = R0 modulo M0 = 15
N1 = R1 modulo M1 = 15
N2 = R2 modulo M2 = 15
N3 = R3 modulo M3 = 15
N4 = R4 modulo M4 = 15
N5 = R5
R1 = INT (R0 / M0) = 1048575
R2 = INT (R1 / M1) =
65535
R3 = INT (R2 / M2) =
4095
R4 = INT (R3 / M3) =
255
R5 = INT (R4 / M4) =
15
= 15
A.2 Example 2
M0 through M5 = 23,17,24,16,27,26; N = 26; R0 = 154FDF4 hex = 22347252
N0 = R0 modulo M0 = 15 R1 = INT (R0 / M0) = 971619
N1 = R1 modulo M1 = 1
R2 = INT (R1 / M1) =
57154
N2 = R2 modulo M2 = 10 R3 = INT (R2 / M2) =
2381
N3 = R3 modulo M3 = 13 R4 = INT (R3 / M3) =
148
N4 = R4 modulo M4 = 13 R5 = INT (R4 / M4) =
5
N5 = R5
= 5