Digital System Design Using a CPU
Background
I
In Digital Devices, a logic network was designed to implement a SSN sequencer. The
logic design included flip-flops and combinational logic to solve a specific problem. A
different SSN required a different logic design. Another approach is possible allowing a
single network to solve many different problems. This design includes using a
microprocessor-based system. The advantage to using a microprocessor based system is
the capability for the system to work for many different circuits without a hardware
change to the system. Simply by reprogramming, an entirely new problem can be solved.
This general purpose logic network might not be as efficient (speed, cost) as a special
purpose logic network, but often allows products to be produced faster than a special
purpose logic network!
Learning Objectives
1. Become familiar with the computer system model.
2. Be able to create the machine code for the SSN CPU from an assembly language
program.
3. Become familiar with the operation of the SSN CPU and write programs to control its
operation.
4. Discuss the implementation of an extension to the SSN CPU instruction set.
Pre-Lab
1. Review the online lecture notes for the SSN CPU machine.
2. Have Altera Maxplus 10.1+ Baseline edition installed on your PC and review how to
compile/simulate designs within Maxplus. Perform the Maxplus tutorial found in the
Digital Devices textbook if you need to review Maxplus operation.
3. Download the file archive containing SSN CPU. Compile the design in Altera
Maxplus, and verify that you can simulate it.
4. Become familiar with the LPM modules used within the SSN CPU design
(lpm_counter, lpm_rom, lpm_dff). Read the material in Appendix A on LPM usage
within MAXPLUS.
Task Overview
1. Write a program for the SSN CPU that outputs the digits of your SSN. Modify the
rom.mif file for your SSN. Demo this program to the TA.
2. Create a new schematic called my_scpu.gdf and make the necessary modifications to
it so that it can support a program that contains up to 32 lines of code. Demonstrate
that your changes work by placing your original program starting at location 16 in
memory. At location 0, place a ‘goto 16’ instruction so that your program will
execute after reset.
Parts List
This lab does not have a hardware component.
Detailed Tasks
These notes assume that you have reviewed the online notes on the SSN CPU.
Lab Report
1. Include the assembly code and machine code of the programs for tasks #1 & #2.
2. Include a screenshot of your schematic for task #2.
3. Briefly discuss the changes that had to be made for the SSN CPU design for task #2
and WHY they needed to be done.
4. Assume we wanted to add a new instruction called ‘NOT’ that would perform a one’s
complement (invert the bits) on the current value in the OUTPUT register. What
changes would have to be made to the decode logic and overall design to implement
this? Show a sketch or rough schematic of the details of the needed changes (there is
more than correct solution).
Appendix A: Introduction to LPM Modules
Altera provides a set of common logic modules that serve as building blocks for digital
systems. These modules use parameters that can be changed by the user to achieve
scalability of the function. An example of this is the LPM_Counter. By changing one
parameter, the symbol for a four-bit counter can easily be converted to an eight-bit
counter. These modules can be found in the mega_lpm library in MaxPlus. Several of
these components are utilized in the lab for the SSN sequencer.
The LPM_Rom is used for the memory that holds the code the system. As discussed in
class the memory is described as a K x N device. The size of K is set by specifying the
LPM_WidthAD (ADdress bus width). Remember that the number of locations is 2k. The
input parameter LPM_Width is used to specify the width of each location (N).
Before compiling the project, the memory must be initialized. In Maxplus, this is
handled by using a memory initialization file (rom.mif is included in the SCPU archives).
This is an ASCII text file that specifies the initial content of a memory block. The file
can be changed with any text editor (MaxPlus has a text editor included). Note that in the
file, the first two lines are the depth (K) and width(N) of the memory block. Next listed
is the radix for the address and data lines. Hex is the default radix.
The LPM_Counter is used as the program counter. Asserting the Enable input will
provide the sequential execution of the code. The counter will increment the output value
each clock cycle which increments the memory location where the code is stored. The
program steps sequentially unless a jump to another location is needed. To jump to
another location, the LPM_Counter is loaded by placing the new location value on the
data_in lines and the load input line is asserted.
The output data is provided by the LPM_DFF. The WIDTH parameter corresponds to the
the number of bits needed to output the values 0-9 (four bits). The DFFs are enabled
when the opcode matches what is needed for the OUT instruction.