Lab 9b/Tutorial 1 (Adapted by DBA for PSU setup)
Introduction to VHDL and ISE on the Digilent NEXYS 3 board and
schematic capture examples
Introduction
These labs will be using what is known as a Field Programmable Gate Array (FPGA). In
your own words, describe what a FPGA is. The FPGA will be on a Digilent Spartan3E
board. FPGAs are different than traditional integrated circuits, because interconnects
between the gates are programmable, which means the hardware itself is configurable.
This lab exercise (for CH425/525) used the first in a series of tutorials produced by Craig
Kief of Cosmiac (Figure 1) and added a schematic capture piece.
Cosmiac assumed that the individual wishing to learn programmable logic would
complete tutorials 1-3 in order. Once that series is complete then the individual could
proceed to any of the remaining tutorials (4-15) in any order desired based on their
individual needs. If you find this stuff fun, you can go in that direction too.
This lab will be an introduction to design techniques for FPGAs using a hardware
descriptive language (VHDL) design. Xilinx ISE 14.2 is the design tool provided by
Xilinx for this purpose. Xilinx makes a free version of this tool called Webpack which
would be virtually identical for this purpose. The board will be a Digilent NEXYS 3
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board with a XC6LX16 chip. Please avoid putting your fingers on the chips, as they are
very electrostatic discharge sensitive.
There are four fundamental steps in all digital logic design. These consist of:
1. Design – The schematic or code that describes the circuit.
2. Synthesis – The intermediate conversion of human readable circuit description
to FPGA code (EDIF) format. It involves syntax checking and
combining of all the separate design files into a single file.
3. Place & Route – Where the layout of the circuit is finalized. This is the
translation of the EDIF into logic gates on the FPGA.
4. Program – The FPGA is updated to reflect the design through the use of
programming (.bit) files.
There are two sections of “design” for the first part of this lab. The first is the VHDL
program design of what the project has to do, where the circuit in question will be
implemented. The second step is the testbench simulation. As its name implies, it is used
for testing the project by simulating the result of driving the inputs and observing the
outputs to verify your design. The software package to be used is the Xilinx ISE 14.2.
ISE has the capability of implementing a variety of different design methodologies
including: Schematic Capture, Finite State Machines, and Hardware Descriptive
Language (VHDL or Verilog). ISE also provides its own simulation tool to test your
designs before setting them on the FPGA. For additional details on the various tools and
their uses, view the video on the FMAC website (www.fpgamac.com).
Objective
The objective is to understand the basics of digital logic and design. This will be
accomplished through the implementation of the small circuit below in an FPGA. The
circuit is designed so that only specific combinations of switches A - D will turn on a
light emitting diode (LED) on the board.
The Boolean expression for this circuit is Y=(NOT(A) AND B) OR (C AND D). The
schematic can be seen in figure 3. The full truth table is big (16 rows) but you can see
how it works by doing the AB and CD combinations (4 rows each) and looking at how
these get ORed together. Do the full truth table or the short version to figure out what it is
going to do before you start.
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Process
1. Analyze the VHDL.
2. Verify inputs and outputs with test bench waveform.
3. Program FPGA with circuit design.
Implementation
1. Open the Xilinx ISE Design Suite by selecting it from the start menu or by doubleclicking the desktop icon.
2. Within the project navigator, select from the File Menu, New Project. Name the
project “tutorial1” (Figure 4). To put the project in a different location, either
directly type the file path into Project Location or search by clicking the Three-dotted
Browse button. The location of the project can always be seen on the top of the
Project Navigator screen. Click next and it will show the device properties window.
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3. Set the applicable device properties (Family is Spartan 6, device is XC6LX16,
package is CS324) and make sure you change the Preferred Language to VHDL and
then continue to select Next until the project is created.
4. A new blank project will open. For this project, there are three source files.
Download them and copy them into the directory for Tutorial 1. The files are:
Tut1Source.vhd (the source file), tut1_tb.vhd (the testbench) and tut1.ucf (the user
constraint file). When naming testbenches, it is common practice to add the “_tb”
to the file name. Right click on the device in the top left pane and select Add
Source as shown in figure 6.
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5. Select the three source files (Figure 7) and click Open.
6. The green check marks (Figure 8) identify that the program knows what type of
files they are and what to do with them. The Tut1Source.vhd file can be used for
Synthesis, Implementation, and Simulation. The tut1.ucf constraint file can’t be
used for simulation. The tut1_tb testbench can only be used for simulation. Click
OK to pull the files into the project.
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7. Figure 9 shows that there are two major sections on
the left side of the Project Navigator where most of
the work gets done. The windows are the Sources
tab (top) and the Processes tab (bottom). In the
Sources tab, a tree structure is displayed. If you click
on the “+” symbol you will see that the .ucf file falls
below the source file.
8. By double-clicking on the Tut1Source.vhd file you
can see the source file in the text editor screen to the
right. The source code is commented and some parts
are easy to follow (Figure 10). Copy and paste the
part of the code that executes the logic diagrammed
in Figure 3 here. In the sources tab, Click on the
radio button to select Simulation and select
Behavioral in the drop down menu immediately
below.
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9. In the Sources window, the tree structure is again seen. This time, if you click on
the “+” symbol, the source file is shown as a child to the testbench file. Highlight
the testbench file and double-click on the “Simulate Behavioral Model” in the
processes window.
10. The Xilinx ISim will launch (Figure 12) after a minute or so. You can zoom to
show the whole time window by right clicking on the waveform and selecting “To
Full View” (Figure 13).You can then zoom in by right clicking and selecting “In”
or by using the icon on the toolbar above.
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11. By clicking into the waveform, the yellow marker line will appear. By clicking
or scrolling back and forth, you can see what combinations of inputs cause a high
on the output. You can either “eyeball” the logic states, or use the values on the
left side of the display. Verify that this “jives” with your predictions from above
(the truth table).
12. In the sources pane, choose Implementation (Figure 14). The source file is used to
describe the behavior of the hardware. The third file that is used in this project is
the tut1.ucf file. The “ucf” stands for user constraint file. What this file does is
tie the source file inputs and outputs to the actual pins on the device, which are in
turn connected to switches and LEDs, etc. on the NEXYS 3 board. There are
many more things that a UCF file can be used for but they are beyond the scope
of this tutorial.
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13. Highlight the ucf file in the sources section as shown in figure 15. In the processes
tab, expand the user constraints section. Double-click on the Edit Constraints
(Text) button. This will bring up the five line ucf file (Figure 16).
14. The first line in Figure 16 ties the input
A to pin G18 on the FPGA. On the old
boards, Pin G18 was tied to switch 0 on
the FPGA board (Figure 22). The word
“NET” identifies a signal input or
output. The “LOC” identifies a pin
number on the FPGA and the green text
is comments. The entire listing of all
the permissible connections is listed on
the Digilent web site. In this case, we
can get the proper LOC assignments
from the FPGA board, since they are screen printed on the board. For example,
SW0 is now T10, rather than G18 (find this on your board). Change the other
three switches and the output LED (which is now U16) inside of the quotation
marks in the UCF file, then save the file using a control - S.
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15. As mentioned earlier, there are four distinct steps to any FPGA project: design,
synthesis, implementation, and programming. The design portion is now finished.
Next do the synthesis by double clicking on Synthesize in the processes tab - if
the operation is successful you get a green check mark (Figure 17). When
synthesis is done, double click on Implement Design. Once both process have
completed double click on generate programming file. This will create the “.bit”
file that will be used to program the FPGA.
16. Turn on the Nexys 3 board using the Power slider switch in the corner and start
the program “Digilent Adept” (probably on the desktop or under the Start button).
Adept is the software provided by Digilent that the Xilinx tools will use to
communicate through the JTAG chain to the programming pins on the FPGA.
The box that opens is shown in figure 18. This application will program the
FPGA.
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17. Clicking “Initialize Chain” finds the items on the JTAG chain. Typical items are
the FPGA and possibly a PROM. Choose the “.bit” file and then Open (Figure
19). If there is a PROM skip this selection.
18. Click the “Program” button to program the FPGA (Figure 20). At this point the
programming file is loaded into the device.
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19.
When the device has successfully programmed you should be able to use the
switches to verify that the hardware works properly. This is done by sliding the
switches to the center for on and towards the board’s edge for off (Figures 21 and
22). Confirm that the whole process worked by giving a set of inputs that turned
the LED on below.
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Part 2 – Schematic Capture
In this part of this tutorial, we’ll use the Schematic Capture functionality of the ISE
software to make the FPGA board mimic a couple of the circuits we’ve already built. In
principle, you can make arbitrarily complex digital circuits using this approach, but
practically speaking, it usually becomes easier to do really big jobs using the VHDL
programming language. If you want to try out the VHDL versions, let me know, and we
can either use a tutorial that was developed for a Physics lab at PSU or one of the
Cosmiac ones.
We’ll build the RS Latch and the Full Adder circuits. Locate these two circuits in Labs 8
and 9 and copy and paste them in below. Refresh yourself on the truth tables for these
two circuits so you know what to expect.
1. “Circuit” exercise 1 – Open ISE Design Suite (if it isn’t still open) and select File 
New Project. Call the project “SchemCap” or something like that. At the bottom of the
Create New Project dialog in the Top level source type drop-down box select Schematic
and then click Next. Again make sure the Family and Device are correct (they should be
as you set before) then click Next and then Finish. Select Project  new Source from the
ISE menu and then choose Schematic and fill in a name (SchemCap is ok). Click Next
and then Finish.
2. In the right window of the ISE Project Navigator you will see the schematic drawing
window. The icon on the left that looks like an AND gate on top of a resistor allows you
to select components and place them on the diagram and the one near the top that looks
like a pencil drawing a red line is the wiring tool. Click the component icon and choose
the logic category and the nand2 symbol (two-input NAND gate) and move your mouse
onto the whiteboard. Click once to drop a gate. You need two gates, as shown in your
diagram above for the RS Latch. Wire the logic gate part of the circuit. It’s usually easier
if you zoom in until you see the dots and then when you get the wiring tool over the
inputs and outputs of the gates, it will indicate the connection by putting a few dots
around it. You click at the one end, move to the other end and click again, and it
automatically makes the wire route “pretty”. If there is a red spot on the wire, you haven’t
made a proper connection. To make the inputs, select the Add I/O marker icon right
above the Add Component one and click on the diagram where the R and S connections
are. Then make the Q and Q’ outputs by adding a short piece of wire to the “wraparound” wire (you terminate a wire by right clicking instead of left) and then adding the
outputs to the ends of the wires using the Add I/O marker tool. Note that each of the
inputs and outputs has a name (like XLXN_1) – later you will associate these names with
markers (and thus switches or LEDs) on the Nexys 3 board.
3. Assuming that your schematic now looks like the RS latch, you are ready to proceed
with the creation of the .ucf file, the code generation (schematic capture), the place and
route, and the final programming. Save the project first, then use the black arrow at the
bottom of the left window to scroll back through the tabs and select the Design tab. Click
your source code in the top pane to highlight it and note that the bottom pane changes to
include a tree structure. Click on the + next to User Constraints and double click on the
first line: I/O Pin Planning (Plan Ahead)…. If it asks whether you want to save, say yes.
Then it will ask if you want to add a ucf file, and again say yes. This should launch the
PlanAhead program, but it may be a little slow to start up. In the bottom pane of the
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PlanAhead program click on the + next to Scalar Ports (4) and it will expand to show the
four I/Os you defined in your schematic (quite possibly XLXN_1 to 4). Click in the Site
box on one of the rows (note that these boxes are white on a white background and aren’t
visible until you click on them – duh!) and choose the appropriate location for the input
or output: for example, use T10 to connect the right-most slider switch to the R input.
Make all four connections, consulting your Nexys 3 board and your schematic if
necessary. Click save and close PlanAhead. In the upper pane of the left window in ISE,
click the + next to your source file name and double click on the .ucf file that you just
created. Note that it is just a text file like before that shows the linkages between the I/O
elements in the schematic and the locations on the board. PlanAhead does a lot of other
stuff, but can be used as a fancy way of creating the .ucf text file.
4. Next, save the project, highlight your source file in the upper pane and double click on
the Synthesize XST line in the lower pane. Hopefully, when the process indicators stop
spinning, you will have a green check mark next to this line. Next double-click the
Implement Design line, and finally the Generate Programming File line. Assuming that
all three steps ran successfully, you are ready to program the device. Start the Adept
program, if you didn’t leave it open before. If it doesn’t recognize the board, cycle the
on/off slider switch next to the USB and click the Connect drop-down box to select the
Nexys3. Click the Initialize Chain button, then use the Browse button and locate your
*.bit file. Click the Program button. When it finishes, your board should respond and you
should be able to check that your circuit is acting as an RS latch.
Fill out the truth table again, to verify that it is behaving correctly.
5. The next exercise is to replicate the whole procedure, but build the full adder. See if
you can do it without prompts (the ultimate test of user-friendliness) but if not, you can
just cycle back to the start and follow the directions, making changes where necessary.
Either is good practice.
Do the truth table for the adder below.
6. If you have time and desire, you can either try the multiple bit adder or make the two
digit decimal counter that we described in Lab 9. Both are reasonably easy, just requiring
a little cut n’pasting. If so, describe what you did and how it worked out.
Revised 6/12/2013 DBA (did not bother to try to update pictures, since software will
probably change before next time – use snipping tool to take screen grabs)
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About the original author: Craig Kief is the Deputy Director of the Configurable Space
Microsystems Innovations & Applications Center (COSMIAC) and can be reached at
Craig.kief@cosmiac.org.
VHDL Source File
--VHDL files contain three parts: library declarations, entity and
--behavior. The library describes what each function will do. Entity
--describes the inputs and outputs. Behavior is the working
--portion of the project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Declaration of the module's inputs and outputs for part 1 of tutorial 2
entity tut1 is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
Y: out std_logic
);
end tut1;
--Defining the modules behavior
Architecture behavioral of tut1 is
begin
process (A,B,C,D) begin
Y <= (NOT(A) AND B) OR (C AND D);
end process;
end behavioral;
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VHDL Testbench
--This is a VHDL testbench. It is used to stimulate the inputs to
--file we are testing. A good design practice is to create a testbench
--for each component you are developing. Test each component separately
--before combining them.
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE testbench_arch OF testbench IS
COMPONENT tut1
PORT (
A
B
C
D
Y
);
END COMPONENT;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic
--develop signals to stimulate
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL C : std_logic := '0';
SIGNAL D : std_logic := '0';
SIGNAL Y : std_logic := '0';
--UUT means unit under test
BEGIN
UUT : tut1
--map signals on right to entitys on the left
PORT MAP (
A => A,
B => B,
C => C,
D => D,
Y => Y
);
signal_A: process
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begin
A <= NOT A;
wait for 1 ns;
end process;
signal_B: process
begin
B <= NOT B;
wait for 2 ns;
end process;
signal_C: process
begin
C <= NOT C;
wait for 4 ns;
end process;
signal_D: process
begin
D <= NOT D;
wait for 8 ns;
end process;
END testbench_arch;
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