WYV54
A High Speed Binary Floating Point Multiplier Using Dadda
Algorithm
Jeevan, B. ; Narender, S. ; Reddy, C.V.K. ; Sivani, K.
Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013
International Multi-Conference on
DOI: 10.1109/iMac4s.2013.6526454
Publication Year: 2013 Page(s): 455 - 460
Project Title
: A High Speed Binary Floating Point Multiplier Using Dadda Algorithm
Domain
: VLSI
Reference
: IEEE
Publish Year
: 22-23 March 2013 Page(s): 455 - 460
D.O.I
: 10.1109/iMac4s.2013.6526454
Software Tool
: XILINX
Language
Developed By
: Verilog HDL
: Wine Yard Technologies, Hyderabad
www.wineyard.in
1|Page
WYV54
A High Speed Binary Floating Point Multiplier Using Dadda
Algorithm
Abstract:
This paper presents a high speed binary floating point multiplier based on Dadda Algorithm.
To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry
Save Multiplier. Floating point numbers are one possible way of representing real numbers
in binary format, the IEEE 754 standard presents two different floating point formats, Binary
interchange format and Decimal interchange format. Multiplying floating point numbers is a
critical requirement for DSP applications involving large dynamic range .The design
achieves high speed with maximum frequency of 526 MHz compared to existing floating
point multipliers. The floating point multiplier is developed to handle the underflow and
overflow cases. To give more precision, rounding is not implemented for mantissa
multiplication. The multiplier is implemented using Verilog HDL and it is targeted for Xilinx
Virtex-5 FPGA. The multiplier is compared with Xilinx floating point multiplier core.
Existing method:
1. Serial Multiplier
2. Booth Multiplier
3. Combinational Multiplier
4. Wallace Tree Multiplier
Proposed method:
An implementation of a floating point multiplier using Dadda Multiplier that supports the
IEEE 754- 2008 binary interchange format; the multiplier is more precise because it doesn’t
implement rounding and just presents the significand multiplication result.
Floating point numbers are one possible way of representing real numbers in binary format
the IEEE 754 standard presents two different floating point formats, Binary interchange
format and Decimal interchange format. Multiplying floating point numbers is a critical
www.wineyard.in
2|Page
WYV54
requirement for DSP applications involving large dynamic range. This paper focuses only on
single precision normalized binary interchange format. The IEEE 754 single precision binary
format representation consists of a one bit sign (S), an eight bit exponent (E), and a twenty
three bit fraction (M or Mantissa). An extra bit is added to the fraction to form what is called
the significand1.
Applications:
1. Digital systems designing
2. Digital signal processing
3. Communication
4. Computer graphics
5. Cryptography applications
Advantages:
1. Area Efficient circuits.
2. Low power Circuits.
3. High speed square computation circuit.
Conclusion:
This paper describes an implementation of a floating point multiplier using Dadda Multiplier
that supports the IEEE 754- 2008 binary interchange format; the multiplier is more precise
because it doesn’t implement rounding and just presents the significand multiplication
result as is (48 bits). The significand multiplication time is reduced by using Dadda
Algorithm. The design has been implemented on a Xilinx Virtex5 FPGA and achieved the
speed of 526MHz.
www.wineyard.in
3|Page
WYV54
Circuit or block Diagrams:
www.wineyard.in
4|Page
WYV54
Screen shots:
www.wineyard.in
5|Page