CHAPTER I
BOOLEAN ALGEBRA
CONTENTS
What are logical statement and arguments
How can the statements and arguments be represented with switches
What are Logic Gates
Boolean Algebra and some basic postulates
Boolean Expressions and truth tables
Simplification of Boolean Expressions
Canonical forms of Boolean expressions
Karnaugh maps and implementation of Boolean Expressions by Logic Diagrams
1.1 LOGICAL STATEMENTS AND ARGUMENTS
Logic is reasoning. A logical statement is one which may be either true or false. There is
no scope for ambiguity in a logical statement. The statement ‘I am wearing a sweater’
will either be true or false. There cannot be any ambiguity in the truth or falsehood of the
statement. On the other hand the statement ‘When I feel cold I may wear a sweater ’ is a
statement which has no true or false answer and is quite ambiguous. This statement could
well be broken down into several components as a) I shall feel cold if the temperature
falls below 15 degrees Celsius or if I have fever b) I shall wear a sweater. The statement
in a) has three independent statements i) ‘I shall feel cold’ will be true if ii) The
temperature falls below 15 degrees Celsius or iii) ‘I have fever’ We may tabulate the
statements made above as shown in TABLE 1.1 (a). From this table, we observe all
possible answers that the two component statements and the resulting statement can
have. We allot symbols to the statements or represent them with switches as follows. If
the statements are true we will say the switch is ON and if it is false we may say the
switch is off.
‘A’ The temperature is below 15 degrees Celsius
‘B’ I have fever
‘X’ I shall wear a sweater
In TABLE 1.1 (b) the same argument depicted in
representing TRUE with ON and FALSE with OFF.
TABLE 1.1 (a) is shown by
In the table 1.1 (b) we may consider ‘A’, ‘B’, and ‘X’ as variables which can have one of
two values ‘1’ for ON and ‘0’ for OFF. We may further represent table 9.1 (b) as table
9.1 (c) replacing ‘ON’ with ‘1’ and ‘ OFF’ with ‘0’.
TABLE 1.1 (a) ANSWERS TO STATEMENTS
TEMPERATURE
SWEATER
BELOW 150 C
I HAVE FEVER
I SHALL WEAR A
(A)
FALSE
(B)
FALSE
(X)
FALSE
FALSE
TRUE
TRUE
TRUE
FALSE
TRUE
TRUE
TRUE
TRUE
Table 1.1 (c) is called the truth table for the argument put forward for conditions under
which I shall wear a sweater. The truth table shows the output condition for all possible
combinations of input conditions. From the truth table shown in table 1.1 (c) we may
conclude that output ‘X’ will be true if input ‘A’ is true OR if input ‘B’ is true. This is
the truth table for ‘OR’ operation.
George Boole symbolised logic i.e., provided symbols to represent logical statements and
defined the operators between logical statements to build logical arguments. In the above
argument ‘A’, ‘B’ and ‘X’ are Boolean variable and ‘OR’ is the operation between ‘A’
and ‘B’. X is the resulting statement. We can represent the truth table shown in table 1.1
(c) shown above in the form of a Boolean Expression as (A+B =X) the ‘+’ sign between
‘A’ and ‘B’ represents a logical OR operation in Boolean Algebra and not addition.
TABLE 1.1 (b) ANSWERS AS ON/OFF
SWITCH ‘A’
SWITCH ‘B’
SWITCH ‘X’
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
TABLE 1.1 (c) TRUTH TABLE FOR ‘OR’ OPERATION
A
B
X
0
0
1
1
0
1
0
1
0
1
1
1
Let us consider the statement ‘I shall buy a car if I have money and a garage’ . This
statement (say ‘X’) will be true if i) I have money ( say ‘A’) and ii) I have a garage (say
‘B’) are both true. Proceeding as before the truth table for this statement is as shown in
Table 1.2 .
In table 1.2 we have a truth table for statements ‘A’ and ‘B’ with an ‘AND’ operator
between them. In ‘AND’ operation all the inputs must be true for the resulting statement
to be true. Algebraically this is written as (A . B =X) the dot between ‘A’ and ‘B’
represents an ‘AND’ operation in Boolean algebra.
Let us consider the statement ‘ Ashok will be selected only if Arun is not selected’. This
statement is composed of two statements ‘ Ashok is selected’ (say X) and ‘Arun is
selected’ (say ‘A’). To present our argument i.e., ‘Ashok will be selected if Arun is not
selected, we write the truth table shown in Table 1.3 .
TABLE 1.2 TRUTH TABLE FOR ‘AND’ OPERATION
A
B
X
0
0
1
1
0
1
0
1
0
0
0
1
TABLE 1.3 THE ‘NOT’ OPERATION
A
X
0
1
1
0
Logic gates are diagrammatic representations of logic operators ‘OR’ , ‘AND’, ‘NOT’.
The table 1.3 can be explained as ‘ X will be true if A is false and X will be false if A is
true’ alternatively we may say that X is a complement of A ,algebraically ( X=A’) the “ ’
” on A indicates complement of A.
1.2 LOGIC GATES AND OPERATIONS :- AND, OR & NOT
Logic gates are diagrammatic representations of the Logic Operators like ‘OR’, ‘AND’
and ‘NOT’. The logic gates have one or more inputs and only one output. There are three
basic logic gates which perform the three basic logic functions ‘OR’ , ‘AND’ and
‘NOT’. The FIG. 1.1 shows the logic diagram for each of these and also their algebraic
symbols. In section 1.1 the truth table for each of these operations has already been
shown.
We may show electrical connections of switches to depict the OR and AND operations
as in FIG. 1.2(a) and FIG. 1.2 (b) . It may be observed that in OR operation the bulb will
light if ‘A’ OR ‘B’ switch is closed or both are closed. In AND operation the bulb will
light only if switches ‘A’ and ‘B’ are both closed. FIG. 1.2 ( c) the bulb will light only if
switch ‘A’ is off indicating the ‘NOT’ function.
1.3 BOOLEAN ALGEBRA
Boolean algebra provides a symbolic representation of logical arguments which are
made up of logical statements. A Boolean expression will have Boolean variables and
operators.
From the discussion presented in section 9.1 above we may summarise the following in
connection with Boolean Algebra:
a) A Boolean variable can have one of two values ‘1’ or ‘0’.
b) The only operators permitted in Boolean algebra are ‘OR’ , ‘AND’ and ‘NOT’
FIG. 1.1 LOGIC GATES
LOGIC OPERATION
OR
AND
NOT
LOGIC DIAGRAM
ALGEBRAIC SYMBOLS
A
B
A+B
+
A
B
A.B
.
A
A’
’
FIG.1.2 SWITCHES TO SHOW ‘OR’ AND ‘AND’ OPERATION
a) OR operation
b) AND Operation
A
Battery
A
B
B
Battery
Bulb
Bulb
c) NOT Operation
A
1.3.1 Some Basic Postulates of Boolean Algebra
We may enumerate some basic postulates of Boolean Algebra mainly to highlight its
differences with conventional algebra and also to familiarise with symbolic logic.
a) A+ 0 = A
b) A+1 = 1, In fact 1 OR anything will be 1 as , as long as one of the inputs for
the
OR operation is true the output will be true.
c) A. 0 = 0 , 0 AND anything will be 0 as all the inputs for the AND operation
must
be true for the output to be true.
d) A.1 = A
e) A+ A’= 1, As if A is 0 , A’ will be 1 and if A is 1 ,A’ will be 0. 1 OR anything
is 1
A+A’ , is Tautology as its value is always true.
f) A. A’ = 0, As either a or A’ will be 0 as 0 and anything is 0.
A.A’ is Fallacy as its value is always false.
Proof: A+A= (A+A).1=(A+A)(A+A’)=A+A.A’=A
g) A+A= A
Idempotent Law
h) A. A = A
i) A.B=B.A
LHS=RHS
Proof: A.A=A.A+0=A.A+A.A’=A(A+A’)= A.1=A
Proof : By making the truth table and showing
Commutative Law
j) A+B=B+A
k) (A+B)+C=A+(B+C)
Proof: By truth table
Associative Law
l) (A.B).C=A.(B.C)
m) A+ AB = A ,
Proof: A+AB= A( 1+ B) = A. 1= A
Absorption Law
n) A.(A+B)=A
o) A.(B+C)=AB+AC
Distributive Law
p) A+BC=(A+B).(A+C)
q) A’’ = A
Proof: (A+B).(A+C)=AA+AC+AB+BC
=A(1+A+C+B)+BC
=A+BC
Involution
r) A+ A’B = A+B
AB+AB=AB
A(B+B’)+A’B = AB+AB’+ A’B+AB
since
= A(B+B’)+B(A+A’) =A+B
1.3.2 De’Morgan’s Theorems
De’Morgan’s Theorems’ are useful in changing the forms of Boolean expressions . The
two theorems are:
i) The complement of the sum is equivalent to the product of individual
complements.
( A+B)’ = A’ . B’
Proof: The truth table for the expression is as shown in Table 1.4 below:
From table 1.4 it may be observed that for all possible input combinations of A and B
the LHS (Left Hand Side) is the same as RHS ( Right Hand Side). The table thus shows
the proof of the theorem.
ii) The complement of the product is equal to the sum of individual
complements.
(A.B)’ = A’ + B’
Proof: The truth table for the above expression is shown in Table 1.5
From Table 1.5 it is observed that the LHS and RHS of the expression have the same
value for all possible input combinations of ‘A’ and ‘B’. The theorem is thus proved.
1.3.3 Proof of De’ Morgan’s theorem by induction
I) To prove (A+B)’ = A’.B’
Now as (A+B). A’.B’=0 and (A+B) + A’.B’ =1
X
. Y =0
X
+
Y
=1
X’ = Y
(A+B). A’.B’ = A’.B’. (A+B)
*ANDing both sides by (A+B)
= A’. B’ . A + A’. B’. B
= A.A’.B + A’.B’. B
= 0. B + A’. 0
* A . A’ = 0
= 0+0
= 0
A + B + A’.B’ = (A+B+A’).( A+B+B’)
= (1+ B).(A+1)
= 1.1
=1
i.e.,
(A+B)’ = A’.B’
II) To prove (A.B)’ = A’ + B’
Now as A.B (A’ + B’) = 0 and A.B + (A’+B’) = 1
X . Y
=0
X’ = Y
X +
Y
=1
A.B( A’+ B’) = A.B.A’ + A.B.B’
= A.A’.B + A.B.B’
= 0.B + A.0
= 0+0=0
A.B + (A’ + B’) = (A’ + B’ + A). (A’ +B’ + B)
= ( 1+B’).(A’ +1)
=1.1 =1
i.e., (A.B)’ = A’ + B’
TABLE 1.4 DE’ MORGAN’S THEOREM
A
B
LHS= (A+B)’
RHS= A’ . B’
0
0
(0+0)’= 0’ = 1
0’. 0’= 1.1 = 1
0
1
(0+1)’= 1’ = 0
0’.1’= 1.0 = 0
1
0
(1+0)’= 1’= 0
1’.0’= 0.1 = 0
1
1
(1+1)’= 1’= 0
1’.1’= 0.0 = 0
TABLE 1.5 DE’MORGAN’S THEOREM
A
B
LHS= (A .B)’
RHS= A’+. B’
0
0
(0.0)’= 0’ = 1
0’+ 0’= 1+1 = 1
0
1
(0.1)’= 0’ = 1
0’+0’= 1+1 = 1
1
0
(1. 0)’= 0’= 1
1’+0’= 0+1 = 1
1
1
(1+1)’= 1’= 0
1’+1’= 0+0 = 0
1.4 TRUTH TABLES
While writing truth tables the following points should be remembered:
a)
b)
c)
d)
A truth table with ‘n’ inputs should have 2n rows.
All inputs are entered in the left most column of the truth table.
Outputs are entered in the right most column.
The order of inputs should be such that the decimal values obtained from the
conversion of bits should be in ascending order row wise.
1.5 PRINCIPLE OF DUALITY
According to this principle, For every valid expression in Boolean Algebra there exists
an equally valid dual expression. The dual expression can be obtained by following the
following three steps:
i) Complement each 0 and 1 (Change the 0’s to 1’s and 1’s to 0’s)
ii) Replace each OR (+) sign by AND (.) and each AND (.) sign by OR (+)
iii) Leave NOTs unchanged.
The dual of
i) X.1 = X is X + 1= X
ii) X + (YZ) is X . (Y+ Z)
iii) X.(Y+Z) is X+ (Y.Z)
1.6 SIMPLIFICATION OF BOOLEAN (LOGICAL) EXPRESSIONS
We have already seen a number of identities and also the De’ Morgans theorems. These
can be used in reducing Boolean expressions. The main purpose of reducing Boolean
expressions is to implement the logic with the use of minimum hardware. The
minimisation of hardware would involve reducing the the number of inputs to a logic gate
and also the number of gates without altering the truth table of the expressions. In other
words simplifying the logical argument without beating around the bush.
The following examples demonstrate the utility of the identities and De’ Morgan’s
theorems in reducing Boolean expressions:
Ex 1.1
Reduce the following expressions to the minimum.
i ) A’BC (ABC+A’B’C’ + A’B +ABC’)
= 0+ 0 +A’B + 0
* Opening the parenthesis
= A’BC
ii ) (A’+B+C)(A’+B’+C’)(A’+B’+C)
= (A’.A’+A’.B’+A’.C’+A’B+BB’+BC’+A’C+B’C+CC’)(A’+B’+C) *Opening
the first
two
parentesis
= ( A’+A’B’+A’C’+A’B+0+BC’+A’C+B’C+0)(A’+B’+C)
*Using
A’A’=A’
and CC’=0
= ( A’+BC’+B’C)(A’+B’+C)
*A’+A’B’=A’
= (A’A’+A’B’+ A’C+A’BC’+0+0+A’B’C+B’B'C+B’CC)
= A’+B’C
*A’(1+ ..........) =A’
Ex. 1.2
Reduce the following
i ) A(BC)’ + (ABC)’
= A(B’+C’)+A’+B’+C’
= AB’+AC’+A’+B’+C’
= B’(A+1)+C’(A+1)+A’
= B’+C’+A’
ii ) (A+(B+C)’)(A+B+C)’
* Using De’ Morgan’s theorem
= (A+B’C’)(A’B’C’)
= 0+ A’B’C’
= A’B’C’
*Using De’ Morgan’s theorem
Ex. 1.3
Reduce the following
i ) (xyz+x(yz)’+ xy’z)’
= (xyz)’. (x(yz)’)’ . (xy’z)’
* Removing the outermost complement
using
= (x’+y’+z’)( x’+(yz)’’)(x’+y’’+z’)
De’Morgans theorems
= (x’+y’+z’)(x’+yz)(x’+y+z’)
= (x’+x’yz+x’y’+0+x’z’+0)(x’+y+z’)
= x’(1+ yz+ y’+z’)(x’+y+z’)
= x’( 1)(x’+y+z’)
* 1 OR anything will be 1
= x’+x’y+x’z’
= x’(1+y+z’)
= x’
ii ) ((x+y+z)’ + (xyz)’)’
= (x+y+z)’’ . (xyz)’’
= (x+y+z).xyz
= xyz+xyz+xyz
= xyz
iii) (x (yz)’ ((xy)’z(xyz)’+xyz’+x(yz)’))’
= x yz ( xy z . xyz + xy z + x yz)
= x yz + xy z . xyz +xy z + x yz
= x + yz + xy z + xyz .xy z . x yz
= x +yz + (xy + z + xyz.( x+y +z).(x +yz)
= x + yz + xy+z = x + y + z
*Using A’ + AB= A’+B
1.7 CANONICAL FORMS OF BOOLEAN EXPRESSIONS
Canonical forms are standard forms. Let us consider the Boolean expression in three
variables whose truth table is shown in table 1.6
From truth table 1.6 we have the Boolean expression :
A’B’C’ + AB’C + ABC’ +ABC = 1
...................................I
TABLE 1.6 TRUTH TABLE
OF EXPRESSION A’B’C’ + AB’C + ABC’ +ABC = 1
A
B
C
F= VALUE OF THE
EXPRESSION
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
In this expression we see that there are four terms and each term contains all the variables
which occur in the expression. The expression is true for any of the terms which occur in
the expression. Each one of the product terms which occur in the expression having all
the variables of the expression is called a min term and the expression itself is in min
terms canonical form.
From the same truth table 1.6 we can also write the following expression :
A’B’C+A’BC’+A’BC+AB’C’ = 0
.....................................II
Normally the Boolean expression is written for a true value. If we commplement both
sides of expresion II we have:
(A’B’C+A’BC’+A’BC+AB’C’)’ = 0’
or (A+B+C’)(A+B’+C)(A+B’+C’)(A’+B+C) = 1
....III
*By using De’Morgan’s theorem
Scrutinising expression III we see that each sum term in the product of sums has all the
three variables of the expression. Each one of these terms is called a max term and the
expression III is an expression in max terms canonical form or Product Of Sums (POS)
canonical form .
1.8 THE THREE VARIABLE KARNAUGH MAP
From the truth table we can make a Karnaugh Map, these maps are very useful in
reducing Boolean expressions as we shall see shortly. While making a Karnaugh map it
must be ensured that in adjacent cells of the map only one variable should change. The
Karnaugh map for the truth table 1.6 is shown in FIG. 1.3
FIG 1.3 KARNAUGH MAP FOR TRUTH TABLE 9.6
The expression is A’B’C’ + AB’C + ABC’ +ABC = 1
A’B’
C’
1 (0)
C
0 (1)
A’B
0 (2)
0 (3)
AB
1 (6)
1 (7)
AB’
0 (4)
1 (5)
In FIG 1.3 the truth values in each cell are reproduced from the truth table 1.6 and within
parenthesis the cell numbers are marked for ready reference. We may also observe that
only one variable varies in adjacent cells. The Karnaugh maps may be folded from left to
right and also from top to bottom, thus cells (0) and (1) are adjacent and cells (0) and (4)
are also adjacent. Cells (1) and (5) are adjacent but cells (0) and (5) are not adjacent. Let
us take cell (0) in this the variables are A’B’C’ and in cell (5) the variable are AB’C thus
A and C change in these two cells so they are not adjacent.
Let us now consider the two adjacent cells (6) and (7) . Considering these two cells alone
we get the expression :
ABC’+ABC = 1 i.e., AB(C+C’) = 1 , i.e., AB = 1 . The variable C which changes in
these two cells gets eliminated. We can thus presume that if we have a pair of 1’s in
adjacent cells we can eliminate one variable. FIG. 1.4 shows the combinations which can
be made to reduce the Boolean expression I.
FIG 1.4 REDUCING THE EXPRESSION WITH KARNAUGH MAP
The expression is A’B’C’ + AB’C + ABC’ +ABC = 1
C’
C
A’B’
1 (0)
0 (1)
A’B
0 (2)
0 (3)
AB
1 (6)
1 (7)
AB’
0 (4)
1 (5)
We have an isolated 1 in the cell A’B’C’ and two pairs in cells ABC’, ABC and ABC,
AB’C as shown enclosed in boxes.
The reduced expression thus becomes A’B’C’+AB+AC=1..
From the
Karnaugh map 1.4 we
also
get
expression
II, i.e.,
A’B’C+A’BC’+A’BC+AB’C’ = 0 . We may consider the adjacent cell 0’s. We see that
we have 0’s in adjacent cells (1),(3) and (2)(3) and there is an isolated 0 in cell 4.
Eliminating the changing variable in adjacent cells we have A’C+A’B+AB’C’=0.
Complementing both sides of this expression we get the expression
(A+C’)(A+B’)(A’+B+C) = 1. Thus from the same Karnaugh map we can get two
reduced expressions which are true, one in a Sum of Products (SOP) form and another
in a Product of Sums(POS) form.
The expression
A’B’C’ + AB’C + ABC’ +ABC = 1 as f(A,B,C) =
Products of cell numbers 0, 5, 6 and 7
( 0, 5, 6,7) i.e. Sum of
and the expression
(A+B+C’)(A+B’+C)(A+B’+C’)(A’+B+C) = 1 as f(A, B, C) =
Product of Sums of cells 1, 2, 3 and 4..
( 1, 2, 3, 4) i.e., the
1.8 THE FOUR VARIABLE KARNAUGH MAP
The Karnaugh maps in theory can be drawn for Boolean expressions with any number of
variables. We shall however restrict or discussions up-to four variables. In section 1.7 we
had restricted ourselves only to forming pairs with adjacent cells. We shall soon see that
we can combine adjacent cells making groups of 2n where n is an integer. Thus we can
combine adjacent cells 22 = 4 cells or quads 23 = 8 cells called Octets etc. A quad will
eliminate two variables, an Octet will eliminate three variables as we shall soon see.
Let us consider the Boolean expression:
F (A, B, C, D) =
( 0,1, 3, 4, 7, 8, 9, 11, 12)
The expression in sum of products canonical form is:
A’B’C’D’+A’B’C’D+A’B’CD+A'BC'D'|+A’BCD+AB’C’D’+AB'C'D+AB’CD+
ABC’D’ = 1 .............................I
Table 1.7 A shows the truth table for the expression alongwith the cell numbers and min
terms represented by each cell. FIG.1.5 shows the Karnaugh map for the expression with
cell numbers given in parenthesis. FIG. 1.5A shows that two quads ‘a’ and ‘b’ can be
formed by combining adjacent cells with a truth value of ‘1’ and a pair ‘c’ can also be
formed with truth value ‘1’ in adjacent cells. Let us now consider the two quads ‘a’ and
‘b’ and the pair ‘c’ individually.
From quad ‘a’ we get:
OR
OR
OR
OR
A’B’C’D’+A’BC’D’+ABC’D’+AB’C’D’ = 1
A’C’D’(B’+B)+ AC’D’(B+B’)= 1
A’C’D’+AC’D’= 1
C’D’(A’+A)= 1
C’D’ = 1
..........................i
Note that in this quad the variables A and B change and hence can be eliminated.
The truth table for the expression is shown in table 1.7
TABLE 1.7 TRUTH TABLE FOR F (A, B, C, D) =
CELL NO.
( 0,1, 3, 4, 7, 8, 9, 11, 12)
A
B
C
D
F
MIN TERM
0
0
0
0
1
0
A’B’C’D’
0
0
0
1
1
1
A’B’C’D
0
0
1
0
0
2
A’B’CD’
0
0
1
1
1
3
A’B’CD
0
1
0
0
1
4
A’BC’D’
0
1
0
1
0
5
A’BC’D
0
1
1
0
0
6
A’BCD’
0
1
1
1
1
7
A’BCD
1
0
0
0
1
8
AB’C’D’
1
0
0
1
1
9
AB’C’D
1
0
1
0
0
10
AB’CD’
1
0
1
1
1
11
AB’CD
1
1
0
0
1
12
ABC’D’
1
1
0
1
0
13
ABC’D
1
1
1
0
0
14
ABCD’
1
1
1
1
0
15
ABCD
FIG 1.5 KARNAUGH MAP
C’D’
A’B’
1 (0)
A’B
1(4)
AB
AB’
C’D
1(1)
CD
CD’
1 (3)
0(2)
0(5)
1(7)
0(6)
1(12)
0(13)
0(15)
0(14)
1(8)
1(9)
1(11)
0(10)
*The cell numbers are marked in parenthesis
FIG. 1.5 A
Reproducing the Karnaugh map without cell nos.
and combining adjacent cells
C’D’
A’B’
1
A’B
1
AB
1
AB’
1
C’D
b 1
a
CD
CD’
1
0
0
1
c
0
0
0
0
b 1
1
0
From quad ‘b’ (Obtained by folding or wrapping around the Karnaugh map) we get:
A’B’C’ D + A’B’CD + AB’ C’D+ AB’ CD = 1
OR
A’B’D(C’+C) + AB’D(C’+C) = 1
OR
A’B’D + AB’D = 1
OR
B’D(A’+A)= 1
OR
B’D = 1
.........................ii
Note that in this quad the variables A and C change and can be eliminated
From the pair ‘c’ we get:
A’B’CD + A’BCD = 1
OR
A’CD(B’+B)= 1
OR
A’CD = 1
.........................iii
Note that in this pair only the variable B changes and can be eliminated.
From i, ii and iii above we get:
C’D’ + B’D + A’CD = 1 ..................................................(X)
The original expression
(
A’B’C’D’+A’B’C’D+A’B’CD+A'BC'D'+A’BCD+AB’C’D’+AB'C'D+AB’CD+ABC’
D’ = 1) reduces to the expression (C’D’ + B’D + A’CD = 1) with the help of the
Karnaugh map.
The Karnaugh map of FIG. 1.5A is reproduced in FIG. 1.5B. We shall now reduce the
expression to obtain a simplified expression in product of sums form.
FIG.1. 5B SIMPLIFICATION FOR POS FORM
C’D’
C’D
A’B’
1
1
A’B
1
0
AB
1
CD
CD’
1
0
1
0
0
0
b
0
c
AB’
1
1
a
1
0
Combining the 0’s we get the following simplified expression:
CD’ (FROM QUAD ‘A’) + BC’D (FROM PAIR ‘b’) + ABD (from pair ‘c’) = 0
complementing both sides we have:
CD’ + BC’D + ABD = 0
OR
(CD’)’. (BC’D)’. (ABD)’ = 1
OR (C’ + D). ( B’+C+D’). (A’+B’+D’) = 1 ..........................(Y)
Note : You may verify that if all the cells in a Karnaugh map contain a 1 then the
sum of all min terms will be 1 and the Boolean expression will be true for all
possible input combinations. Similarly if all cells are 0 then the output is false for
possible input combinations.
SUMMARY : In this chapter we have seen that with the help of two state logic arithmetic
as well as logical problems could be solved. There are only three basic logic gates, OR,
AND and NOT. Algebra developed by George Boole is extensively used in designing
logic circuits and is the basis on which digital electronic computers are designed.
Truth tables for Boolean expressions show the output of the expression for all possible
combinations of the input. They represent the argument stated by the expression. The
Boolean expressions could be represented in sum of products or product of sums
canonical forms. Karnaugh map is a useful tool for simplifying Boolean expressions.
QUESTIONS FOR REVIEW
Q.1. What do you understand by binary state and what is its significance in the study of
digital
electronic computers ?
Q.2. Which are the basic logic gates and name some combinational gates. What is the
difference
between basic logic gates and combinational logic gates.
Q.3. What do you understand by a Truth Table? Give the truth tables for basic logic
gates.
Q.4. What is the speciality of Boolean algebra? Why is it so useful in designing
computers?
Q.5. Explain how logic gates could be used to add bits.
Q.6. Give examples of how logic gates could be used to represent logical arguments.
Q.7. Simplify the following Boolean expressions :
a) A(BCD)’ + A(BC)’ D(A’BC’D+AB’CD+A(BCD)’)
b) (xyz’ + (xy)’z + x(yz)’ )’
c) (AB’+ CD’ + A(BC)’ + (AB)’CD + (ABC)’ D)’
Q.8. Simplify the following expressions using Karnaugh maps, implement each of
the
expressions using only NAND gates and also by using only NOR gates:
a) f(a,b,c,d) =
(1,2,5,6,8,9,10,13,14,15)
b) f (x,y,z) =
( 0,3,4,5,6)
CHAPTER II
COMPUTER HARDWARE
CONTENTS
Elementary logic gates and Combinations of logic gates
Uses of logic gates in circuits
Applications of Boolean Algebra and logic gates to build arithmetic and logic
circuits
Multivibrators
Microprocessor Applications
2.1 LOGIC GATES
We have seen the basic logic gates, namely, OR AND and NOT in section 1.2 in chapter
I
With the help of the basic logic gates shown in the FIG. 1.1 some combinational gates as
shown in FIG. 2.1 are built which are very commonly used. These gates and their truth
tables are shown in FIG. 2.1. The NOT gate following the OR gate results in a NOR gate.
The NOT gate following the AND gate results in a NAND gate. The combination of
basic gates required to form the EXCLUSIVE OR (EX-OR) gate is also shown in FIG.
2.1. The EX-OR gate is very useful and is also used for constructing the adders as will be
shown in the next section. The EX-OR gate gives a true output if the inputs are not
similar. For similar inputs the EX-OR gate gives a false output. In the truth tables shown
in FIG. 2.1 ‘1’ represents true and ‘0’ represents false . The EXCLOSIVE NOR (EXNOR) gate gives a true output for similar inputs. The NAND gates and NOR gates are
called universal building blocks as any logic can be implemented by using either NAND
gates alone or NOR gates alone, as will be shown later in this chapter.
FIG. 2.1 COMBINATIONAL LOGIC GATES
COMPONENTS
LOGIC DIAGRAM
A
B
A
B
A’
A
A
B
A
B
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
0
NAND
0 0
0 1
1 0
1 1
1
1
1
0
EX-OR
0
0
1
1
0 0
1 1
0
1
1 0
EX-NOR 0
0
1
Y=(A’B+AB’)’
1
0 1
1 0
0 0
1 1
Y=( A . B)’
Y=A’B+AB’
A
B
TRUTH TABLE
NOR
Y=(A+B)’
A’B
B
GATE
AB’
B’
A’
A
A’B
B
A
B
A
B
AB’
B’
2.2 USING LOGIC GATES TO ADD BITS
Adding two bits
We can use a combination of logic gates to add two bits. Let us say that the two bits to be
added are ‘A’ and ‘B’. Each of these bits may have a value of ‘0’ or ‘1’ . Taking all
possible combinations of ‘A’ and ‘B’ their sum in binary will be as shown in TABLE 2.1
below: The logic diagram for the implementation of the half adder is shown in FIG. 2.2
(a)
TABLE
2.1 SUM OF TWO BITS
SUM OF TWO BITS
‘A’ and ‘B’
TRUTH TABLE FOR LOGIC DIAGRAM
OF HALF ADDER (FIG.9.3)
A
B
SUM
A
B
Ci
S
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
1
0
0
1
1
1
10
1
1
1
0
The Boolean expressions for the carry (Ci) and sum ( S) seen from the above truth tables
will be:
Ci = A.B and S = AB’+A’B
Adding three bits
The logic diagram for adding three bits (full adder) is shown in FIG 2.2 (b) and the truth
table for this logic diagram is shown in TABLE 2.2. We may observe from the logic
diagram of the full adder shown in FIG. 2.2 (b) that if two half adders are cascaded and
the carry outputs of the two half adders input to an OR gate for generating the carry we
can add one more bit. Similarly if a number of half adders are cascaded we can add more
and more bits. In an Integrated Circuit ( IC) a number of half adders could be cascaded to
enable addition of a number of bits.
You may verify from the truth table of the full adder that the Boolean expressions
for the carry ‘Ci’ and the sum ‘S’ are as follows:
Ci = A’BC+AB’C+ABC’+ABC
S = A’B’C+A’BC’+AB’C’+ABC
We can use logic circuits for adding the complement of negative numbers to perform
subtraction. Since multiplication is repeated addition and division is repeated subtraction,
all arithmetic operations can be performed by using logic gates.
TABLE 2.2 SUM OF THREE BITS
A
B
C
Ci
S
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
1
0
0
1
2.3 UNIVERSAL BUILDING BLOCKS
In section 2.1 above it was mentioned that with the help of ‘NAND’ gates alone or
‘NOR’ gates alone any logic can be implemented. The basic gates are ‘OR’, ‘AND’ and
‘NOT’. It therefore follows that if these three basic gates can be implemented , any logic
can be implemented. In FIG. 2.3A implementation of the basic gates by ‘NAND’ gates
is shown. and in FIG. 2.3B implementation of the basic gates by ‘NOR’ gates is shown.
The NAND gates alone could be used to implement any logic as it is possible to
implement the basic gates (OR, AND and NOT) using NAND gates. Similarly NOR
gates alone could be used to implement any logic. Production of only one type of gates
would be more convenient than production of an assortment of gates. The NAND gates
are universal building blocks.
2.4 USING LOGIC GATES TO IMPLEMENT LOGICAL ARGUMENTS
We have seen in section 2.2 how logic gates could be used to perform arithmetic
functions. The logic gates could also be used to implement logical arguments. Let us say
I have two friends, A and B. B plays badminton, A plays tennis and all of us play cricket.
I have a holiday and I invite both my friends. Four situations could arise as follows:
i ) If non of my friends come I shall read a book.
ii ) If only B accepts my invitation I shall play badminton with him.
iii) If only A accepts the invitation I shall play tennis with him.
iv) If both come we shall all play cricket.
FIG. 2.4 shows how this argument can be implemented using Logic gates.
In FIG. 2.4 there are two inputs ‘A’ and ‘B’. These inputs are fed two AND gates either
in complemented or uncomplemented form . If the inputs are uncomplemented they are
represented by ‘1’ (True) and if they are in uncomplemented form they are represented by
‘0’(false). One of the four outputs of the AND gates will be true depending whether the
inputs are true or false. If ‘A’ and ‘B’ are both absent, then ‘A’ and ‘B’ will both be ‘0’
and their complements ‘1’, so the top most AND gate will give a True output and all
other AND gates will give a False output. Under these conditions I shall read a book.
Proceeding similarly for other values of ‘A’ and ‘B’ as shown in the truth table one of the
output paths will be selected.
Two inputs enable us to select from 4 output paths. Three inputs will enable selection
from among 8 output paths. for selection from among ‘2n’ output paths we will require n
inputs.
FIG. 2.4 THE
A
TABLE
B
DECODER (MULTIPLEXER)
No invitation accepted
TRUTH
Read a book
A
B
ACTION
0
0
0
1
1
0
1
BOOK
1
BADMINTON
Only ‘B’ Accepts invitation
Play badminton
TENNIS
CRICKET
Only ‘A’ accepts invitation
Play Tennis
Both accept invitation
play cricket
The FIG. 2.4 shows the logic diagram for a 2 x 4 decoder or multiplexer. We can have 3
x 8,
4 x 16, 5 x 32 etc. decoders, the first digit indicating the number of inputs and the second
figure indicating the number of output selections possible. Thus in a 3 x 8 decoder we
will need 3 inputs to select one of 23 = 8 outputs.
Let us now consider another situation. I have decided to go out, that is the output is
decided. Now, I have a choice of shirts Red, Blue, Green and Yellow. If I want a logic
circuit which make the decision, two switches ‘X’ and ‘Y’ will be needed as they give 4
possible combinations.
The FIG. 2.5 shows a 4 x 2 Encoder, similarly we can have 8 x 3 , 16 x 4 etc., encoders
the first number indicating the number of input options and the second number indicating
the number of switches required for selection. The OR gate at the output ensures that the
output will always be true and would have selected one of input options.
FIG. 2.5 ENCODER (DEMULTIPLEXER)
X
Y
TRUTH TABLE
Red
Blue
X
Y
SHIRT
0
0
1
1
0 RED
1 BLUE
0 GREEN
1 YELLOW
GO OUT
Green
yellow
If we have only NAND gates it is easy to implement the SOP form of expressio and if we
have only NOR gates it is easy to implement the POS form of the expression as show
shown in FIG 9.11
2.5 IMPLEMENTING
BLOCKS
EXPRESSIONS
USING
UNIVERSAL
BUILDING
We have seen in section 2.3 that the basic logic gates can be implemented by NAD gates
alone or NOR gates alone. Thus we need only manufacture only one type of universal
gates to enable us to implement any Boolean expression . Fig. 2.6 shows how expressions
may be implemented using the universal gates.
FIG. 2.6 IMLEMENTION OF EXRESSIONS WITH UNIVERSAL GATES
A (USING NAND GATES)
GATES)
EXPRESSION(X) C’D’ + B’D + A’CD = 1
(A’+B’+D’) = 1
B (USING NOR
EXPRESSION (Y) (C’ + D). ( B’+C+D’).
C’
C’
D’
D
B’
D
B’
C
D’
A’
B’
D’
A’
C
D
C (USING ONLY NOR GATES)
The expression: (A+C’)(A+B’)(A’+B+C) = 1.
A’
B
C
(A’+B+C)’
((A’+B+C)’+(A+B’)’+(A+C’)’)’
A
B’
(A’+B+C)(A+B’)(A+C’)
A
C’
(A+C’)’
D ( SAME EXPRESSION IMPLEMENTED USING VARIETY OF GATES AND
ONLY NAND GATES)
The expression A’B’C’+AB+AC=1. Can be implemented using a variety of gates and
using only NAND gates
Using a variety of gates
A’
B’
C’
A
A’B’ C’
AB
B
A’B’C’+AB+AC
A
C
AC
Using only NAND gates
The expression A’B’C’+AB+AC=1..
A’
B’
C’
( A’B’C’)’
((A’B’C’)’.(AB)’.(AC)’)’ =
A
A’B’C’+AB+AC
A
C
(AC)’
In the FIG. 2.6 D A the simplified Boolean expression is implemented without any
restriction on the type of gates used and using only NAND gates and FIG. 2.6 C
implements the expression in POS form using only NOR gates. It may be observed that it
is easy to implement an expression in SOP form using only NAND gates and the
expression in POS form using only NOR gates. The original expressions in SOP form
and POS form may also be written as follows:
It is easy to implement the expression (X) using only NAND gates and implement
expression (Y) using only NOR gates as shown in FIG. 2.6A and 2.6B
2.6 MULTIVIBRATORS
Multivibrators are regenerative circuits with two active devices, designed so that one
device conducts while the other cuts off. The multivibrators can store binary numbers,
count pulses and perform other essential functions in digital electronic systems. Any
device which has two stable states is said be bistable.A toggle switch has two stable
states. A switch may be presumed to have memory, since once ON it will remain ON till
someone changes the position of the handle. A flip-flop is a bistable electronic circuit and
can be used to store one binary digit, either 0 or 1. An input pulse could be used store a 1
and another pulse to store a 0. Let us study the operation of Fig. 2.7. We have two NOR
gates connected in the manner shown . The circuit has two outputs Q and Q'. It may be
observed from the truth table that if S is set to 1, Q output will be 1 (Set) and if R is set
to 1(Reset) Q output will be 0. If both S and R are 0 the last value stred will be retained
and if both S and R are 1 the output cannot be predicted (Forbidden condition). The flipflop so constructed can be used to store binary information and is an example of a
bistable multivibrator.
FIG. 2.7 NOR GATE FLIP FLOP
R
Y= Q
S
Y=Q'
TRUTH TABLE
R
0
0
1
1
S
0
1
0
1
Q
Last Value
1
0
?
ACTION
No Change
Set
Reset
Forbidden
In an astable multivibrator non of the output states is stable. The output will continuously
toggle between 1 and 0 and can used to generate clock pulses.
The monostable multibrators have only one stable state. The normal mode of operation is
to trigger the multivibrator into its quasistable state, in which it will remain for a
predetermined length of time and the go back to its stable state. These multivibrators are
widely used in industryfor timing operations. The logic symbols and waveform for the
monostable multivibrator is shown in Fig. 2.8
FIG. 2.8 THE MONOSTABLE MULTIVIBRATOR
Q
1
Trigger
0
Q'
Q
Trigger
1
0
Logic Symbol
Wave forms
2.7 MICROPROCESSOR OPERATIONS
The processor which processes the information stored in the main memory and performs
the arithmetic and logic functions is referred to as the central processing unit ( CPU).
The logic circuits required to perform the operations of CPU may be distributed among
several chips on several printed circuit boards. A microprcessor is a single integrated
circuit (IC) i.e., a chip that performs the functions of the CPU. The design of
microprocessors differs from manufacturer to manufacturer. The design of an Intel
microprocessor will be different from that of a Motorola microprocessor. We shall
describe a hypothetical design which encorporates the basic design functions of a
microprocessor, referred to as a processor or CPU henceforth in this chapter. The CPU
has some salient registers which are similar to memory locations but have some
additional logic associated with them. The main registers are shown in FIG. 2.9 and their
functions are as follows
FIG. 2.9 (a) THE CENTRAL PROCESSING UNIT
(b)
FIG. 2.9
MAIN MEMORY
PC
MAR
IR
INSTRUCTIONS
MBR
GPR 1
GPR 3
GPR 2
DATA
GPR’S
Program Counter (P C): The program counter contains the address of the next
instruction to be executed. The PC will never contain the address of the operand (On the
data on which the instruction is to be performed). On receiving the address the first
instruction to be executed the PC passes on the address to the Memory Address Register
(MAR) and before the instruction is executed, the address in the PC will be changed to
point to the address of the next instruction to be executed. The PC is also referred to as
the Current Instruction Register (CIR) though it points to the next instruction to be
executed.
Memory Address Register (MAR): The contents of the MAR is the address of the
memory location whose contents are to be fetched and brought for processing to the
processor. If the address in the MAR has been received from the PC the contents of the
memory location will be brought to the Instruction Register (IR) for decoding the
instruction. If the address in the MAR has been received from a register other than the
PC, then the address refers to the address of an operand and the contents of that operand
will not be brought to the IR but will be taken to a register or a destination in the
processor as directed by the instruction.
Instruction Register (IR): The moment the instruction comes to the IR its decoding
commences. The instruction has two components i.e., the operation to be performed
called the op code and the address specifications . The logic circuits required to be
activated (switching sequence) to perform the operation will be activated the moment the
instruction comes to the instruction register and simultaneously the process of computing
the operand and fetching the operand will commence to enable execution of the
instruction. If the address of the operand pertains to a main memory location, the address
is given to the MAR. The contents of the address indicated by the MAR now will not be
taken to the IR as the address was not received from PC. The contents of the memory
location will now be taken to wherever the instruction has directed.
Memory Buffer Register (MBR): All information that comes to or goes from the
processor must pass through the Memory Buffer Register (MBR). The MBR thus
regulates the traffic from and to the processor. The MBR is also referred to as the
Memory Data Register (MDR). In this book MBR is preferred to MDR as the instructions
as well as data will pass through it and it indeed acts as a buffer between the processor
and the main memory to cater for the speed mismatch between the two.
Processor Status Register (PSR): The processor status register keeps a track of the
conditions occurring in the processor. The Operating System monitors the contents of
this register to keep a track of the processor for managing it (Processor Management
Function of the O/S). Each bit in this register signifies some condition and these bits are
referred to as flags. Some common flags are are C-to indicate the occurrence of a
carry, O-To indicate overflow, Z-to indicate a zero result, S- to indicate the sign of
the result. These bits are very useful in checking conditions for branching.
General Purpose Registers (GPR’s): In addition to the above special purpose registers
the processor may have a number of General Purpose Registers (GPR’s) . These are
used as scratch pads by the processor to store intermediate calculations or store
information temporarily during the execution of an instruction. In FIG. 2.9 (a) above
these are shown as R1 , R2 , R3 etc.
2.7.1 INSTRUCTION EXECUTION CYCLE
Having described the salient registers in the processor, we may now review the steps
involved in executing an instruction by the processor. FIG. 2.7(a) showing the salient
registers in a processor and FIG. 2.7 (b) showing the main memory will be useful in
following the instruction execution cycle.
The starting address of the program to be executed is given to the PC. The PC passes on
this address to the MAR. The contents of the memory location indicated by the MAR are
reproduced in the IR. As the decoding of the instruction commences on reaching the IR
the PC increments to the next instruction to be executed , without waiting for the
execution of the current instruction by the processor. The IR sends the operation code for
decoding and activating the logic circuits for performing the operation. Simultaneously
the IR also sends the address specifications for decoding and computing the address of
the operand. On computing the address of the operand the address is sent to the MAR.
The contents of the memory location indicated by the MAR are now not taken to the IR
but will be operated upon and the result taken to the destination indicated by the
instruction. On execution of an instruction the next instruction to be executed , as
indicated by the PC is taken up for execution.
2.7.2 CONTROL FUNCTIONS
The actual change of state from one to another takes place only on the arrival of a master
clock pulse . The master clock in the computer system generates a frequency of electronic
pulses and these pulses control the timings of all internal operations in the processor. The
higher the frequency of the master clock, the greater will be the speed of execution of
instructions. The change of state e.g., suppose the PC has the address of the next
instruction, this address will remain there or the state will not change till the clock pulse
arrives. When the clock pulse arrives the address may be shifted to the MAR. Thus the
actual change of states are referred to as control functions. On accessing an Input/Output
system , whether the information is to be input (read) or output (written) is also a control
function. The logic circuits required to perform the control functions are distributed all
over the computer system. At times conceptually it is said that the control functions are
performed by the control unit, though physically there is no control unit in the computer
system
SUMMARY: In this chapter we have seen that the basic logic gates may be combined to
form more complex logic gates. The logic gates could be interconnected to solve
arithmetic and logical problems.Any logic could be implemented if we have NAND or
NOR gates alone and these gates are called universal building blocks. Multivibrators
are elctronic switches and are used for storing, timing and other logic functions.The
microprocessor consists of several registers, which in addition to storing information
temporariry perform some specific functions. The instruction and operands need to be
fetched from the memory to execute an instruction.
QUESTIONS FOR REVIEW
Q.1 Which are basic logic gates? Implement AND and OR gates using only i) NAND
gates
and ii) Using only Nor gates.
Q.2. Show the logic diagram for implementing the EX-OR gate using the basic gates.
And writ the truth table for the resulting EX-OR gate. Why is it popular?
Q.3. Explain the circumstances under which you would choose an encoder and a
decoder.
Implement a decoder using only NAND gates.
Q.4. Imlement a logic circuit for adding four bits.
Q.5 What are multivibrators? Explain the difference between an astable and monostable
multivibrator
Q.6 Explain the purpose of the following registers in a processor:
a) The program counter.
b) Memory Address Register.
c) Instruction Register.
d) Memory Buffer Register
e) Processor Status Register.
.
Q.7. Trace out the sequence of events that would take place in executing a machine
language
instruction stored in the main memory of the computer.
Q.8. What do you mean by the speed of machine? What factors would affect the speed of
the
machine ?
Things to do
1. Select suitable chips and build a circuit which will add three bits
2. Implement a circuit which will accept three bits and display the result in
decimal.