Visualization of Binary Decision Diagram
by Teh, Eugene Yee
Research Project
Submitted to the Department of Electrical Engineering and Computer Sciences,
University of California at Berkeley, in partial satisfaction of the requirements for the
degree of Master of Science, Plan II.
Approval for the Report and Comprehensive Examination:
Committee:
Professor A. Richard Newton
(Date)
*******
Professor Kurt Keutzer
(Date)
1
1.
Contents
1. Contents ................................................................................................................................... 2
2. Introduction ............................................................................................................................ 4
3. Background and Related Work ............................................................................................ 6
3.1 Formal Definitions ............................................................................................................ 6
3.1.1 Formal Definition of Binary Decision Diagram ................................................... 6
3.1.2 Formal Definition of Reduced Ordered BDD ...................................................... 6
3.2 BDD as Boolean Function Representation .................................................................... 7
3.3 ite Formulation of BDD ................................................................................................... 8
3.4 BDD Package Design Issues ............................................................................................ 9
3.5 Variable Ordering of BDDs ........................................................................................... 12
3.5.1 Memory Explosion Problem ................................................................................ 12
3.5.2 Circuit Classes and BDD Variable Ordering ..................................................... 13
3.5.3 Exact Ordering Algorithms ................................................................................. 14
3.5.4 Ordering and Circuit Structure .......................................................................... 15
3.5.5 Static Heuristic Algorithms ................................................................................. 15
3.5.6 Dynamic Variable Ordering (DVO) ................................................................... 16
3.6 Application of BDDs ......................................................................................................... 17
3.7 Variants of BDDs .............................................................................................................. 17
3.8 Scientific Visualization Techniques ................................................................................. 19
3.8.1 Data Flow Architecture ....................................................................................... 19
3.8.2 Scalar Mapping Technique ................................................................................. 20
3.9 Graph Visualization Algorithms ..................................................................................... 20
3.10 Existing BDD Visualization Techniques ...................................................................... 22
4. Motivations and Challenges in BDD Visualization ......................................................... 23
2
4.1 Large BDD Sizes .......................................................................................................... 23
4.2 Understanding Algorithmic Behavior ........................................................................ 24
4.3 Visualization for Education ......................................................................................... 25
5. Visualization Infrastructure .............................................................................................. 26
5.1 Visualization Operators ............................................................................................... 27
5.2 BDD Package ................................................................................................................ 28
5.3 Visualization Packages ................................................................................................ 29
5.3.1 DIVA - Dynamic Interactive Visualization Architecture ............................... 29
5.3.2 VisAD - Visualization for Algorithm Development ......................................... 29
5.4 User Interface ................................................................................................................ 31
5.5 Shared Data Space ........................................................................................................
5.6 Model View Controller .................................................................................................
5.7 View(s) ............................................................................................................................
5.8 Miscellaneous Implementation Issues .........................................................................
5.8.1 Java Native Interface (JNI) .................................................................................
6. Package Description ..........................................................................................................
6.1 Interaction Matrix Viewer .................................................................................................
6.1.1 Interaction Matrix Viewer 1: Graph Visualization ...............................................
6.1.2 Interaction Matrix Viewer 2: 3D-Blocks .................................................................
6.2 Statistical Monitor ...............................................................................................................
6.3 BDD Dump ...........................................................................................................................
6.4 Network Visualization .........................................................................................................
6.4.1 Network Visualization 1: Dump ...............................................................................
6.4.2 Network Visualization 2: Clique Color Bars ...........................................................
7. Visualization Results and Discussions .....................................................................................
7.1 Structural Correlation ........................................................................................................
3
7.2 Multiple Data Views ............................................................................................................
7.3 Algorithm Animation ..........................................................................................................
7.4 System Integration Architecture ........................................................................................
8. Conclusions and Future Work .................................................................................................
9. References ..................................................................................................................................
10. Appendices .................................................................................................................................
4
2.
Introduction
Digital systems can be represented very effectively using Boolean functions while their
interactions can be easily described using the Laws of Boolean Algebra. A central issue in
Computer-Aided Design (CAD) is to provide efficient data structures to represent Boolean
functions as well as fast algorithms to operate on these data structures. In recent years, binary
decision diagram (BDD) has emerged as the choice representation for Boolean functions in the
CAD community because of its compactness and canonicity, as well as the availability of
efficient BDD manipulation algorithms. As we will discuss in further detail in Section 3.1.1,
BDDs are essentially directed acyclic graphs (DAGs), hence many graph traversal algorithms can
be easily adapted to manipulate BDDs. This fact allows BDD packages to leverage the wellresearched field of graph algorithms.
Scientific visualization techniques are increasingly being used to help algorithm developers
understand high-level algorithmic behavior [EW93] [PAL93]. Visualization is particularly useful
when applied to heuristic algorithms operating on large data sets. This is a very common
situation in BDD construction and manipulation algorithms.
The goals of this project are stated as follows:

Apply effective techniques in the field of scientific visualization to expose interesting
characteristics of BDDs.

Provide visualizations to help algorithm developers better understand BDD algorithms.

Reveal structural correlation between different data representations, especially between good
BDDs and the circuit structures.
5

Utilize the information obtained from BDD visualization for further optimization of BDD
algorithms.
We will demonstrate the effectiveness of the visualization system in the analysis and design of
BDD variable ordering algorithms.
This concludes the general introduction to the report. Section 3 provides some necessary
background information on BDDs, review selected BDD algorithms, relevant scientific
visualization techniques, system architecture and relevant graph visualization algorithms, and
conclude with a brief summary of current research effort in BDD visualization. Section 4
illustrates a need for effective BDD visualization techniques. Section 5 discusses the architecture
of our visualization system. Section 6 presents the various visualization capabilities of our
system. Section 7 discusses some insights that we have gained from the results of BDD
visualizations. Lastly, Section 8 concludes the report and provides future directions.
6
3.
Background and Related Work
3.1
Formal Definitions
3.1.1
Formal Definition of Binary Decision Diagram
A BDD [BRY86] is a rooted DAG, G(V,E). The vertex set V is made up of two different types of
vertices; terminal and non-terminal. Each BDD has one or two terminal vertice(s) with out-degree
of zero and multiple non-terminal vertices, each with out-degree of exactly two. A terminal vertex
v, has attribute value(v) {0,1} . A non-terminal vertex v has attribute index(v)  {1,2,..,n} and
two children low(v), high(v)  V. The attribute index(v) specifies a linear ordering of the
variables in the support of the BDD; i.e. it satisfies the property such that for any non-terminal
vertex v, index(v) < { index(low(v)), index(high(v)) }.
3.1.2
Formal Definition of Reduced Ordered BDD
Reduced Ordered Binary Decision Diagram (ROBDD) extends the above definitions of BDD
with two additional constraints. Before these constraints are introduced, we will review the
definition of isomorphism in graph context.
Two (sub)-graphs rooted at v and w, G'(v) and G''(w) respectively are isomorphic if there
exists a one-to-one mapping : {VG’} {VG”}, from the vertices in G'(v) to the vertices
in G''(w) such that for every vertex v' in G', there is a vertex w' = (v') in G” which
satisfies the following conditions: either both v' and w' are terminal vertices with value(v')
7
= value(w') or both v' and w' are non-terminal vertices with index(v') = index(w'),
(low(v')) = low(w') and (high(v')) = high(w').
The additional constraints mentioned in the section above are presented as such:

An ROBDD has no isomorphic sub-graphs in its DAG.

An ROBDD has no redundant vertex in its DAG, i.e. there is no vertex v  V such that low(v)
= high(v)
For the rest of this report, BDD and ROBDD are used interchangeably to denote ROBDD unless
otherwise stated.
3.2
BDD as Boolean Function Representation
In a BDD, every sub-graph that is rooted at a vertex v represents a unique function fv. The DAG
rooted at the root r of the entire BDD represents the main Boolean function f = fr. A function fv is
stored in the data structure of the vertex v and is defined recursively as such:

If v is a terminal vertex such that value(v) = 0, then fv = 0, else if v is a terminal vertex such
that value(v) = 1, then fv = 1

If v is a non-terminal vertex such that index(v) = i, then fv = xi fhigh(v) + xi' flow(v), where the
variable order is x1 < x2 < … < xn and fhigh(v) and flow(v) represents the functions rooted at
high(v) and low(v) respectively.
The definition above describes a bottom-up construction of BDD. It is also informative to look at
a BDD using its top-down definition, which is based on Shannon's Decomposition Theorem:
f = xi . fxi + xi' . fxi'
8
where fxi and fxi' are f evaluated at xi = 1 and xi = 0, respectively. This theorem allows us to
construct a unique Boolean function at each vertex of the BDD G(V,E), starting from the root,
which represents the main function of the entire BDD. The construction is performed as such;
given a vertex v representing fv, and v with attribute index(v) = i, the functions represented by its
two children, low(v) and high(v) are flow(v) = fxi' and fhigh(v) = fxi, respectively. fxi’ and fxi are known
as the co-factors of f with respect to xi’ and xI, respectively.
3.3
ite Formulation of BDD
Shannon's decomposition theorem also provides the foundation for the recursive if-then-else (ite)
[BRB90] formulation of BDD. The ite operator is defined as follow:
ite(f,g,h) = f.g + f'.h
where f, g, h are arbitrary Boolean functions. It is a well-known fact that the ite operators can be
used to implement all Boolean functions with one or two operands, as shown in Table 1.
Table
Name
Expression
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
AND(f,g)
f>g
f
f<g
g
XOR(f,g)
OR(f,g)
NOR(f,g)
XNOR(f,g)
NOT(f,g)
fg
NOT(f)
fg
NAND(f,g)
1
0
f.g
f.g'
f
f'.g
g
f g
f+g
(f + g)'
(f g)'
g'
f + g'
f'
f' + g
(f.g)'
1
Equivalent
Form
0
ite(f,g,0)
ite(f,g',0)
f
ite(f,0,g)
g
ite(f,g',g)
ite(f,1,g)
ite(f,0,g')
ite(f,g,g')
ite(g,0,1)
ite(f,1,g')
ite(f,0,1)
ite(f,g,1)
ite(f,g',1)
1
Table 1. Two Argument Operators Expressed as ite operations
9
Let Z = ite(f,g,h) and v be the top variable of functions f, g, h. Then
Z = ite(f,g,h)
= v.Zv + v'.Zv' (Shannon Decomposition Theorem)
= v.(f.g + f'.h)v + v'.(f.g + f'.h)v'
= v.(fv.gv + f'v.hv) + v'.(f v'.g v' + f' v'.h v')
= ite(v, ite(fv,gv,hv), ite(fv',gv',hv'))
The terminal cases of this recursion are:
ite(1,f,g) = ite(0,g,f) = ite(f,1,0) = ite(g,f,f) = f
The pseudo-code for ite-based algorithm is presented in Appendix 10.1.
3.4
BDD Package Design Issues
We will now investigate some important design issues that will have to be considered in order to
implement an efficient BDD package [BRB90]. In this context, efficiency is described both in
terms of memory consumption and CPU requirements. Currently, most of the efficient and hence
popular implementations of BDD packages are based on the recursive ite formulation described
in Section 2.1. Table 2 summarizes some fundamental concepts and data structures used in these
implementations.
10
Concepts and Data Structures
Shared BDD
Brief Description and Analysis

A multiple-output Boolean function is represented as a single
multi-rooted BDD with a root for each function that are of
explicit interest to us.

This concept is based on the assumption that different
Boolean functions have common sub-expressions, and
representing these sub-expressions using one sub-graph rather
than multiple copies of identical sub-graphs reduces memory
consumption.
Unique Table

A dictionary of all functions represented in the current DAG.

Implemented as a Hashtable with collision chains.

(key, object) of the Hashtable is ( (index(v), low(v), high(v)) ,
*v) such that *v is the pointer to a BDD vertex.

Collision chains are implemented using an additional entry in
every BDD vertex data structure.

Provides a guarantee that there are no isomorphic (sub)graphs
in the DAG at any time. Maintains strong canonicity such that
any two equivalent functions always share the same subgraph.
Computed Table

Implemented as a Hash-based Cache.

Stores the results of recent computations, i.e. informs the
package if a certain ite(f,g,h) has been recently computed. If
so returns the resultant vertex that represents the function.

Result = ite(f,g,h).

Reduces the complexity of the ite recursions from
exponential in the size of input variables to polynomial in the
size of operand sub-graphs.
BDD vertex

Can be efficiently implemented using as few as 4 memory
word1.
1
A memory word is 4 bytes wide on 32-bit computers
11
reference-count || index(v), * high(v), *low(v) and *next (See
Figure 1)

*next implements the collision chain of the Unique Table

reference-count variable will be discussed in conjunction with
garbage collection

Each vertex v, represents a distinct Boolean function
f(xi,xi+1,..,xn) where index(v) = i.
Garbage Collection

Automatic garbage collection is based on the reference-count
value stored in the BDD vertex data structure above. When
sufficient units of BDD vertices have reference count = 0, this
mechanism is invoked

Releases memory occupied by dead vertices, and
appropriately update (rehash if necessary) the computed table
and the unique table.

The reference count value of a vertex v maintains the sum of
all other BDD vertices or user-defined functions that
reference v. v is a dead vertex if its reference count is zero.

The CPU cost garbage collection is amortized over all the
dead vertices at each invocation of the garbage collection
mechanism.
Table 2: Fundamental Concepts and Data Structures used in Efficient BDD Implementations
12
Figure 1: Memory Picture of a Vertex Data Structure (32 bit machine)
3.5
Variable Ordering of BDDs
3.5.1
Memory Explosion Problem
As stated in Section 3.1.1, BDDs are DAG representations of Boolean functions, and many
Boolean manipulations are modeled as graph traversal algorithms. The complexities of most
graph traversal algorithms are expressed in terms of the sizes of its input graphs, specifically the
number of vertices and the number of edges of these graphs. Consequently, BDDs with smaller
sizes (i.e. less vertices) are both more efficient representations of Boolean functions (in terms of
memory requirements) as well as more efficient models for Boolean computations (in terms of
CPU processing time requirements).
Based on its definition, the size of a BDD is exponential in the worst case. It is the focus of many
current researches to discover techniques that avoid situations in BDD algorithms when BDDs
approach exponential sizes- a situation commonly referred to as the memory explosion problem.
In this section we will discuss one of the most common way to address the memory explosion
problem - variable ordering.
13
3.5.2
Circuit Classes and BDD Variable Ordering
Figure 2: OBDD representations of f = a1b1 + a2b2 + a3b3 under different variable ordering
Figure 2 illustrates the importance of BDD variable ordering. Both BDDs represent the same
Boolean function f = a1b1 + a2b2 + a3b3, but with different variable orderings. The BDD on the
left-hand side of Figure 2 is ordered as a1 < a2 < a3 < b1 < b2 < b3 whereas the BDD on the righthand side is ordered as a1 < b1 < a2 < b2 < a3 < b3. The first BDD has fourteen non-terminal
vertices while the second only has six non-terminal vertices. This simple example can easily be
extended to n terms, f = a1b1 + a2b2 + a2b2 + ... + anbn. A non-interleaved order, a1 < b1 < a2 < b2
< a3 < b3 < ... < an < bn produces a BDD with 2n non-terminal vertices whereas the interleaved
ordering a1 < a2 < a3 < ... < an < b1 < b2 < b3 < ... < bn, produces a BDD with 2 n+1 non-terminal
vertices. One BDD has polynomial complexity whereas the other has exponential complexity.
BDD algorithms will efficiently handle the former BDD, whereas in the latter these same
algorithms will fail.
14
This simple example also provides important insights on how to perform BDD variable ordering
for this specific class of digital circuits, which includes the integer adder component of the
Arithmetic Logic Unit (ALU). Table 3 [BRY92] summarizes the asymptotic behavior of 3
different classes of Boolean circuits and illustrates the extent of their sensitivities to BDD
variable orderings. Symmetric functions such as the parity function always have small BDDs
regardless of their variable orderings, whereas integer multiplication circuits are proven [BRY91]
to have BDDs which are always exponential in the number of input variables, regardless of their
variable orderings. However, most other useful Boolean functions belong in categories similar to
the Integer Addition circuit, which are sensitive to BDD variable ordering (though best and worst
case complexities may differ significantly).
Function Class
Best Case
Complexity
Worst Case
Complexity
Symmetric
Linear
Quadratic
Integer Addition (any bit)
Linear
Exponential
Integer Multiplication (middle bits)
Exponential
Exponential
Table 3: Asymptotic Behavior of 3 classes of Boolean Circuits
3.5.3
Exact Ordering Algorithms
The most direct method to obtain the optimum variable order is to test all different permutations
of variable orderings in order to find the one which gives the smallest BDD. Assuming that there
are n input variables, we will have to test n! different permutations. The worst case complexity
for BDDs is illustrated by a simplistic approach of O(n!2n), but this is clearly not feasible
except for the smallest circuits.
15
A more sophisticated approach uses Dynamic Programming techniques when performing similar
searches. This method arises from the theory that given a cut across the width of the BDD, the
size of the BDD below the cut is independent of the variable order of all variables above the cut
[FS87]. Even though this technique considerably reduces the complexity of finding the optimal
BDD order, it is still too complex for any real-life applications. In fact [FS87], it has proven that
the problem of finding an optimal BDD variable order is co-NP complete. Consequently,
researchers began to turn to heuristics-based algorithms.
3.5.4
Ordering Derived from Circuit Structure
[BER89] and [MCM92] have derived theoretical upper bounds for several classes of circuits
based on the structural properties of their logic network realizations. Their work provides the
theoretical basis for subsequent efforts that have exploited circuit structures in order to find good
BDD variable orders. Some of these techniques will be discussed in the next section. [BER89]
and [MCM92] also introduced the notion of the width of a logic network realization based on
some topological ordering of the network. They have successfully expressed BDD upper bounds
according to the width of its circuit network structure. More details on their work are available in
[BER89] and [MCM92], respectively.
3.5.5
Static Heuristic Algorithms
Heuristic ordering algorithms are the first techniques that have successfully allowed researchers
to utilize BDD packages for the manipulation of large industrial circuits. Most heuristic
algorithms exploit the structural properties of the logic network implementations of digital
circuits in order to derive good BDD variable orders. The main objective of these algorithms is to
16
avoid the memory explosion phenomena. Listed below are some heuristic algorithms that have
been particularly successful:
Ordering based on the binateness of variables: When a Boolean function is expressed in the SumOf-Product (SOP) form, binateness is a measure of the frequency that a variable appears
explicitly in its positive as well as negative form in the expression. This algorithm places
the most binate variables at the top of the BDD such that the total number of terms in the
SOP expressions of its co-factors are minimized. The main heuristic of this algorithm is
that a SOP expression with fewer product terms will in turn reduce the size of the subgraph rooted at its representative vertex.
Depth-First-Search (DFS) method: [MWBS88] proposes that a simple DFS traversal of the logic
network graph be used to obtain the BDD variable order. This heuristic is particularly
effective for obtaining non-interleaved variable orders, which is described in Section
3.5.2 above. Hence this method gives optimal variable orders for fanout free such as the
arithmetic adders. For non-fanout free circuits, it approximates the non-interleaved
variable orders. This technique can be viewed as a search algorithm for a circuit topology
which minimizes the width (refer to previous section) of the circuit.
Variable Ranking: This heuristic attempts to rank variables according to their influence on the
output value(s) of the Boolean function. A weight assignment scheme is derived by
traversing the circuit graph from its output vertices to input vertices, which attempts to
characterize the degree of importance of the inputs. Variables with high weights are
placed at the top of the BDD.
3.5.6
Dynamic Variable Ordering (DVO)
17
Currently, algorithms that allow variable ordering to change dynamically during the BDD
construction and manipulation processes are the most effective variable ordering algorithms.
Dynamic Variable Ordering (DVO) [RUD93] [PS95] [PSP94] is a technique whereby a variable
is successively moved to each position in the ordering list of the BDD, before it is finally
assigned to the position that results in the smallest BDD. The process of moving a variable up (or
down) one location each time is known as sifting. Sifting has emerged as an excellent heuristic to
achieve a very good compromise between low CPU time requirements and high quality of results
[RUD93].
Windowed sifting is a refinement to the sifting algorithms whereby a small window of k
consecutive variables is created and sifting is performed only within the window. The window is
moved forward repeatedly until the whole length of the DAG has been covered. Another
optimization of the DVO algorithm speeds up the sifting process by reducing the number of sifts
required through variable grouping.
3.6
Application of BDDs
BDDs have been successfully applied to many problems in CAD. The fact that it is canonical
made it extremely useful for equivalence checking, satisfiability and tautology problems.
Equivalence testing is performed simply by checking if the two pointers for the functions under
investigation point to the same BDD vertex, whereas satisfiability and tautology problems only
require a simple check to see if the BDD representing the function is the constant zero or one
terminal vertices, respectively. Section 3.3 discusses how BDD performs all other Boolean
manipulation efficiently based on the ite operator. BDDs are widely used for problems in formal
18
verification, test generation and logic synthesis because of these desirable properties [BRY92].
Aside from CAD applications, BDDs are also used in many other application domains including
concurrent system design, problem solving in artificial intelligence, and mathematical logic
[BRY92].
3.7
Variants of BDD
Over the years, researchers have proposed many variations of BDDs for various application
domains. Some of them are discussed below :
Different decomposition technique: Instead of using Shannon's decomposition technique to derive
the respective co-factors, Ordered Functional Decision Diagram (OFDD) [KEB92]
proposes that the "Reed-Muller" expression be used instead for this purpose. OFDD is
shown to handle some functions better than ROBDD.
Breadth First Manipulation: This technique [OYY93] exploits the memory hierarchy of
workstations, storing only a few levels of the BDD in the main memory and all other
levels in secondary memory. This technique greatly increases the class of functions that
can be manipulated BDD packages [SRSB96].
Non-canonical BDD: XBDD [JPHS91] trades canonicity for structure in verification algorithms.
IBDD [JBAFA97] allows any variable to appear multiple times in any root-to-terminal
paths. Typed Free BDD [GM94] relaxes the total ordering constraint.
19
Partitioned ROBDD: [NJFS96] partitions the Boolean space and uses different DAGs to represent
each partition.
We have reviewed many aspects of BDDs that present opportunity for visualizations. In fact,
much previous work on BDDs can be easily attributed as results of simple visualizations. In the
next few sections, a brief review of relevant techniques will be presented.
20
3.8
Scientific Visualization Techniques
3.8.1
Data Flow Architecture
A data flow architecture [HAE88] [DYR90] is a data-centric model for visualization whereby the
data set is transformed in a series of logical steps before it is finally being displayed. These steps
are described by a series of computation modules as illustrated in Figure 3.
Figure 3: Data transformation steps in data-flow architecture
Filtering:
A process whereby raw data is transformed into data of “interest”. Some
examples of these computations are interpolation, smoothing, data
extractions, etc.
Mapping:
A set of modules that build geometric representations of the data.
Rendering:
The geometric representations of data are converted to an image that can
be displayed
Application developers pick from a library of modules, each categorized under one of the three
types listed above, and wires them together into a network. In this system, a module reads in data
21
in a format that it understands and presents its output to a subsequent module. Data flows through
the network, from the filter modules, through the mapping modules, to the render modules –
hence the term “data flow” architecture is derived.
3.8.2
Scalar Mapping Technique
The scalar mapping technique [HDB92] introduced by Hibbard et al performs the visualization of
a data set based on a set of user-defined mapping functions i(s). This visualization technique is
implemented in the VisAD [HAP97] system. Further discussion of this architecture is included in
Section 5.3.2.

3.9
Graph Visualization Algorithms
Graph visualization algorithms are formulated to draw graphs based on a few visual principles
[DOTALG]:

Expose hierarchical structure in graphs, expose general flow of directed graphs

Avoid edge crossings, sharp bends and other visual anomalies that do not convey information

Keep edges as short as possible

Expose symmetry, parallelism, regularity and balance to reveal patterns

Efficiently use layout area for recognition and readability of individual objects
The human eye and display have finite resolution. These physical limitations translate into the
resolution rules stated below:

integer values for vertices and bends
22

minimum distance between vertices

minimum distance between a vertex and non-incident edges

minimum angle form by consecutive edges (angular resolution)
The graph drawing algorithm implemented by DOT currently has four passes. The first pass of
the algorithm assigns an optimal topological rank to all vertices in the graph. The second pass
orders vertices within their ranks. The third pass assigns positions to vertices based on their rank
assignments. Lastly, the forth pass routes the edges.
The visual principles and resolution rules above can also serve as a general guide for good
visualizations. A well-designed graph visualization system coupled with extensive userinteraction capabilities such as zooming, panning, and event handling mechanisms can be used to
effectively display large graphs in the order of ten thousands of vertices. However, current BDD
packages commonly manipulate BDDs with millions of vertices. Therefore graph dumps are
usually not feasible1 visualizations for these industrial strength BDDs. For these situations, we
have to rely on effective abstractions in order to make sense of the data set .
3.10 Existing BDD Visualization Techniques
Currently, there is not much available in the way of BDD visualization. To our knowledge,
besides traditional text printouts for debugging purposes, the only available utilities for the
visualization of BDDs is to display the entire DAG using graph display algorithms, i.e. dumps
1
Both in terms of memory and CPU requirements.
23
the BDD DAG as it is, vertex for vertex and edge for edge. There is no work done in the area of
data set preprocessing to provide more meaningful abstraction of data.
Layout of BDD dumps are simpler compared to general graph layout. To start, we know the level
(or topological rank) of all vertices. We would only need the last three passes of the graph
drawing algorithms presented in the previous section. Most current systems attempt to layout
BDDs according to the visual principles specified in the previous section.
24
4.
Motivations and Challenges in BDD Visualization
We will argue that the whole concept of BDD can be easily derived through simple
visualizations. Specifically, the BDD reduction idea mentioned in Section 3.1.2 can be visualized
graphically using DAG drawing techniques as shown in Figure 4. From this visualization, it is
easy to see that a vertex v, with low(v) equals to high(v), makes no consequential decision in the
overall decision diagram, and it is redundant. The two sub-trees in the right side of Figure 4
graphically illustrate isomorphism and expose the opportunity to safely prune away portions of
the decision diagram that exhibit such characteristic. Without this simple visualization, these
deductions are not immediately obvious.
Figure 4: Illustrations for Redundant Vertex and Isomorphic Subgraphs
4.1
Large BDD Sizes
The sizes of BDDs in real world applications are in the order of millions of vertices whereas
physical and technological limitations discussed in previous sections depict that we can only
25
display up to a few thousands of vertices effectively on the screen of the computer. There are two
possible solutions to this inherent difficulty:
i. Perform visualizations only on small samples and deduce behavior of larger systems based
on these small visualizations.
ii. Design more advanced BDD visualization techniques, which utilize appropriate abstractions
for large data sets commonly associated with real world examples.
Solution (i) is more useful for deterministic operations such as the BDD reduction rules illustrated
in Figure 4. When invoking these rules, we know with absolute certainty that every time a
redundant vertex is removed, or an existing sub-graph is reused for its isomorphic instances, we
are another step closer to the optimal result.
On the other hand, heuristics algorithms such as BDD variable ordering algorithms do not
provide such assurance. Greedy algorithms are confined at local minimas. In these situations, it is
not obvious how behavior of large systems can be inferred from that of smaller ones.
Consequently, we need more advanced BDD visualization techniques based on effective
abstractions of initial data set.
4.2
Understanding Algorithmic Behavior
This section addresses the problems associated with the lack of understanding of BDD
algorithmic behavior, specifically BDD variable ordering algorithms. Since the optimal variableordering problem is NP-complete, all effective algorithms for problem instances of any realistic
sizes are based on heuristics. Most experimentally effective heuristics are derived from the
structure of network implementations of Boolean functions. Effective BDD visualization
26
techniques will expose structural correlation between BDDs and circuit networks, and help
algorithm developers understand these structural correlation. This understanding should guide
algorithm developers in their search for new heuristics or optimizations of current heuristics.
Effective visualizations should also reveal why certain heuristics performs well on selected
classes of circuits and poorly on others. Developers can then fine-tune or modify their algorithms
appropriately. Visualizations can also be used to help developers determine confidence levels of
the performance of their algorithms and make more accurate claims about their various heuristics.
Developers should also be able to observe intermediate results at run-time, and perform
computation steering to quickly test new hypothesis in the visualization environment. A well
designed BDD visualization system should shorten algorithm development time, ease the
development process and result in better-optimized algorithms.
4.3
Visualization for Education
One of the most effective methods for teaching BDD data structures and algorithms is by its
visualization. The field of graph visualization arises because people can generally understand
visual representations of graphs better than its mathematical models [DOTALG] [DOTAPP].
Most structural and behavioral properties of graphs cannot be directly derived from its concise
mathematical descriptions. Consequently, the DAG structure of BDD implies the effectiveness of
its visualization. Algorithm developers can utilize effective visualization techniques to present
new BDD algorithms to the community at large.
27
5.
Visualization Infrastructure
Figure 5 illustrates the architectural model of our BDD visualization system. This model is
adapted from [PAL93]. In this section, we will describe each component shown in the model
above.
Visualization
Packages
Custom
BDD
package
DIVA
Visualization
Operators
Shared Data
Space
Visualization
Operators
User
Interface
VisAD
Scalar
Mapping
Visualization
Operators
View(s)
Direct Manipulation
Figure 5: Architectural Model of BDD Visualization System
28
5.1
Visualization Operators
All components in the system are connected to the shared data space through visualization
operators. Visualization operators have two main roles (See Figure 6):
i. Extract data from the shared data space and transport data to various functional blocks of
the visualization system
ii. Modify data values or control variables in the shared data space.
Data Values
Shared Data Space
Visualization
Operator
to other components
of the system
Control
variables
Figure 6: Visualization Operator
Each visualization operator is an independent entity that can be created or destroyed without
affecting other operators. A visualization operator is only aware of its own existence and the
shared data space. It performs various operations based on the current state of the shared data
29
space, i.e. current data and control values seen by all visualization operators. This architecture is
very similar to the model/view/controller architecture [KP88]. (See Section 5.6)
There is no direct communication mechanism between any functional blocks in the system. As
shown in Figure 5, the visualization operators are the main communication objects in the
visualization system. Functional blocks communicate indirectly using control variables stored in
the shared data space. For example, a visualization operator from the User Interface may set the
nextSift control variable in the shared data space. Subsequently another visualization operator that
is monitoring the state the nextSift variable will be activated, which in turn informs the BDD
package to perform the appropriate nextSift operation.
Even though all visualization operators can modify or extract data from the shared data space,
some of them are created only for data probing purposes, as evident in Figure 5. All the
visualization tools used in such systems as VisAD, DIVA and Custom packages do not directly
modify the shared data space.
5.2
BDD Package
This component is the main data generator for the BDD visualization system. It provides the
initial raw data as well as subsequent data updates as the algorithm progresses. The visualization
operators transfer these data to the shared data space.
The SIS package [SIS92] is the main environment for this component of the system, while cudd
(Colorado University Decision Diagram) is the BDD package used in the core of the SIS package
30
for our experimentation. SIS is an interactive tool for the synthesis and optimization of digital
(combination and sequential) circuits. It provides a readily available environment to build and
optimize logic networks. We have decided to use cudd as the main BDD package because it is the
current state-of-the-art. Furthermore, there are a lot of built in functions in this package to
facilitate the extraction of potentially useful statistical data.
5.3
Visualization Packages
The main visualization packages used for this project are DIVA [DIVA] and VisAD. DIVA is
used specifically for graph visualizations whereas VisAD is used to generate most other
visualizations in our BDD visualization system. The Custom block shown in Figure 5 represents
other, more specialized visualizations that are not provided by these two packages.
5.3.1
DIVA - Dynamic Interactive Visualization Architecture
The Diva graph package provides a graph visualization environment based on the
model/view/controller data and notification model. One of the package's strength is the
fundamental separation between the model (the underlying graph) and its view (the graph
visualization), which makes it easy for applications to create multiple views of a common graph
structure. [DIVA] This fits in nicely with the general architecture of the BDD visualization
system.
31
5.3.2
VisAD - Visualization for Algorithm Development
VisAD[HDB92] is a Java class library for interactive and collaborative visualization and analysis
of numerical data. It implements the scalar mapping visualization technique first introduced in
Section 3.8.2. This architecture is particularly suited for our purpose of providing the end-users of
the system with the capabilities to easily experiment with various visualizations. The system
provides an initial set of predefined mapping functions i(s), but ultimately the strength of the
system lies in the ease at which end users are able to specify arbitrary data-display mappings
using the system’s user interface (Figure 8).
Figure 7: Visualization design in VisAD
32
The VisAD data model is designed to support virtually any numerical data by providing a rich set
of classes that allow developers to build complex data structures as hierarchical compositions of
primitive data objects. All primitive data types are scalar types, and the system only defines two
primitive data classes, Real and Text. Data objects include metadata, which are integrated into the
visualization process. Metadata allows the creation of user-defined primitives (scalar types),
either as Real types or Text types. Complex data structures are built from these (user-defined)
primitive data types using the Tuple, Set and Function classes provided by the package. These
user-defined primitives are eventually mapped to display primitives using i(s), initially
mentioned in the previous section. i(s) are defined as mappings from scalar (data) types to
display scalar types. These scalar mapping functions i(s) provide a simple user interface for
controlling how all data types are to be displayed, since the graphical depiction of any (complex)
data objects can be derived from them. A simple VisAD data design and data-display mapping
assignment process is illustrated in Figure 7.
33
Figure 8: Screen-shot for the package User Interface when selecting data-display mappings.
(Actual image will be slightly different - this is an image from VisAD's example.)
5.4
User Interface
In the design of the User Interface, we adhere to the following guidelines:

User Interface should enable rapid data exploration. An end-user should be able to access any
data easily.

There should be sufficient interface to the BDD package such that an end-user can effectively
guide the execution of various BDD algorithms as needed.

The User Interface should allow end-users to customize the visualizations. VisAD's
architecture and implementation makes it easy for developers to specify arbitrary data-display
mappings for visualizations. The User Interface should extend this capability to end-users
(see Figure 8).
34
5.5
Shared Data Space
This component provides the mechanism for storing and manipulating BDD data set. Data will be
managed differently depending on its magnitude and complexity; i.e. data of large magnitude are
not stored, whereas complex data are stored in memory as much as possible. This approach is an
effort to arrive a good trade-off between memory and CPU processing requirements.
The shared data space has no specific knowledge of the visualization operators. It contains an
arbitrary number of visualization operators; i.e. visualization operators can be added to or deleted
from the system without any consequence to the shared data. This component also contains
various control variables, which, combine with various visualization operators, form the only
communication channels between various functional blocks in Figure 5.
5.6
Model View Controller
Figure 5 is effectively the model/view/controller architecture [KP88] introduced by Smalltalk-80
version of the Smalltalk programming language. The shared data set represents the model of the
system. The model is used to manage information and notify observers whenever information
changes. It contains data and functionality that are related by a common purpose. The BDD
package implements both the view and the controller. It is a view because it listens to the model
and updates its state appropriately when it receives notification from the model. It is a controller
because it modifies (provides and updates) the value of the BDD data set in the shared data space.
35
Similarly, the user interface block is both a view and a controller. VisAD, DIVA and Custom are
views, whereas the View(s) block is both a view and a controller. Direct manipulation techniques
implemented in VisAD allow the users to use data depictions (View(s)) to modify data values,
hence the controller role is illustrated.
5.7
View(s)
Most of the data interpolation, curve smoothing or fitting, data object generation and image
rendering processes of the system is performed by the VisAD system, and will not be discussed in
this report. We need only to specify the appropriate mapping functions (s) and supply the
appropriate data to perform various visualizations.
5.7
Miscellaneous Architectural Issues
5.7.1
Java Native Interface (JNI)
BDD packages are almost always implemented in the C/C++ language as it requires extensive
memory management capabilities. Therefore the visualization system is implemented in Java and
is communicated with the BDD package via Java JNI.
36
5.7.1
Java Remote Method Invocation (RMI)
The Java RMI system allows programmers to create Java objects distributed across a network of
workstations and communicate with each other as if only local method invocations are performed.
Using this system, the components of the BDD visualization package can be distributed across
different workstations, possibly of different platforms. For example, the BDD package of the
system can be implemented as a remote object on a server, while the other components connect as
client objects for visualization purposes.
37
6.
Package Description
6.1
Interaction Matrix Viewers
A new graph G*(V*, E*) is built from the BDD G(V,E) using the abstractions listed below:

Create a vertex v*  V* for each variable of the BDD.

Weight each vertex v* such that weight(v*) = { v  V | index(v) = variable index of v*}.

Create an edge (u* , v*) for each distinct node pairs (u* , v*).

Weight each edge (u* , v*) such that weight((u* , v*)) = { (u,v)  E | index(u) = variable
index of u* and index(v) = variable index of v* }.

Remove all vertices and edges of zero weight.
The interaction matrix used in this section is the matrix representation of graph G*(V*, E*).
6.1.1
Interaction Matrix Viewer 1: Graph Visualization
This visualization attempts to discover the correlation between the connectivity structure of the
interaction matrix and the quality of its BDD during the execution of the sift algorithm. The focus
of this visualization is the degree of connectivity between variables and how it changes during the
execution of the algorithm. We have decided to use the graph visualization for this purpose. The
simple metrics developed for this visualization is shown in Table 4.
38
BDD Attributes
Visual Attributes
Variable connectivity
Edges
Density of connectivity
Thickness and shade of edges
Number of nodes representing variable xi
Width of node representing variable xi
Movement of variables during sifting
Color of nodes
Changes in node sizes after sifting
Appended node-segments and colors
Each invocation of the sift algorithm
Index into the animation sequence
Table 4: Visualization Metrics
Figure 9: Portion of s1423 as visualized
Figure 9 shows a screenshot of a portion of the visualization performed on the BDD of s1423
(ISCAS89) after the first sift. This diagram shows the variable G75 sifted from the initial position
marked by the arrow to its current position. This move is shown by the respective coloring of the
39
variable vertices; i.e. for this particular example, the red vertex represents G75, the variable that
has just been sifted and the orange vertices represent variables affected by this particular sift. To
maximize space utilization as well as minimize edge clustering, the vertices in this visualization
are laid out over two columns.
6.1.2
Interaction Matrix Viewer 2: 3D-Blocks
This visualization supplements the graph view (see Section 6.1.1) of the interaction matrix. While
the graph visualization in Section 6.1.1 focuses on the connectivity property of the BDD, the 3DBlocks view in this section focuses on the general structure of the BDD (Figure 10).
Figure 10: 3D-Block Visualization of s1423
40
This visualization has a much simpler data-display mappings as shown in Table 5.
BDD Attributes
Display Attributes
BDD Variable
Block
BDD Variable Index
Block's y-position
Number of vertices representing variable xi
Size of Block representing xi
Color of Block representing xi


Each invocation of the sift algorithm
Index into the animation sequence
Table 5: Visualization Metrics for 3D-Blocks
Figure 11: 3D-Block Visualization of s1423 at the end of sifting
This visualization reveals the structure of BDDs in the most straightforward manner possible. The
variable blocks are lined up in a single file (as opposed to two columns in Section 6.1.1) so that a
user knows exactly where the variables are with respect to each other. This visualization is most
effective in revealing size variations as well as patterns of size variations in BDD structures. It is
41
easy to observe if the algorithm eventually favors an ordering which alternate sizes of BDD
variable, or if it favors an ordering which clusters large variables together, i.e. Figure 10 shows
two distinct clusters of large variables whereas Figure 11 shows alternating variables.
In the visualization metrics presented in Table 5, the color attribute is redundant since block size
is a sufficiently effective visual representation of the number of vertices. Therefore, we can
easily modify this metrics to use colors more effective, i.e. to reveal the location of clusters of
tightly connected variables. In this package, the color attribute is currently reserved to show
correlation across visualizations of different structures. However, in single display visualizations
such as that in Figure 10 and Figure 11, color is used in a redundant manner, so that it can easily
be overwritten when performing multiple display visualizations.
6.2
Statistical Monitor
This visualization monitors and remembers among others, the utilization of physical memory
during the execution of BDD algorithms. This is particularly important because the current most
challenging problem associated with BDD packages is the memory explosion problem discussed
in Section 3.3.1. We believe that proper monitoring of memory consumption pattern during the
execution of various algorithms will help developers make more informed decisions in the
process of designing memory-intensive data structures.
42
Figure 12: 3D statistical plot of s1423
In a BDD package, the most memory intensive data structures (refer to Section 3.2) are:

Unique Table, where the current BDD vertices are stored

Computed Table, stores function pointers

Node Free List, nodes which are freed but not whose memory are not released yet.
More useful statistical data can be easily extracted from the data structures defined in the Cheader files (Appendix 10.2) of the BDD package. We may want to monitor the memory usage
pattern when BDDs are being built in order to discover when and how problematic instances
arise, or if these algorithms are using memory efficiently. We may also be interested in
monitoring performance-related statistical data, i.e. cache statistics for the Computed Table such
as total lookups, hit rate, miss rate, etc.
43
From Appendix 10.2, we can see that there are many statistical data that may be of interest to a
developer. Furthermore, a developer may want to visualize these data in a variety of ways. Hence
it is not feasible for the system to attempt to provide visualizations for every conceivable
combinations of these data. VisAD system provides a SpreadSheet class which allows end-users
to select (at runtime) arbitrary data combinations for visualizations and construct specialized
visualizations using the User Interface illustrated in Figure 8.
Additional data values that can be visualized by this display includes:

Total number of vertices

Total number of variables in the real-support of the BDD

Total number of variables at each variable-level

Effectiveness of garbage collection scheme (number of dead vertices, number of reclaimed
vertices during the execution of BDD algorithms)
6.3
BDD Dump
This visualization is actually graph visualization for the entire BDD. It displays the BDD as stated
in Section 3.8, vertex for vertex, edge for edge. Even though this visualization is not effective for
real BDD examples as discussed in Section 4.1, it is included in this package because it is the
most detailed visual depiction of BDD and can be used in the following situations:

Testing purposes - In the process of developing algorithms, developers test their design using
small data samples (typically less than 15 variables). In these instances, a complete BDD
dump is a feasible best visualization of the data structure.
44

Debugging purposes - As above, BDD dumps are extremely effective visualization for this
purpose because of the fact that small data samples are normally used for this purpose.
Furthermore, the BDD vertices can be color-coded according to other important information.

Demonstration and Education: Visualization of the actual BDD DAG at each stage of the
execution of an algorithm is the best way to relate and understand the inner mechanics of the
algorithm. As such, this is a powerful tool for educating other communities about the BDD
data structures as well as its algorithms.
Figure 13: BDD Dump Visualization
6.4
Network Visualization
6.4.1
Network Visualization 1: Dump
In SIS, a logic network is expressed as a network of vertices with multiple fanins and fanouts.
Each vertex represents a sub-function that operates on its fanin set.
This view is the graph visualization of the network realization of the logic function (see Figure
13). More specifically, it is the visualization of the internal network data structure maintained by
the SIS [SIS92] package. Taking into account the fact that most BDD heuristics are based on the
45
structure of its logic network, this visualization is particularly useful both in the process of
designing and testing of various BDD algorithms.
Network dumps are slightly more complicated than BDD dumps (Section 6.3). Firstly, the fact
that a network is not always a DAG complicates vertex placement in DOT's layout
algorithms[DOTALG]. Additionally, there are different types of vertices, namely Primary Inputs,
Primary Outputs, Internal Vertices, and Latches. We may want to use different shapes for
different types of vertices.
Figure 13: Network Dump Visualization
46
7.
Visualization Results and Discussions
This report discusses results based on experimentation of the BDD visualization package using
the sifting algorithm. The sifting algorithm is a good example for this study because it is an
inexpensive and effective way to enumerate a sizeable subset of the complete set of variable
ordering permutations. According to some local search strategy it is a greedy algorithm that
performs successive improvements based on an existing variable order.
7.1
Structural Correlation
One of the main challenges of this visualization project is to provide intuitive visual depictions of
BDD data that will reveal how the structure of BDD changes as algorithms operate on it. As the
structure of the BDD changes, we want to capture good1 instances and view these instances
against its network visualizations to discover interesting structural correlation that may be used
for the purposes of algorithm optimization.
Figure 9 shows the BDD of s1423 of the ISCAS89 benchmark circuits. This BDD is extracted
during the initial stages of the sifting algorithm, i.e. after the first variable G75 has been sifted.
Following the algorithm outlined in [RUD93] the sifting algorithm takes as inputs an existing
ordered BDD, and sifts variables in the order of their sizes in the BDD. We have listed a few
interesting observations from Figure 9. The initial static ordering algorithm that provides the
input BDD for our experimentation has created a BDD with a small knot of large variables that
are tightly connected to each other. The tight connectivity is evident from the thickness of the
47
edges between the vertices in this small cluster. Elsewhere in the BDD, variable vertices are
much smaller and variable interactions are relatively sparse.
At this point, we may want to know if this structure is typical of good BDDs produced by static
ordering algorithms, and whether the sifting algorithm will modify this structure to discover
better BDDs. Figure 14 shows the variable connectivity s1423 before and after sifting. We can
see that the sifting algorithm takes the single tight knot of variables and eventually created two
tight knots in the final BDD.
Figure 14: s1423 visualizations before and after sifting respectively
Thus far, we have only used this visualization to discover if there is any correlation between
good BDD and the general structure of its interaction matrix. Section 7.2 will introduce
1
For the sake of simplicity, good instances are BDDs extracted at the end of each variable sifting process.
48
techniques that will allow developers to view correlation between different structures, i.e. the
correlation between the structure of the interaction matrix and the structure of the logic network.
7.2
Multiple Data Views
The architecture of the visualization system allows us to have multiple views of the data at
various stages of the algorithm. As discussed in Section 6, currently supported visualizations
include interaction matrix viewers, various statistical monitors, BDD dump and Boolean network
viewers. Having multiple concurrent visualizations of a shared data set is a powerful technique to
obtain a better and more comprehensive understanding of the data structures as utilized by its
various algorithms.
Figure 15: Multiple data views of s1423
We will illustrate this concept using two simple visualizations of the sifting algorithm operating
on s1423 as shown in Figure 15. We can see that the sifting algorithm chooses G75 as the first
sifting variable, based on the heuristic that G75 being the largest variable has the greatest
potential for optimization. However, as we can further see from Figure 15, this sift is not as
effective as originally predicted since there is only a marginal decrease in the size of the BDD at
the end of this sift. In fact the most significant size reduction occurs when variable G90 was sifted
(see Figure 15). This fact is not consistent with the original variable selection heuristics since G90
49
is initially a small variable (see Figure 9). This insight is obtained when two different
visualizations are viewed simultaneously, i.e. the graph visualization of the interaction matrix and
the plot of BDD size vs. sifting variable.
At this point we should be able to devise other tests to discover if the overall procedure would be
more effective if G90 is the first variable to be sifted, or if this significant size reduction can be
indirectly attributed to the less-effective sifts in the earlier stages of the algorithm. We should also
be able to use other visualizations to arrive at heuristics to discover good sifting variables such as
G90 based on initially available information, i.e. the structure of the circuit network.
In order to discover any interesting structural correlation between the interaction matrices of good
BDDs and logic network using different data views provided by the package, we can utilize
colors in these visualizations. The variable nodes in the network graphs can be colored such that
it corresponds to the coloring scheme applied to the BDD visualizations. This simple color
visualization should expose structural correlation; i.e. we should identify portions of the network
structure that are mapped to respective portions of the BDD structure.
More figures !!
7.3
Algorithm Animation
Real-time algorithm animation is one of the most effective visualization techniques to help
developers understand complex algorithmic behavior. Developers are able to observe selected
data structures changing in response to different operations performed by their algorithms. Using
these animation techniques, algorithm developers will be able to tell if a blow-up occurrence is a
50
gradual process or (as its name implies) a sudden process triggered by the execution of specific
operations. Visualization will also allow developers to isolate problematic operations in their
algorithms that may require further optimizations.
With real-time animation, developers can stop the execution of an algorithm when visualizations
reveal interesting behaviors that call for further investigations. The current state of the system can
be examined more closely in an attempt to provide explanations for these behaviors. To extend
the idea, Section 7.4 discusses the concept of total system integration in the visualization system
that provides an environment that allows developers to perform real-time algorithmic
modifications.
7.4
System Integration Architecture
The visualization process outlined in Figure XXX illustrates the total system integration
architecture of this package. For the visualization system to be useful in the design and
optimization process of algorithms, developers should be able to easily modify the execution path
of various algorithms. End users of the visualization system should be able to use the User
Interface of the system to quickly control both the visualization environment as well as the BDD
manipulation environment.
Computational steering [PJB97] allows developers to steer their algorithm in real-time. It allows
developers to change algorithm and visualization parameters and observe the effects of these
changes immediately. Developers can then use the visualization environment to drive the
scientific discovery process, and interact with their data. Currently, computational steering is
51
performed through the display direct manipulation capabilities provided by the VisAD
visualization system as well as the user interface provided by the package.
52
8.
Conclusions and Future Work
The BDD visualization package has been demonstrated to be useful in the design, construction
and optimization process of BDD algorithms. The system includes visualization capabilities for
BDD data structures as well as other important data values. One central issue in the design of this
system is to provide developers the option of viewing data at different levels of abstractions. This
is important to ensure that developers can easily detect existing patterns or symmetries in the
visual depictions provided by the system. In designing this system, we have taken into account
some important rules of scientific visualizations such as those listed in Section 3.9.
A scientific visualization system has to be extensible in order for it to be useful. It is impossible
for the designer of such visualization systems to anticipate all possible data visualizations which
algorithm developers may desire, and the feedback and redesign process between visualization
system developers and algorithm developers are often too slow to be of any use. In this respect,
we have decided to utilize the Scalar Mapping Technique implemented by the VisAD
visualization system, and develop simple user-interfaces to allow algorithm developers to build
their own data-display mappings.
We have demonstrated the visualization system as applied to the BDD sifting algorithm. This
algorithm is a good candidate for this demonstration purpose because it explores a sizeable subset
of the complete problem space. These good BDD instances discovered by the sifting algorithm
can be used in the visualization process to discover correlation between good BDD variable
orders and the structural properties of various data such as the BDD interaction matrix or the
network realization of the digital circuit.
53
We have also demonstrated some important visualization concepts using this system. Multiple
concurrent visualizations of a shared data space are very useful in helping developers gain a more
concrete understanding of their algorithms. Figure XXX demonstrated an important design
sequence that the package provides with its total system integration architecture. With this
architecture, we have integrated BDD package control mechanisms into the system so that
developers can use the visualization environment to perform computational steering of the
algorithm.
54
9.
References
[BER89]
Ordered Binary Decision Diagrams and Circuit Structure Extended Abstract
C. Leonard Berman
IEEE Conference on Computer Design, Oct 1999
[BOU96]
An Ordering Heuristic for Building Binary Decision Diagrams from Fault-Trees
M. Bouissou
Annual Reliability and Maintainability Symposium, January 1996
[BRB90]
Efficient Implementation of a BDD Package
K.S. Brace, R.L. Rudell, R.E. Byrant
IEEE Design Automation Conference 1990
[BRY86]
Graph-Based Algorithms for Boolean Function Manipulation
R.E. Bryant
IEEE Transactions on Computers, August 1986
[BRY91]
On the complexity of VLSI implementations and graph representations of
Boolean functions with application to integer multiplication
R.E. Bryant
IEEE Transactions on Computers, Feb 1991
[BRY92]
Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams
R.E. Bryant
ACM Computing Surveys, Vol 24. September 1992
[FFK85]
Evaluation and Improvements of Boolean Comparison Method Based on Binary
Decision Diagram
M. Fujita, H. Fujisawa, N. Kawato
ICCAD November 1988
55
[FFM93]
Variable Ordering Algorithms for Ordered Binary Decision Diagrams and Their
Evaluation.
M. Fujita, H. Fujisawa, Y. Matsunaga
ICCAD January 1993
[FS87]
Finding the Optimal Variable Ordering for Binary Decision Diagrams
S.J. Friedman, K.J. Supowit
Design Automation Conference, June 1987
[GKB97]
Canonical TBDD's and Their Application to Combinational Verification
E.I. Goldberg, Y. Kukimoto, R.K. Brayton
[KP88]
A Cookbook for Using the Model View Controller User Interface Design
Paradigm in Smalltalk-80.
G.E. Krasner, S.T. Pope
Journal of Object Oriented Programming, 1988
[MCM92]
Symbolic Model Checking: An Approach to the State Explosion Problem.
K.L. McMillan
Ph.D Thesis, School of Computer Science, Carnegie-Mellon University
[MWBS88]
Logic Verification using Binary Decision Diagrams in a Logic Synthesis
Environment
S. Malik, A.R. Wang, R.K. Brayton, A. Sangiovanni-Vincentelli
ICCAD November 1988
[NAR98]
BDD Partitioning for Formal Verification and Synthesis of Digital Systems
Amit Narayan
Ph.D Thesis, Department of Electrical Engineering and Computer Sciences,
University of California at Berkeley 1998
[NJFSSurvey] A Survey of Techniques for Formal Verification of Combinational Circuits
J. Jain, A. Narayan, M. Fujita, A. Sangiovanni-Vincentelli
56
[OYY93]
Breadth First Manipulation of Very Large Binary-Decision Diagrams
H. Ochi, K. Yasouka, S. Yajima
ICCAD 1993
[PS95]
Who are the Variables in your Neighborhood
S. Panda, F. Somenzi
ICCAD November 1995
[PJB97]
Computational steering. Software systems and strategies.
S.G. Parker, C.R. Johnson, D. Beazley.
IEEE Computational Science and Engineering, December 1997
[PSP94]
Symmetry Detection and Dynamic Variable Ordering of Binary Decision
Diagrams
S. Panda, F. Somenzi, B.F. Plessier
ICCAD November 1994
[RUD93]
Dynamic Variable Ordering for Ordered Binary Decision Diagrams
R. Rudell
ICCAD November 1993
[SRSB96]
High Performance BDD Package by Exploiting Memory Hierarchy
J.V. Sanghavi, R.K. Ranjan, A. Sangiovanni-Vincentelli, R.K. Brayton
[YK97]
Variable Ordering for Ordered Binary Decision Diagrams by a Divide-AndConquer Approach
F.M. Yeh, S.M. Kuo
Computers and Digital Techniques, September 1997
[KEB92]
Multilevel Logic Synthesis based on Functional Decision Diagrams
U. Kebschull
European DAC 1992
57
[JPHS91]
Structural BDDs: Trading Canonicity for Structure in Verification Algorithms.
S.W. Jeong, B. Plessier, G. Hachtel, F. Somenzi
ICCAD 1991
[JBAFA97]
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify
Boolean Functions
J. Jain, J. Bitner, M. Abadir, D.S. Fussell, J.A. Abraham
Computers, November 1997
[GM94]
Efficient Boolean Manipulation With OBDD's can be extended to FBDD's
J. Gergov, C. Meinel
Computers 1994
[NJFS96]
Partitioned ROBDDs - A Compact, Canonical and Efficiently Manipulable
Representation for Boolean Functions
A. Narayan, J. Jain, M. Fujita, A. Sangiovanni-Vincentelli
ICCAD 1996
[HDB92]
Display of Scientific Data Structures for Algorithm Visualization
W. Hibbard, C.R. Dyer, B. Paul
Visualization 1992.
[HAP97]
A Java and World Wide Web Implementation of VisAD
W. Hibbard, J. Anderson, B.Paul
[HAE88]
ConMan: A Visual Programming Language for Interactive Graphics
P. Haeberli
Computer Graphics 22(4) pp 103 – 111, 1988
[DYR90]
A Dataflow Toolkit for Visualization
D.S. Dyer
Computer Graphics and Applications
[EW93]
Animation and Scientific Visualization, Tools and Applications
58
R.A. Earnshaw, D. Watson
Academic Press, 1993.
[PAL93]
Scientific Visualization, Advanced Software Techniques
P. Palamidese
Ellis Horwood Workshop Series, 1993.
[SIS92]
SIS - A System for Sequential Circuit Synthesis
Electronics Research Laboratory
ERL Memorandum No. UCB/ERL, M92/41
[FOH93]
Interleaving Based Variable Ordering Methods for Ordered Binary Decision
Disgrams
H. Fujii, G. Ootomo, C. Hori
ULSI Research Laboratories, R&D Center.
Toshiba Corporation.
[BETT94]
Algorithms for Drawing Graphs: an Annotated Bibliography
G.D. Battista, P. Eades, R. Tamassia, I.G. Tollis
June 1994 (ftp://wilma.cs.brown.edu/pub/papers/compgeo/gdbiblio.ps.gz)
[DOTALG]
A Technique for Drawing Directed Graphs
E.R. Gansner, E. Koutsofios, S.C. North, K.P. Vo
AT&T Bell Laboratories, New Jersey
[DOTAPP]
Applications of Graph Visualization
S.C. North, E. Koutsofios
AT&T Bell Laboratories, New Jersey
[PWL96]
Approaches to Uncertainty Visualization
A.T. Pang, C.M. Wittenbrink, S.K. Lodha
Visual Computer 1997
[BE96]
Software Visualization in the Large
59
T. Ball, S.G. Eick
Computer April 1996
[CLR90]
An Introduction to Algorithms
T.H. Cormen, C.E. Leiserson, R.L. Rivest
McGraw-Hill New York, 1990
60
10. Appendices
10.1 Pseudo-code for ite algorithm
ite(F,G,H){
if(terminal case){
return results;
} else if(computed-table has entry (F,G,H)){
return results;
} else{
let v = top variable of {F,G,H};
T = ite(Fv,Gv,Hv);
E = ite(Fv',Gv',Hv');
if (T equals E){
return T;
}
R = find_or_add_unique_table(v,T,E);
insert_computed_table((F,G,H), R);
return R;
}
}
61
10.2 Statistical Data of BDD Package
Listing of statistical Data Structures.
/*
* Statistics and Other Queries
*/
typedef struct bdd_cache_stats {
unsigned int hits;
unsigned int misses;
unsigned int collisions;
unsigned int inserts;
} bdd_cache_stats;
typedef struct bdd_stats {
struct {
bdd_cache_stats hashtable;
bdd_cache_stats itetable;
bdd_cache_stats consttable;
bdd_cache_stats adhoc;
} cache;
struct {
unsigned int calls;
struct {
unsigned int trivial;
unsigned int cached;
unsigned int full;
} returns;
} ITE_ops,
ITE_constant_ops,
adhoc_ops;
struct {
unsigned int total;
} blocks;
struct {
unsigned int used;
unsigned int unused;
unsigned int total;
unsigned int peak;
} nodes;
struct {
unsigned int used;
unsigned int unused;
unsigned int total;
unsigned int blocks;
} extptrs;
struct {
unsigned int times;
/* the unique table; collisions and
inserts fields not used */
/* various cache statistics */
/* bdd_nodeBlock count */
/* bdd_node count */
/* bdd_t count */
/* the number of times the
garbage-collector has run */
unsigned int nodes_collected; /* cumulative number of nodes
collected over life of manager */
long runtime;
/* cumulative CPU time spent
garbage collecting */
} gc;
struct {
int first_sbrk;
/* value of sbrk at start of manager;
used to analyze memory usage */
int last_sbrk;
/* value of last sbrk (see "man sbrk")
fetched; used to analyze memory usage */
unsigned int manager;
unsigned int nodes;
unsigned int hashtable;
unsigned int ext_ptrs;
unsigned int ITE_cache;
unsigned int ITE_const_cache;
unsigned int adhoc_cache;
unsigned int total;
62
} memory;
} bdd_stats;
struct DdManager {
/* Constants */
DdNode *one;
DdNode *zero;
DdNode *plusinfinity;
DdNode *minusinfinity;
DdNode *background;
/* memory usage */
/* specialized DD symbol table */
/*
/*
/*
/*
/*
/* Computed Table */
DdCache *cache;
/*
unsigned int cacheSlots; /*
int cacheShift;
/*
double cacheMisses;
/*
double cacheHits;
/*
double minHit;
/*
unsigned int maxCache;
/*
unsigned int minCache;
/*
unsigned int maxCacheHard;/*
/* Unique Table */
int size;
int sizeZ;
int maxSize;
int maxSizeZ;
DdSubtable *subtables;
DdSubtable *subtableZ;
DdSubtable constants;
unsigned int slots;
unsigned int keys;
unsigned int keysZ;
unsigned int dead;
unsigned int deadZ;
unsigned int minDead;
unsigned int gcPercent;
int gcEnabled;
unsigned int looseUpTo;
constant 1 */
constant 0 */
plus infinity */
minus infinity */
background value */
the cache-based computed table */
total number of cache entries */
shift value for cache hash function */
number of cache misses (since resizing) */
number of cache hits (since resizing) */
hit percentage above which to resize */
size above which no resizing occurs */
minimum size for the cache */
max value for maxCache */
double reclaimed;
int isolated;
int *perm;
int *permZ;
int *invperm;
int *invpermZ;
DdNode **vars;
DdNode **univ;
int linearSize;
long *interact;
long *linear;
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/* Free List */
DdNode **memoryList;
DdNode *nextFree;
/* memory manager for symbol table */
/* list of free nodes */
/* General Parameters */
CUDD_VALUE_TYPE epsilon;
/* tolerance on comparisons */
DdNode **stack;
double allocated;
number of unique subtables */
for ZDD */
max number of subtables before resizing */
for ZDD */
array of unique subtables */
for ZDD */
unique subtable for the constants */
total number of hash buckets */
total number of BDD and ADD nodes */
total number of ZDD nodes */
total number of dead BDD and ADD nodes */
total number of dead ZDD nodes */
do not GC if fewer than these dead */
gc when this percent are dead */
gc is enabled */
slow growth beyond this limit */
(measured w.r.t. slots, not keys) */
stack for iterative procedures */
number of nodes allocated */
(not during reordering) */
number of nodes brought back from the dead */
isolated projection functions */
current variable perm. (index to level) */
for ZDD */
current inv. var. perm. (level to index) */
for ZDD */
projection functions */
ZDD 1 for each variable */
number of rows and columns of linear */
interacting variable matrix */
linear transform matrix */
/* Dynamic Reordering Parameters */
int reordered;
/* flag set at the end of reordering */
int reorderings;
/* number of calls to Cudd_ReduceHeap */
int siftMaxVar;
/* maximum number of vars sifted */
int siftMaxSwap;
/* maximum number of swaps per sifting */
double maxGrowth;
/* maximum growth during reordering */
int autoDyn;
/* automatic dynamic reordering flag (BDD) */
int autoDynZ;
/* automatic dynamic reordering flag (ZDD) */
Cudd_ReorderingType autoMethod; /* default reordering method */
Cudd_ReorderingType autoMethodZ; /* default reordering method (ZDD) */
63
int realign;
/* realign ZDD order after BDD reordering */
int realignZ;
/* realign BDD order after ZDD reordering */
unsigned int nextDyn;
/* reorder if this size is reached */
unsigned int countDead;
/* if 0, count deads to trigger reordering */
MtrNode *tree;
/* Variable group tree (BDD) */
MtrNode *treeZ;
/* Variable group tree (ZDD) */
Cudd_AggregationType groupcheck; /* Used during group sifting */
int recomb;
/* Used during group sifting */
int symmviolation;
/* Used during group sifting */
int arcviolation;
/* Used during group sifting */
int populationSize;
/* population size for GA */
int numberXovers;
/* number of crossovers for GA */
DdLocalCache *localCaches;/* local caches currently in existence */
/* Statistical counters. */
long memused;
int garbageCollections;
long GCTime;
long reordTime;
double totCachehits;
double totCacheMisses;
double cachecollisions;
double cacheinserts;
double cachedeletions;
#ifdef DD_STATS
double nodesFreed;
double nodesDropped;
#endif
#ifdef DD_UNIQUE_PROFILE
double uniqueLookUps;
double uniqueLinks;
#endif
};
/*
/*
/*
/*
/*
/*
/*
/*
/*
total memory allocated for the manager */
number of garbage collections */
total time spent in garbage collection */
total time spent in reordering */
total number of cache hits */
total number of cache misses */
number of cache collisions */
number of cache insertions */
number of deletions during garbage coll. */
/* number of nodes returned to the free list */
/* number of nodes killed by dereferencing */
/* number of unique table lookups */
/* total distance traveled in coll. chains */
64