UNIT I
Introduction to Number Systems & Boolean Function
Introduction
Number system is a basis for counting various items. On hearing the
word ‘ number’ , all of us immediately think of the familiar decimal number
system with its 10 digits : 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
Modern computers communicate and operate with binary numbers which
use only the digits 0 and 1. Let us consider decimal number 18. This number is
represented in binary as 10010. In the example, if decimal number is considered,
we require only two digits to represent the number, whereas if binary number is
considered we require five digits. Therefore we can say that, when decimal
quantities are represented in the binary form, they take more digits. For large
decimal numbers people have to deal with very large binary strings and therefore,
they do not like working with binary numbers. This fact gave rise to three new
number systems : Octal, Hexadecimal and Binary Coded Decimal (BCD). These
number systems represent binary number in a compressed form. Therefore, these
number systems are now widely used to compress long strings of binary numbers.
In this chapter, we discuss binary, octal, hexadecimal, and BCD number
systems, and we will see how to convert from decimal to binary, octal and
hexadecimal, and vice versa. In the later section of this chap Ler we are going to
see binary, hexadecimal, Excess-3 and BCD arithmetic.
Decimal Number System
Before considering any number system, let us consider familiar decimal
number system. In decimal number system we can express any decimal number in
1
units, tens, hundreds, thousands and so on. When we write a decimal number say,
5678.9, we know it can be represented as
5000 + 600 + 70 + 8 + 0.9 = 5678.9
The decimal number 5678.9 can also be written as 5678.9 where the 10 subscript
indicates the radix or base.
In power of 10, we can write as
This says that, the position of a digit with reference to the decimal point
determines its value/weight. The sum of all the digits multiplied by their weights
gives the total number being represented. The leftmost digit, which has the
greatest weight is called the most significant digit and the rightmost digit, which
has the least weight, is called the least significant digit. Fig. 1.1 shows decimal
digit and its weights expressed as power of 10.
2
Binary Number System
We know that decimal system with its ten digits is a base-ten system.
Similarly binary system with its two digits is a base-two system. The two binary
digits (bits) a I and 0. Like digital system, in binary system each binary digit
commonly known bit, has its own value or weight. However in binary system
weight is expressed as power of 2, as shown in Fig. 1.2.
Octal Number System
We know that the base of the decimal number system is 10 because it uses the
digits 0 to 9, and the base of binary number system is 2 because it uses digits 0
and 1.
The octal number system uses first eight digits of decimal number system: 0,
1, 2, 3, 4, 5, 6, and 7. As it uses 8 digits, its base is 8.
Ex. 1.3: Represent octal number 567 in power of 8 and find its decimal equivalent.
Sol.: The given octal number 567 can be represented in power of 8 as
Hexadecimal Number System
3
The hexadecimal number system has a base of 16 having 16 digits : 0, 1, 2,
3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F. It is another number system that is
particularly useful for human communications with a computer. Although it is
somewhat more difficult to interpret than the octal number system, it has become
the most popular. Since its base is a power of 2 (2 it is easy to convert
hexadecimal numbers to binary and vice versa.
Table 1.1 shows the relationship between decimal, binary and hexadecimal.
Note that each hexadecimal digit represents a group of four binary digits, called
nibbles that are fundamental parts of larger binary words.
4
Counting in Radix (Base) r
In previous sections we have seen number systems with radix (base) r
equal to 10, 2, 8 and 16. Each number system has r set of characters.
Forexample, in decimal number system r equals to 10 has 10 characters from 0
to 9, in binary number system r equals to 2 has 2 characters 0 and I and soon. In
general we can say that, a number represented in radix r, has r characters in its
set and r can be any value. This is illustrated in Table.1.2.
5
Number Base Conversions
The human beings use decimal number system while computer uses binary
number system. Therefore, it is necessary to convert decimal number into its
equivalent binary while feeding number into the computer and to convert binary
number into its decimal equivalent while displaying result of operation to the
human beings. However, dealing with a large quantity of binary numbers of many
bits is inconvenient for human beings. Therefore, octal and hexadecimal numbers
are used as a shorthand means of expressing large binary numbers. But it is
necessary to keep in mind that the digital circuits and systems work strictly in
binary; we are using octal and hexadecimal only as a convenience for the
operators of the system.
Before going to see conversions between binary, octal and hexadecimal
numbers we see the number of digits in several number systems. Table 1.3 shows
the decimal, binary, octal and hexadecimal numbers.
6
Binary to Octal Conversion
We know that base for octal numbers is 8 and the base for binary numbers is
2. T base for octal number is the third power of the base for binary numbers.
Therefore, grouping 3 digits of binary numbers and then converting each group
digit to its octal equivalent we can convert binary number to its octal equivalent.
Octal to Binary Conversion
Conversion from octal to binary is a reversal of the process explained in
the previous section. Each digit of the octal number is individually converted to
its binary equivalent to get octal to binary conversion of the number.
7
Binary to Hexadecimal Conversion
We know that base for hexadecimal numbers is 16 and the base for binary
numbers is 2. The base for hexadecimal number is the fourth power of the base
for binary numbers. Therefore, by grouping 4 digits of binary numbers and then
converting each group digit to its hexadecimal equivalent
we can convert binary number to its hexadecimal equivalent.
Hexadecimal to Binary Conversion
Conversion from hexadecimal to binary is a reversal of the process
explained in the previous section. Each digit of the hexadecimal number is
individually converted to its binary equivalent to get hexadecimal to binary
conversion of the number.
Octal to Hexadecimal Conversion
The easiest way to convert octal number to hexadecimal number is given
below
1. Convert octal number to its binary equivalent.
2. Convert binary number to its hexadecimal equivalent.
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Hexadecimal to Octal Conversion
The easiest way to convert hexadecimal number to octal number is given
below.
1. Convert hexadecimal number to its binary equivalent.
2. Convert binary number to its octal equivalent.
9
Complements
In digital computers, to simplify the subtraction operation and for logical
manipulation complements are used. There are two types of complements for each radix
system: The radix complement and diminished radix complement. The first is referred to
as the r’ s complement and the second as the (r —i)’ s complement. For example, in
binary system we substitute base value 2 in place of r to refer complements as 2s
complement and is complement. In decimal number system, we substitute base value 10
in place of r to refer complements as 10’ s complement and 9’ s complement.
1‘ s Complement Representation
The l complement of a binary number is the number that results when we change all ls
to zeros and the zeros to ones.
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l’ s Complement Subtraction
Subtraction of binary numbers can be accomplished by the direct method
by using the l’ s complement method, which allows to perform
subtraction using only addition. For subtraction of two numbers we have two cases.
• Subtraction of smaller number from larger number and
• Subtraction of larger number from smaller number.
The 1’ s complement subtraction method for these two cases is as follows.
Subtraction of Smaller Number from Larger Number Method:
1. Determine the l complement of the smaller number.
2. Add the l’ s complement to the larger number.
3. Remove the. Carry and add it to the result.
This is called end-around carry.
Subtraction of Larger Number from Smaller Number
Method:
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1. Determine the 1’ s complement of the larger number.
2. Add the l complement to the smaller number.
3. Answer is in l’ s complement from. To get the answer in true form take the l’ s
complement and assign negative sign to the answer.
Advantages of l’ s Complement Subtraction
1. The l’ s complement subtraction can be accomplished with an binary adder.
Therefore, this method is useful in arithmetic logic circuits.
2. The l’ s complement of a number is easily obtained by inverting each bit in the
number.
2’ s Complement Subtraction
Like l’ s complement subtraction, in 2s complement subtraction, the subtraction is
accomplished by only addition. Let us see the methods for 2’ s complement subtraction.
Subtraction of Smaller Number from Larger Number Method:
1. Determine the 2’ s complement of a smaller number.
2. Add the 2’ s complement to the larger number.
3. Discard the carry.
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Signed Binary. Numbers
In practice, we use plus sign to represent positive number and minus sign to
represent negative number. However, because of hardware limitations, in computers,
both positive and negative numbers are represented with only binary digits. The left most
bit (sign bit) in the number represents sign of the number. The sign bit is 0 for positive
numbers and it is 1 for negative numbers. These numbers are represented by the signed
magnitude format. Fig. 1.3 shows the sign magnitude format for 8 bit signed number.
Here, the most significant bit (MSB) represents sign of the number. If MSB is 1,
number is negative and if MSB is 0, number is positive. The remaining bits represent
magnitude of the number. Here are some examples of sign-magnitude numbers.
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In case of unsigned 8-bit binary numbers the decimal range is 0 to 255. For
signed magnitude 8-bit binary numbers the largest magnitude is reduced from 255 to
127 because we need to represent both positive and negative numbers.
Maximum positive number 0111 1111 = +127
Maximum negative number 1111 1111 = —128
We have seen positive and negative number representation in the signed magnitude
format. This is the only way to represent positive numbers; however there are two
more ways represent negative numbers: signed complement representation and signed2’ s complement representation. Let us see how 6 are represented in these three
formats. Consider the number 6 represented in binary with eight bits.
Signed-magnitude representation 10000110 Signed-I’ s
complement representation 11111001 Signed
complement representation 11111010
In signed-magnitude, 6 are obtained from 6 by changing the sign hit in the left most
position from 0 to 1. In signed-I’ s complement, 6 is obtained by complementing all
the bits of +6, including the sign bit. The signed-2’ s complement representation of 6
is obtained by taking 2’ s complement of positive number, including the sign bit.
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Table 1.4
The Table 1.4 lists all possible 4-bit signed binary numbers in the three
representations. Looking at the Table 1.4 we understand following points
• Positive numbers in all three representations are identical and have 0 in the leftmost
position.
• All negative numbers have a 1 in the left most bit position.
• The signed-2’ s complement system has only one representation for 0, which is
always positive.
• The signed-magnitude and is complement systems have either a positive 0 or a
negative 0.
• With four bits, we can represent 16 binary numbers.
The sign-magnitude representation requires separate handling for sign and magnitude
during arithmetic operations and hence it is suitable in computer arithmetic. Therefore,
the signed complement numbers are normally used in computer arithmetic. The is
complement imposes some difficulties and is seldom used for arithmetic operations. It is
used as a logical operation since the change of is to 0 or 0 to 1 is equivalent to a logical
complement operation.
The signed-2’ s complement system is commonly used in computer
arithmetic.
Binary Arithmetic
Computer circuits do not process decimal numbers; they process binary numbers. In this
section, we are going to learn binary arithmetic. Binary addition is the key to binary
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subtraction, multiplication, and division. So, let us see rules for binary addition.
Rules for Binary Addition
17
The signed-magnitude system follows the rules of ordinary arithmetic. If the signs
are same, we add the two magnitudes and give the sum the common sign. If the signs are
different, we subtract the smaller magnitude from the larger and give the result the sign
of the larger magnitude. For example, (+24) + ( —32) = —(32 — 24) = —8 . This
process requires the comparison of the signs and the magnitudes and then performing
either addition or subtraction. In contrast, the rules for adding numbers in the signedcomplement system does not require a comparison or subtraction, but only addition let us
see the 2’ s complement arithmetic for signed numbers represented with 8-bits for all
possible cases
18
Therefore, we can change subtraction operation to an addition operation by
changing the sign of the subtrahend.It is important to note that binary numbers in the
signed complement system are added and subtracted by the same basic addition and
subtraction rules as unsigned numbers. Therefore, computer can perform both types of
arithmetic (signed and unsigned) using only one common hardware circuit.
The user or programmer has to interpret the result of such addition or sub tractor
differently, depending on whether it is assumed that the numbers are signed or
unsigned.
Binary Code
Usually, the digital data is represented, stored and transmitted as groups of
binary digits (bits). The group of bits, also known as binary code, represents both
numbers and letters of the alphabets as well as many special characters and control
functions. The’ are classified as numeric or alphanumeric. Numeric codes are used to
represent numbers. On the other hand, alphanumeric codes are used to represent
characters alphabetic letters and numerals. In these codes, a numeral is treated simply as
another symbol rather than as a number or numeric value.
Classification of Binary Codes
The different binary codes can be classified as
1. Weighted codes
2. Non-weighted codes
3. Reflective codes
4. Sequential codes
5. Alphanumeric codes
6. Error Detecting and Correcting codes
Weighted Codes
In weighted codes, each digit position of the number represents a specific weight
For example, in decimal code, if number is 567 then weight of 5 is 100, weight of 6 i
10 and weight of 7 is 1. In weighted binary codes each digit has a weight 8, 4, 2 or 1.
The codes 8421, 2421 and 5211 are all weighted codes Non-weighted Codes Nonweighted codes are not assigned with any weight to each digit position, i.e. each digit
position within the number is not assigned fixed value.
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Excess-3 and gray codes are the non-weighted codes.
Reflective Codes
A code is said to be reflective when the code for 9 is the complement for the cods
for 0, 8 for 1, 7 for 2, 6 for 3, and 5 for 4. Note that the 2421, 5211 and excess-3 code5
are reflective, whereas the 8421 code is not (Refer tables 1.5, 1.7 and 1.8). Reflectivity h
desirable in a code when the nine’ s complement must be found, such as in nine
complement subtraction.
Sequential Codes
In sequential codes each succeeding code is one binary number greater than it
preceding code. This greatly aids mathematical manipulation of data. The 8421 and
excess-3 are sequential, whereas the 2421 and 5211 codes are not.
Alphanumeric Codes
The codes which consist of both numbers and alphabetic characters are called
alphanumeric codes. Most of these codes, however, also represent symbols and various
instructions necessary for conveying intelligible information. The most commonly used
alphanumeric codes are: ASCII (American Standard Code for Information Interchange),
EBCDIC (Extended Binary Coded Decimal Interchange Code) and Hollered code.
Error Detecting and Correcting Codes
When the digital information in the binary form is transmitted from one circuit or
system to another circuit or system an error may occur. This means a signal
corresponding to 0 may change to 1 or vice-versa due to presence of noise. To maintain
the data integrity between transmitter and receiver, extra bit or more than one bit are
added in the data. These extra bits allow the detection and some times correction of error
in the data. The data along with the extra bit/bits forms the code. Codes which allow only
error detection are called error detecting codes and codes which allow error detection and
correction are called error detecting and correcting codes.
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BCD (8-4-2-1)
BCD is an abbreviation for binary-coded-decimal. BCD is a numeric code in
which each digit of a decimal number is represented by a separate group of bits. The
most common BCD code is 8-4-2-1 BCD, in which each decimal digit is represented by a
4-bit binary number. It is called 8-4-2-1 BCD because the weights associated with 4 bits
are 8-4-2-1 from left to right. This means that, bit 3 has weight 8, bit 2 has weight 4, bit 1
has weight 2 and bit 0 has weight 1.
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As seen from the above example, in multidigit coding of 8-4-2-1 BCD
numbers we require 4-bits per decimal digit. Therefore, total 8-bits are required to
encode 58 in 8-4-2-1 BCD. When we represent the same number (58) in binary:
1110102, we require only 6 digits. This means that, for representing numbers, 8-4-21 BCD is less efficient than pure binary number system. The advantage of a BCD
code is that it is easy to convert between it and decimal. The principle disadvantage
of a BCD, besides its low efficiency, is that arithmetic operations are more complex
than they are in pure binary. Let us see the arithmetic operations using 8-4-2-1 BCD.
BCD Addition
The addition of two BCD numbers can be best understood by considering the
three cases that occur when two BCD digits are added.
Sum equals 9 or less with carry 0
Let us consider additions of 3 and 6 in BCD.
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BCD Subtraction
Addition of signed BCD numbers can be performed by using 9’ s or 10’ s
complement methods. A negative BCD number can be expressed by taking the 9’ s or
10’ s complement. Let us see 9’ s and 10’ s complement numbers and subtraction
process using it.
The 9’ s complement of a decimal number is found by subtracting each digit in
the number from 9. The 9’ s complement of each of the decimal digits is as follows
24
In 9’ s complement subtraction when 9’ s complement of smaller number is added t
the larger number, carry is generated. It is necessary to add this carry to the result (this is
called an end-around carry). When larger number is subtracted from small one, there is no
carry, and the result is in 9’ s complement form and negative. This i illustrated in
following examples
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10’ s Complement
The 10’ s complement of a decimal number is equal to the 9’ s complement
plus 1. The 10’ s complement can be used to perform subtraction by adding the minuend
to the
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BOOLEAN ALGEBRA AND LOGIC GATES
AND gate
A gate is simply an electronic circuit which operates a one or more signals to
produce an output signal. The output is high only for certain combination of input
signals.An AND gate (Figure 1.1) has a high output only when all inputs are high.
The output is low when any one input is low.
Figure 1.1 AND gate
Boolean expression for AND gate operation is
Y=A . B
Truth table
A
0
0
1
1
B
0
1
0
1
Y=A.B
0
0
0
1
OR gate
An OR gate (Figure 1.2) produces a high output when any or the entire inputs
are high. The output is low only when all the inputs are low.
Figure 1.2 OR gate
The Boolean expression for an OR gate is
Y=A+B
Truth table:
A
B
Y=A+B
0
0
0
0
1
1
1
0
1
1
1
1
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NOT gate:
A NOT gate (Figure 1.3) is also called an inverter. The circuit has one input
and one output. The output is the complement of the input. If the input signal is high,
the output is low and vice versa.
Figure 1.3 NOT gate
The Boolean expression for NOT gate is
Y=Ā
Truth table:
A
0
1
Y=Ā
1
0
If two NOT gates are cascaded then the output will be same as the input
and the circuit is called buffer circuit.
1.3.4 NAND gate
A NAND (Figure 1.4) gate has two or more input signals but only one output
signal. All input signals must be high to get a low output. When one AND gate is
combined with a NOT gate, a NAND gate is obtained.
Truth table:
A
B
0
0
1
1
0
1
0
1
____
Y= A.B
1
1
1
0
Figure 1.4 NAND gate
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NOR gate:
NOR gate (Fig. 1.5) has two or more input signals and one output signal. It
consists of one OR gate followed by an inverter. A NOR gate produces a high output
only when all the inputs are low.
Figure 1.5 NOR gate
Truth table:
A
0
0
1
1
B
0
1
0
1
_____
Y= A+B
1
0
0
0
XOR gate
XOR (Figure 1.6) gate is an abbreviation of exclusive OR gate. It has two
inputs and one output. For a two input XOR gate, the output is high when the inputs
are different and the output is low when the inputs are same. In general, the output of
an XOR gate is high when the number of its high inputs is odd. The Boolean
expression of the
XOR gate is
_
_
Y = A.B + A.B
a) Logic diagram
34
b) Logic symbol:
Figure 1.6 XOR gate
Truth table:
A
B
Y= A B
0
0
0
0
1
1
1
0
1
1
1
0
Uses of XOR gate:
1. Binary to Gray Converter
Figure 1.7 Binary to Gray Converter
The Figure 1.7 shows the way to convert binary number to gray number using
XOR gates. Since mod-2 addition is involved in the conversion, XOR gate is used for
this purpose.
2. Gray to Binary Converter:
XOR gate is also used to convert gray code to a binary number. The circuit
diagram for this operation is shown in the Figure 1.8.
Figure 1.8 Gray to Binary Converter
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3. Parity checker:
Parity checker can be designed using XOR gates as given in the Figure 1.9. Here the
parity of the word ABCD is checked. The circuit adds the bits of ABCD. A final sum
of 0 implies even parity and a sum of 1 means odd parity.
Figure 1.9 Parity checker
Basic Laws of Boolean Algebra
Commutative law:
A+B=B+A
B+A=A+B
Associative law:
A + (B + C) = (A + B) + C
A. (B.C) = (A.B).C
Distributive law
A. (B + C) = A.B + A.C
Other laws of Boolean algebra:
1. A + 0 = A
2. A + 1 = 1
3. A + A = A
4. A + Ā = 1
5. A .0 = 0
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6. A .1 = A
7. A .A = A
8. A . Ā = 0
=
9. A = A
10. A + A.B =A
11. A.(A + B) = A
12. (A + B).(A+C) = A + B.C
13. A + Ā.B =A + B
14. A.(Ā +B) = A.B
15. (A + B).(Ā + C) = A.C + Ā.B
16. (A + C).(Ā + B) = A.B + Ā.C
De Morgan’s Theorems:
I Theorem statement:
The complement of a sum is equal to
_____ _ _
A+B=A.B
the product of the complements.
II Theorem Statement:
The complement of a product is equal to the sum of the complements.
____ _ _
A.B= A+B
Proof of first theorem:
_____
_ _
To prove A + B = A . B
Case 1: A=0, B=0
_____ _____
_
L.H.S => A + B = 0 + 0 = 0 = 1
_
_
_ _
R.H.S => A . B = 0 . 0 = 1 .1 = 1
Case 2: A=0, B=1
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_____ _____
_
L.H.S => A + B = 0 + 1 =
1 =0
_
_ _ _
R.H.S => A . B = 0 . 1 = 1 .0 = 0
Case 3: A=1, B=0
_____ _____
_
L.H.S => A + B = 1 + 0 =
1 =0
_
_ _ _
R.H.S => A . B = 1 . 0 = 0 .1 = 0
Case 4: A=1, B=1
_____ _____
_
L.H.S => A + B = 1 + 1 =
1 =0
_
_ _ _
R.H.S =>
A . B = 1 . 1 = 0 .0 = 0
Truth table
A
B
0
0
1
1
0
1
0
1
____
_
A+B
1
0
0
0
_
_
A.B
1
0
0
0
Proof of second theorem:
____
_ _
To prove A . B = A + B
Case 1: A=0, B=0
____
___
_
L.H.S => A . B = 0 . 0 = 0 = 1
_ _
_ _
R.H.S => A + B = 0 + 0 = 1 + 1 = 1
Case 2: A=0, B=1
____
____
_
L.H.S => A . B = 0 . 1 = 0 = 1
_ _ _ _
R.H.S => A + B = 0 + 1 = 1 + 0 = 1
Case 3: A=1, B=0
38
____
____ _
L.H.S => A . B = 1 . 0 = 0 = 1
_
_ _
_
R.H.S => A + B = 1 + 0 = 0 +1 = 1
Case 4: A=1, B=1
____
____
_
L.H.S => A . B = 1 . 1 = 1 = 0
_ _
_ _
R.H.S => A + B = 1 + 1
= 0 +0 = 0
Truth table
A
B
0
0
1
1
0
1
0
1
____
_
A.B
1
1
1
0
_
_
A+B
1
1
1
0
BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS
Introduction
We have studied so far logic gates and Boolean algebra. Boolean algebra and
theorems are used for the manipulations of logical expressions. It has also been seen that
a logical expression can be realized by using the logic gates. The number of gates
required and the number of input terminals for the implementation of a logical
expression, in general, get reduced considerably if the expression can be simplified.
Therefore, the simplification of logical expression is very important as it saves the
hardware required to design a specific system
We know that logical expressions are implemented by connecting specific logic
gates. These logic gates produce a specific output for certain specified combinations of
input variables, with no storage involved. These circuits are commonly known as
combinational circuits. In combinational circuits, the output level is always dependent on
the combinations of the input levels.
The combinational circuits can be specified in one of the following ways:
3. A set of statements
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4. Boolean expression, and
5. Truth table.
In this section we will continue our study of combinational circuits and we will
further study various methods of simplifications of logical circuits.
Simplification of Boolean Expressions:
Simplification of Boolean functions is mainly used to reduce the gate count of a
design. Less number of gates means less power consumption, sometimes the circuit
works faster and also when number of gates is reduced, cost also comes down. There are
many ways to simplify a logic design; some of them are given below. We will be looking
at each of these in detail in the next few pages.
4. Algebraic Simplification.
Simplify symbolically using theorems/postulates.
Requires good skills
5. Karnaugh Maps.
- diagram'.
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here:
1. Simplify the Boolean expression
XY′Z′+XY′Z′W+XZ′
The above
be written as
expression can
XY′Z′ (1+W) +XZ′ as 1+W=1
=XY′Z′+XZ′ =XZ′
(Y′+1)
as Y′+1=1
=XZ′
2. Simplify the Boolean expression
X+X′Y+Y′+(X+Y′) X′Y
The above expression can be written as
X+X′Y+Y′+XX′Y+Y′X′Y
=X+X′Y+Y′
as XX′=0,
and YY′=0
=X+Y+Y′
as X+X′Y=X+Y
=X+1
as Y+Y′=1
=1
as X + 1=1
3. Simplify the Boolean expression
Z(Y+Z) (X+Y+Z)
The above expression can be written as
(ZY+ZZ)(X+Y+Z)
= (ZY+Z) (X+Y+Z)
as ZZ=Z
=Z(X+Y+Z)
as
Z+ZY=Z
=ZX+ZY+ZZ
=ZX+ZY+Z
as ZZ=Z,
=ZX+Z
as Z+ZY=Z
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=Z
as Z+ZX=Z
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4. Simplify the Boolean expression
(X+Y)(X′+Z)(Y+Z)
The above expression can be written as
(XX′+XZ+YX′+YZ)(Y+Z)
=(XZ+YX′+YZ) (Y+Z)
as
XX′=0
=XZY+YYX′+YYZ+XZZ+YX′Z+YZZ
=XZY+YX′+YZ+XZ+YX′Z+YZ
as
YY=Y, ZZ=Z
Rearranging the terms we get
XZY+XZ+YX′+YX′Z+YZ
as YZ+YZ=YZ
=XZ(Y+1) +YX′+YZ (X′+1)
as Y+1=1, X′+1=1
=XZ+YX′+YZ
Now it seems that it cannot be reduced further. But apply the following trick:
The above expression can be written as
XZ+YX′+YZ(X+X′)
as X+X′=1
=XZ+YX′+YZX+YZX′
Rearranging the terms we get
XZ+YXZ+Y X′+YX′Z
=XZ (1+Y) +YX′ (1+Z)
=XZ+YX′
as 1+Y=1, 1+Z=1
Sum of Products:
A sum of products expression consists of several product terms logically added. A
product term is a logical product of several variables. The variables may or may not be
complemented. The following are the examples of sum of products expressions.
1. XY+X'Y+XY'
2. AB+ABC+BC'
3. A+AB'+B'C
4. ABC+A'B+AB'C+A'BC'
Sometimes a product term may consist of a single variable.
45
Products of Sums:
8 product of sums expression consists of several sum terms logically multiplied.
A sum term is the logical addition of several variables. The variables may or may not be
complemented. The following are examples of product of sums expressions:
A) (A+B) (A'+B')
B) A (B'+C') (B+C)
c) (X+Y') (X+Y+Z) (Y+Z)
Sometimes a sum term may consist of a single variable.
Canonical SOP and POS Forms:
When each term of a logic expression contains all variables, it’s said to be in the
canonical form. When a sum of products form of logic expression is in canonical form,
each product term is called minterm. Each minterm contains all variables. The canonical
form of a sum of products expression is also called minterm canonical form or standard
sum of products. Similarly, when a product of sums form of logic expression is in
canonical form, each sum term is called a maxterm. Each maxterm contains all variables.
The canonical form of a product of sums expression is also called maxterm canonical
form or standard product of sums.
When a logic expression is not in the canonical form, it can be converted into
canonical form. In the canonical form there is uniformity in the expression, which
facilitates minimization procedure
The following are examples of the canonical form of sum of products expressions
(or minterm canonical form):
(i). Z = XY + XY′
(ii). F = XYZ′ + X′YZ + X′YZ′ + XY′Z + XYZ
In case of 2 variables, the maximum possible product terms are 4, for 3 variables,
the possible product terms are 8, for 4 variables 16, and for n variables, 2ⁿ.
In the above examples the expression (ii) contains 5 out of 8 possible product terms.
When the expression is in the canonical form all terms are mutually exclusive. It means
that for a given set of values of the variables, when one of the terms is equal to 1, all
others must be 0. Of course, it is possible that all terms may be 0.
46
The following are examples of canonical form of product of sums expressions (or
maxterm canonical form).
47
(i). Z = (X + Y) (X + Y′)
(ii). F = (X′ + Y + Z′) (X′ + Y + Z) (X′ + Y′ + Z′)
The following table gives the minterms and maxterms for a three variable logical
function where the number of minterms as well as maxterms is 2³ = 8. In general, for an
n-variable logical function there are 2ⁿ minterms and an equal number of maxterms.
A
0
0
0
0
1
1
1
1
Variables
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Minterms
mi
A' B' C' = m0
A' B' C = m1
A' B C' = m2
A' B C = m3
A B' C' = m4
A B' C = m5
A B C' = m6
A B C = m7
Maxterms
Mi
A + B + C = M0
A + B + C' = M1
A + B' + C = M2
A + B' + C' = M3
A' + B + C = M4
A' + B + C' = M5
A' + B' + C = M6
A' + B' + C' = M7
Minterms and Maxterms for Three variables
As shown in the above table each minterm is represented by mi and each maxterm
is represented by Mi where i is the decimal number equivalent of the natural binary
number. With these shorthand notations logical functions can be represented as follows:
1.
Y = A' B' C’ + A’ B’ C + A’ B C + A B C’
m0 + m1 + m3 + m6
∑m( 0, 1, 3, 6 )
2.
Y = ( A + B + C’ ) ( A + B’ + C’ ) ( A’ + B’ + C )
M1 + M3 + M6
πM( 1, 3, 6 )
Where ∑ denotes sum of product while π denotes product of sum
48
Conversion of Sum of Products Expressions into Canonical Form
The following examples will illustrate how logic expressions can be converted into
canonical form.
Example 1: Convert the expression X + XY’ into canonical form.
The expression has two variables. The first term has only one variable. So to make
it of two variables it can be multiplied by (Y + Y’), as Y + Y’ = 1. After multiplication
the given logic expression can be written as
X(Y + Y′) + XY′, as Y + Y′ = 1
or XY + XY′ + XY′
or XY + XY′
Conversion of Product of Sums Expression into Canonical Form:
Before we proceed with such a conversion a few identities should be
examined. We can write A = (A + B) (A + B′)
This can be proved as follows:
A = A +A + 0
= A( B + B′ ) + A.A + B.B′, as B + B′ =1, AA=A, BB′=1
= AB + AB′ + AA + BB′
= A (A +B) + B′ (A + B)
= (A + B) (A + B′)
Similarly, we can write A + B = (A + B +C) (A + B +
C′). (A + B + C) (A + B + C′)
= AA + AB + AC′ + AB + BB + BC′ + AC + BC + CC′
Rearranging the terms we get
AA + BB + AC′ + BC′ + AC + BC + AB + AB, as CC′ = 0
= (A + B) + C′ (A + B) + C (A + B) + AB + AB
[AA = A; BB = B]
= (A + B) + (A + B) (C + C′) + AB + AB
= (A + B) + (A + B) + AB + AB
= A + B + AB + AB
as C + C′ = 1
as (A + B) + (A + B) = (A + B)
= A + AB + B + AB
= A (1 + B) + B (1 + A)
=A+B
as 1 + B = 1,
1 + A =1
49
This technique can be extended to any number of variables such as
(A + B′ + C) = (A + B′ + C + D) (A + B′ + C + D′)
Example 1: Convert the following expression into canonical form:
(A + B) (B + C)
To convert the above expression into canonical form the following identity can be
used: X + Y = (X + Y + Z) (X + Y + Z′)
Applying the above identity, the given logic expression can be written as
(A + B + C) (A + B + C′) (A + B + C) (A′ + B + C)
= (A + B + C) (A + B + C′) (A′ + B + C)
Karnaugh Maps
Karnaugh maps provide a systematic method to obtain simplified sum-of-products
(SOPs) Boolean expressions. This is a compact way of representing a truth table and is a
technique that is used to simplify logic expressions. It is ideally suited for four or less
variables, becoming cumbersome for five or more variables. Each square represents either
a minterm or maxterm. A K-map of n variables will have 2 squares. For a Boolean
expression, product terms are denoted by 1's, while sum terms are denoted by 0's.
A K-map consists of a grid of squares, each square representing one canonical
minterm combination of the variables or their inverse. The map is arranged so that
squares representing minterms which differ by only one variable are adjacent both
vertically and horizontally. Therefore XY'Z' would be adjacent to X'Y'Z' and would also
adjacent to XY'Z and XYZ'.
Minimization Technique
·
Based on the Unifying Theorem: X + X' = 1
·
The expression to be minimized should generally be in sum-of-products form (If
necessary, the conversion process is applied to create the sum-of-products form).
·
The function is mapped onto the K-map by marking a 1 in those squares
corresponding to the terms in the expression to be simplified (The other squares
may be filled with 0's).
50
·
Pairs of 1's on the map which are adjacent are combined using the theorem
Y(X+X') = Y where Y is any Boolean expression (If two pairs are also adjacent,
then these can also be combined using the same theorem).
51
The minimization procedure consists of recognizing those pairs and multiple pairs
->These are circled indicating reduced terms.
o Groups which can be circled are those which have two (21) 1's, four (22)
1's, and eight (23) 1's.
->Note that because squares on one edge of the map are considered adjacent to those
on the opposite edge, group can be formed with these squares.
->Groups are allowed to overlap.
The objective is to cover all the 1's on the map in the fewest number of groups and to
create the largest groups to do this.
Once all possible groups have been formed, the corresponding terms are identified.
->A group of two 1's eliminates one variable from the original minterm.
->A group of four 1's eliminates two variables from the original minterm.
->A group of eight 1's eliminates three variables from the original minterm, and so on.
->The variables eliminated are those which are different in the original minterms of
the group.
In any K-Map, each square represents a minterm. Adjacent squares always differ by
just one literal (So that the unifying theorem may apply: X + X' = 1). For the 2-variable
case (e.g.: variables X, Y), the map can be drawn as in Figure 2.2.4 (a). Two variable map
is the one which has got only two variables as input.
Figure 2.2.4 (a)
52
Equivalent Labeling
K-map need not follow the ordering as shown in the Figure 2.2.4(a). What this
means is that we can change the positions of m0, m1, m2, m3 of the above figure as
shown in the Figure 2.2.4 (b) and Figure 2.2.4(c).
Position assignment is the same as the default k-map positions. This is the one which we
will be using throughout this unit.
Figure 2.2.4 (b)
This figure is with changed positions of m0, m1, m2, m3.
Figure 2.2.4(c)
The K-map for a function is specified by putting a '1' in the square corresponding to a
minterm, a '0' otherwise.
Grouping/Circling K-maps
The power of K-maps is in minimizing the terms, K-maps can be minimized with
the help of grouping the terms to form single terms as shown in Figure 2.2.4 (d). When
forming groups of squares, observe/consider the following:
53
·
Every square containing 1 must be considered at least once.
·
A square containing 1 can be included in as many groups as desired
A group must be as large as possible.
Figure 2.2.4 (d)
2 If a square that is containing 1 which cannot be placed in a group, then leave it out
to include in final expression.
3 The number of squares in a group must be equal to 2(pair), 4(quad), 8(octet).
The map is considered to be folded or spherical; therefore squares at the end of a row or
column are treated as adjacent squares.
The simplified logic expression obtained from a K-map is not always unique.
Groupings can be made in different ways as shown in Figure 2.2.4(e).
Before drawing a K-map the logic expression must be in canonical form.
54
Figure 2.2.4 (e)
In the next few pages we will see some examples of grouping.
2-Variable K-Map:
Example - F= X'Y+XY
In this example we have the equation as input, and we have one output function. Draw the
k-map for function F with marking 1 for X'Y and XY positions. Now combine two 1's as
shown in Figure 2.2.4 (f) to form the single term. As you can see X and X' get canceled
and only Y remains F = Y
55
Figure 2.2.4 (f)
Example - X'Y+XY+XY'
In this example we have the equation as input, and we have one output function. Draw the
k-map for function F with marking 1 for X'Y, XY and XY positions. Now combine two
1's as shown in Figure 2.2.4(g) to form two single terms.
F=X+Y
Figure 2.2.4(g)
3-Variable K-Map
There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable
K-map. One important thing to note is that K-maps follow the gray code sequence, not
the binary one.
Using gray code arrangement ensures that minterms of adjacent cells differ by only one
literal.
Each cell in a 3-variable K-map has 3 adjacent neighbours. In general, each cell in an nvariable K-map has n adjacent neighbours as shown in Figure 2.2.4(h)
56
Figure
2.2.4(h) There is wrap-around in the K-map
XY'Z' (m4) is adjacent to XYZ' (m6) as shown in Figure
2.2.4(i)
Figure 2.2.4(i)
Example
F = XYZ'+XYZ+X'YZ
57
F = XY + YZ
Example
F(X, Y, Z) = (1, 3, 4, 5, 6, 7)
F=X+Z
4-Variable K-Map
There are 16 cells in a 4-variable (W, X, Y, Z) K-map as shown in the Figure 2.2.4 (j).
Figure 2.2.4(j)
There are 2 wrap-arounds: a horizontal wrap-around and a vertical wrap-around. Every
cell thus has 4 neighbours. For example, the cell corresponding to minterm m0 has
56
neighbours m1, m2, m4 and m8 as shown in Figure 2.2.4(k).
Figure 2.2.4(k)
Example
F (W, X, Y, Z) = (1, 5, 12, 13)
F=WXY'+W'Y'Z
Example
F (W, X, Y, Z) = (4, 5, 10, 11, 14, 15)
57
F = W'XY' + WY
Don’t Care:
In some digital systems, certain input conditions never occur during normal
operations; therefore the corresponding output never appears. Since the output does not
appear it is indicated by an X in the truth table.X is called don’t care condition. So don’t
cares can be treated as 0’s and 1’s which ever is more convenient in the process of k-map
simplification.Consider the following truth table in which the output is low for all input
entries from 1001 and ‘X’ from 1010 through 1111. The don’t care conditions are
denoted by ’X’.
A
0
B
0
C
0
D
0
Y
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
X
1
0
1
1
X
1
1
0
0
X
1
1
0
1
X
1
1
1
0
X
1
1
1
1
X
58
Here three don’t cares are treated as 1’s to get a quad which eliminates two
variables. The remaining don’t cares are treated as 0’s.
Steps to be followed to apply don’t care conditions:
1. For the given truth table, draw a K-map with 0’s, 1’s and don’t cares.
2. Encircle the actual 1’s on the K-map in the largest groups, by treating the don’t cares as
1’s.
3. After the actual 1’s have been included in groups discard the remaining don’t cares
visualizing them as 0’s.
Implementing Boolean Expressions Using NAND Gates:
The implementation of a Boolean function with NAND-NAND logic requires that
the function be simplified in the sum of product form. The relationship between AND-OR
logic and NAND-NAND logic is explained using the following example.
Consider the Boolean function: Y = A B C + D E + F
This Boolean function can be implemented using AND-OR logic as shown
in Figure 2.2.5 (a).
Figure 2.2.5 (a) AND-OR
Figure 2.2.5 (b) NAND-Bubbled OR
59
Figure 2.2.5 (b) shows the AND gates are replaced by NAND gates and the OR gate
is replaced by a bubbled OR gate. The implementation shown in Figure 2.2.5(b) is
equivalent to implementation in Figure 2.2.5 (a), because two bubbles on the same line
represent double inversion (complementation) which is equivalent to having no bubble on
the line. In case of single variable, F, the complemented variable is again complemented by
bubble to produce the normal value of F.
Figure 2.2.5(c) NAND-NAND
In Figure 2.2.5 (c), the output NAND gate is redrawn with the conventional symbol. The
NAND gate with same inputs gives complemented result; therefore F′ is replaced by
NAND gate with F input to its both inputs. Thus all the three implementations of the
Boolean function are equivalent.
From the above example we can summarize the rules for obtaining the NANDNAND logic diagram from a Boolean function as follows:
1. Simplify the given Boolean function and express it in sum of products
form (SOP form).
2. Draw a NAND gate for each product term of the function that has two
or more literals. The inputs to each NAND gate are the literals of the term. This
constitutes a group of first-level gates.
3. If Boolean function includes any single literal or literals draw NAND gates for
each single literal and connect corresponding literal as an input to the NAND
gate.
4. Draw a single NAND gate in the second level, with inputs coming from outputs
of first level gates.
60
Implementing Boolean Expressions Using NOR Gates:
The NOR function is a dual of the NAND function. For this reason, the
implementation procedures and rules for NOR-NOR logic are the duals of the
corresponding procedures and rules developed for NAND-NAND logic.
The implementation of a Boolean function with NOR-NOR logic requires that the
function be simplified in the product of sums form. In product of sums form, we implement
all sum terms using OR gates. This constitutes the first level. In the second level all sum
terms are logically ANDed using AND gates. The relationship between OR-AND logic and
NOR-NOR is explained using following example
Consider the Boolean function: Y = (A + B +C) (D + E) F
The Boolean function can be implemented using OR-AND logic, as shown in the
Figure 2.2.6 (a)
Figure 2.2.6 (a) OR-AND
61
Figure 2.2.6 (b) NOR-Bubbled AND
In Figure 2.2.6 (b) the OR gates are replaced by NOR gates and the AND gate is
replaced by a bubbled AND gate. The implementation shown in Figure 2.2.6 (b) is
equivalent to implementation shown in Figure 2.2.6 (a) because two bubbles on the same
line represent double inversion (complementation) which is equivalent to having no bubble
on the line. In case of single variable, F, the complemented variable is again complemented
by bubble to produce the normal value of F.
Figure 2.2.6(c) NOR-NOR
In Figure 2.2.6 (c), the output NOR gate is redrawn with the conventional symbol. The
NOR gate with same inputs gives complemented result, therefore, F is replaced by NOR
gate with F input to its both inputs. Thus all the three implementations of the Boolean
function are equivalent.
From the above example, we can summarize the rules for obtaining the NOR-NOR logic
diagram from a Boolean function as follows:
1. Simplify the given Boolean function and express it in product of sums form(POS
form)
2. Draw a NOR gate for each sum term of the function that has two or more
literals. The inputs to each NOR gate are the literals of term. This constitute a
group of first level gates.
3. If Boolean function includes any single literal or literals, draw NOR gate for
each single literal and connect corresponding literal as an input to the NOR
gate.
4. Draw a single NOR gate in the second level, with inputs coming from outputs of
first level gates
62
UNIT-II
COMBINATIONAL LOGIC
INTRODUCTION
A logic circuit of the digital system may be sequential or Combinational
 A combinational circuit consists of logic gates whose outputs are determined only from
the present input only.
 A Sequential circuit consists of logic gates and memory Elements whose outputs are
determined from the present input and the state of the Memory Element.
Combinational circuits
 Logic gates/elements – output determined only from the present inputs
variable combinations.
 Consists of input variables, logic gates and output variables
 Logic gates perform some function on the input and generate output
signals.
 It does not have any feed back connection or memory element.
Sequential circuits
 Employ storage elements in addition to gates
 Consists of input variables, logic gates and output variables and state of
memory element
 State of the storage elements depend on the previous inputs
 Output of Sequential circuits may depend on present and past values of
inputs
 It may be synchronous or asynchronous.
COMBINATIONAL CIRCUITS
A combinational circuit consists of logic gates whose outputs are determined only
from the present input. There is no looping or memory element in this.
63
BLOCK DIAGRAM OF A COMBINATIONAL CIRCUIT
 There are no registers or memory elements in the diagram.
 Further there are no feedback paths or loops (i.e. no connection from the output of one
gate to the input of a second gate that forms a part of the input to the first gate)
 Combinational circuit can be specified by a truth table
o
n inputs 2n possible input combinations
o
For each possible input – 1 possible output value
 Some standard combinational circuits
o
Adders, sub tractors, comparators, decoders etc.
Each input variable to a combinational circuit may have one or two wires. When only one
wire is used, the variable may be appearing in its own form or its complement form. When two
wires are used it is necessary to use inverters for inputs.
DESIGN PROCEDURE OF A COMBINATIONAL CIRCUIT
The Design of the combinational circuits starts from the verbal outline of the problem and
ends in a logic circuit diagram or a set of Boolean functions from which the logic diagram can be
easily obtained.
Steps:
1. Determine Number of inputs and number of outputs to the system and assign names to the
input and output variables.
2. Setup a truth table which specifies the output(s) as a function of the input variables.
64
3.
Drive the Algebric Expression for the outputs from the truth table.
4.
Drive simplified algebraic expressions for the output functions using K-maps, the
Tabulation method, or other similar procedures.
5. Draw the circuit diagram using logic gates.
Constraints while Using Gates:
 Minimum Number of logic gates.
 Minimum Number of inputs to the logic gates.
 Minimum propagation Delay
 Minimum number of Interconnections
Circuit Design Using Sum-Of-Products:
A correct two-level circuit can be generated for any sum-of-products expression
Using the following steps:


Required is determined by the number of variables in the product term


gate for the output; the number of inputs required is determined
by the number of AND gates.
Example: CODE CONVERTION
The code converter is a combinational circuit which converts the binary code from
one format to another.
BCD TO EXCESS-3 CODE CONVERTOR:
BCD and Excess-3 both uses 4-bit Binary Codes. Excess -3 Codes is 3 greater than the BCD
code.
65
Block diagram:
BCD INPUTS
EXCESS -3
OUTPUTS
BCD to EXCESS -3
CODE CONVERTERS
DESIGNING:
Step 1:
Determining Number of Inputs and Number of Outputs of the circuit:
Number of Inputs: 4 (A, B, C, D)
Number of Outputs: 4 (w, x, y, z)
Step -2:
Obtaining the Truth Table of the Design
BCD (Input )
EXCESS-3 (Output)
A
B
C
D
W
X
Y
Z
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
66
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
Simplified Boolean Expression:
 z = D’
 y = CD + C’D’ = CD + (C+D)’
 x = B’C + B’D + BC’D’ = B’(C+D) + B(C+D)’
 w = A + BC + BD = A + B (C+D)
The (C+D) factor is used to partially implement the outputs w, x and y.
67
LOGIC DIAGRAM
ANALYSING COMBINATIONAL CIRCUITS
Analyzing is the reverse process of Designing. The process starts from circuit diagram and
ends in verbal explanation.
Steps in analyzing the digital circuit:
 Derive the Boolean Expression for Each output variables (Determine the output function
for each intermediate function(s)) from the circuit diagram.

Develop the Truth table, which consists of input and output variables and their values.
 Explanation of the circuit operation as a verbal explanation.
EXAMPLE: Analyze the circuit given below
68
BOOLEAN EXPRESSIONS:
F2 = AB + AC + BC
T1= A + B + C
T2= ABC
T3= F2’ T1
F1 = T3+ T2
69
 Substituting the values for T3 and T2 we get: F1= A’BC’ + A’B’C + AB’C’ +ABC
 The information-transformation the circuit achieves is that of adding 3 bits of
information – a full adder
•
Can be analyzed by deriving the truth table
–
Inspection of the truth table (i.e. for the inputs A, B and C and outputs F1
and F2)
–
So finally we confirm that it is identical to that of the full adder.
COMBINATIONAL CIRCUIT FOR ARITHMETIC OPERATIONS
The basic operation of a digital computer is addition. Basically there are two types of
adder circuit.
 Half Adder
 Full Adder
 Binary adder
 Half Subtactor
 Full Subtactor
 Multiplier
HALF ADDER
The half adder is the most primitive of the arithmetic circuits. It has two inputs-the
bits to be added-and two outputs-the sum and a carry-out.
Two inputs: x and y (x and y are binary variable)
Two outputs: sum(S) and carry(C)
Truth table:
X
Y
Sum
Carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Logic Diagram:
70
FULL ADDER:
–
Adds 3 bits x, y and z bit which is a carry from the previous lower significant bit
position
–
2 outputs S (sum) and C (carry) – need at least 2 outputs to represent numbers in
range 0 to 3
TRUTH TABLE:
71
The full adder has three inputs-A, B, and CI (carry-in)-and two outputs-S (sum)
and C (carry-out). S is written as
Logic Diagram:
MULTI-BIT ADDER:
If we want to do multi-bit additions, a half adder isn't enough. When we do
addition with pencil and paper, the carry from one column of digits is added to the sum of
the column to its left. The same works for binary addition. We form the ith sum from the
addition of the ith bits and the carry-out of the (i - 1)st sum.
ADDER/SUBTRACTOR:
72
Figure shows the circuit for a 4-bit adder/subtractor constructed from full adder building
blocks. Besides the Ai and Bi inputs, we have introduced a control input
. When this
signal is 0, the circuit performs addition. When it is 1, the circuit becomes a subtractor.
BCD ADDER CIRCUIT:
BCD, or binary-coded decimal, represents the 10 decimal digits in terms of binary
numbers.
for example, let's consider the addition of the two BCD digits 5 and 3:
Now consider the sum of 5 and 8:
The sum is 11012 = 13, but this result should be correctly represented as 0001 0011
in BCD notation. Fortunately, there is a simple way to find the correct result. We add 6
(01102) to the digit sum if it exceeds 9. Let's examine the following cases:
73
In both cases, by adding six we obtain the correct answer in BCD. This observation
is critical to the design of a BCD adder, as we shall see in the next subsection.
BCD Adder Design
Combinational Multiplier
The two numbers involved in a multiplication are called the multiplicand and the
multiplier. The process of binary multiplication is illustrated with an example. In this case, the
multiplicand is 11012 (13) and the multiplier is 10112 (11):
74
Each bit of the multiplier is multiplied against the multiplicand, the product is
aligned according to the position of the bit within the multiplier, and the resulting products
are then summed to form the final result. One attraction of binary multiplication is how
easy it is to form these intermediate products: if the multiplier bit is a 1, the product is an
appropriately shifted copy of the multiplicand; if the multiplier bit is a 0, the product is
simply 0.
Two bit Binary Multiplier:
With J multiplier bits and K multiplicand bits – need JxK AND gates and (J-1) Kbit adders to produce J+K bits
For an n-bit multiplicand and multiplier, the resulting product will be 2n bits.
Stated differently, the product of 2n and 2n is 2n + n = 22n, a 2n-bit number. Thus, the
product of two 4-bit numbers requires 8 bits, of two 8-bit numbers requires 16 bits, and so
on.
4 –BIT MULTIPLIER
75
The first level of 16 AND gates computes the individual partial products.
The second- and third-level logic blocks form the accumulation of the products on
a column-by-column basis. The column sums are formed by a mixture of cascaded half
adders and full adders.
CODE CONVERTION
Code converters are combinational circuits which convert the values from one form to
another form.
Examples of code converters are,
 BCD to Binary
 Binary to BCD
 Binary to Excess-3
Code converters are designed using the same procedure as combinational circuit
HARDWARE DESCRIPTION LANGUAGE
HDL is a language that describes the hardware of the digital system in a textual form. For
example, a network switches, a microprocessor or a memory or a simple flip-flop. This just means
that, by using a HDL one can describe any hardware (digital) at any level.
76
It resembles a programming language, but it is specifically oriented to describing
hardware structures and behavior.
As a documentation language, HDL is used to represent and document digital system in a
form that can be read by both human and computer.
There are two types of applications of HDL Processing
1. Simulation
2. Synthesis.
Simulation:
Logic simulation is the representation of the structure and behavior of a digital system
through the use of a computer.
A Simulator interprets the HDL description and produces readable output such as timing
diagram, that predicts how the hardware will be behave after it was fabricated.
The stimulus that tests the functionality of the design is called Test Bench.
Thus to simulate a digital system, the design is first described in HDL and then verified by
simulating the design and checking it with a test bench.
Synthesis:
Logic synthesis is the process of deriving a list of components and their interconnection
from the model of a digital system described in HDL.
There are two standards for HDL that is supported by IEEE.
VHDL
Verilog HDL
Verilog is an easier language to learn and use. HDL is a harder language.
MODULE REPRESENTATION:
77
Verilog HDL has a syntax that describes precise;y the legal constructs that can be used in
the language. Verilog uses about 100 keywords such as module, endmodule, input, output …etc.
Module is the building block in verilog. It is declared by the keyword module and it is
terminated by the keyword endmodule.
The line with two slashes is a comment that explains the function of the circuit.
Example
//Decription of simple circuit
module smpl_circuit
input A,B,C;
output x, y;
wire e;
and g1(e,A,B);
not g2(y1,C);
or g3(x,e,y);
endmodule
Gate Delay :
It is sometimes necessary to specify the amount of delay from the input to the output of gates.
In verilog, the delay is specified in terms of time units and the symbol#.
Example :
//Decription of simple circuit with delay
module smpl_circuit
input A,B,C;
output x, y;
78
wire e;
and #(30) g1(e,A,B);
not #(20) g2(y1,C);
or #(10) g3(x,e,y);
endmodule
#(30) is the time delay given to the and gate.
In order to simulate a circuit with HDL, it is necessary to apply inputs to the circuit for the
simulator to generate an output response.
Example ;
A test bench for simulating the circuit with delay, Here two modules are included.
1. A stimulus module
2. The circuit description Module.
//stimulus for sample circuit
module stimcrct
reg A,B,C;
wire x,y;
circuit_with_delay cwd(a,B,C,X,Y);
initial
begin
A=1’b0;B=1’b0;C=1’b0;
#100
A=1’b1;B=1’b1; 1’b1;
79
#100
$finish;
end
endmodule
//Decription of simple circuit with delay
module
circuit_with_delay cwd(a,B,C,X,Y);
input A,B,C;
output x, y;
wire e;
and #(30) g1(e,A,B);
not #(20) g2(y1,C);
or #(10) g3(x,e,y);
endmodule
Boolean Expressions:
Boolean Expressions are specified in verilog with a continuous assignment statement
consisting of the keyword “assign” followed by a Boolean Expression.
Logical And,OR,Not are denoted by (&), (|),(~) symbol Respectively.
Example :
Assign x=((a&b) | ~c);
80
UNIT – III
DESIGN WITH MSI DEVICES
DECODER

A decoder is a combinational circuit which converts given n inputs to
m (m<=2n) outputs.
 It is a multiple-input, multiple-output logic circuit that converts coded inputs
into coded outputs, where the input and output codes are different.
Example: n-to-2n, BCD decoders.
Binary n-to-2n Decoders:
 A binary decoder has n inputs and 2n outputs.
 Only the output corresponding to the input value is equal to 1.
n to 2n
n
inputs
:
Decoder
2n
:
outputs
2-to-4 Binary Decoder
2 – to-4 Line Decoder having 2 inputs and 4 outputs, each output represents one of the
minterm of the two input variables.
2
Inputs
4
2 to 4
Outputs
Decoder
81
Truth Table:
X
0
0
1
1
Y F0 F1 F2 F3
0 1 0 0 0
1 0 1 0 0
0 0 0 1 0
1 0 0 0 1
From truth table, circuit for 2x4 decoder :
F0 = X'Y'
F1 = X'Y
F2 = XY'
F3 = XY
X
Y
Implementing Functions Using Decoders
 Any n-variable logic function, in canonical sum-of-minterms form can be implemented
using a single n-to-2n decoder to generate the minterms, and an OR gate to form the
sum.

The output lines of the decoder corresponding to the minterms of the function are
used as inputs to the or gate.
82
 Any combinational circuit with n inputs and m outputs can be implemented with an nto-2n decoder with m OR gates.
 Suitable when a circuit has many outputs, and each output function is expressed with
few minterms.
Example: Full adder implementation using decoders
TRUTH TABLE OF FULL ADDER :
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
Boolean Expressions:
Sum :
S(x, y, z) = S (1,2,4,7)
Carry :
C(x, y, z) = S (3,5,6,7)
83
3-to-8
0
S
Decoder 1
x
S2
2
y
3
S1
z
C
4
5
S0
6
7
ENCODERS
 If the decoder's output code has fewer bits than the input code, the device is usually
called an encoder.
E.g. 2n-to-n, priority encoders.
 The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs = 1
and the output is the n-bit binary number corresponding to the active input.
Binary
n
2
inputs
.
.
encode
r
.
.
.
n
outputs
.
For an 8-to-3 binary encoder with inputs I0 - I7 the logic expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7
84
At any one time, only one input line has a value of 1.
Inputs
I
0
1
0
0
0
0
0
0
0
I
1
0
1
0
0
0
0
0
0
I 2
0
0
1
0
0
0
0
0
I 3
0
0
0
1
0
0
0
0
I 4
0
0
0
0
1
0
0
0
Outputs
I
5
0
0
0
0
0
1
0
0
I 6
0
0
0
0
0
0
1
0
I 7
0
0
0
0
0
0
0
1
y2
0
0
0
0
1
1
1
1
y1
0
0
1
1
0
0
1
1
y2
0
1
0
1
0
1
0
1
CIRCUIT DIAGRAM:
I0
Y2 = I4 + I5 + I6 + I7
I1
I2
y1 = I2 + I3 + I6 + I7
I3
I4
Y0 = I1 + I3 + I5 + I7
I5
I6
I7
MULTIPLEXERS
85
 A multiplexer (MUX) is a digital switch which connects data from one of n sources to the
output.
 A number of select inputs determine which data source is connected to the output.
Multiplexer
Enable
EN
s bits
Select
SEL
b bits
Data
D0
.
.
b bits
n Data
Y
D1
Sources
TRUTH TABLE:
86
outpu
t
SIMPLIFICATION:
This truth table can be simplified by allowing Don't-cares in the table:
CIRCUIT DIAGRAM:
4 * 1 MUX
A 4x1 MUX has
selections
and
. Its output
The truth table for a 4x1 MUX:
inputs
,
,
and
, and
is one of the four inputs depending on the selections.
87
88
Inputs
I0
I1
I2
I3
0
1
4:1
MUX Y
2
3
S1 S0
select
SYMBOL OF MUX
89
Output
Inputs
I0
I1
mux
I2
I3
Y
S1 S 0
select
IMPLEMENTAING LARGER MUX USING SMALLER MUX
 Larger multiplexers can be constructed from smaller ones.
An 8-to-1 multiplexer can be constructed from smaller multiplexers as shown:
I0
I1
4:1
MUX
I2
I3
2:1
MUX
S 1 S0
Y
I4
I5
4:1
MUX
S2
I6
I7
S 1 S0
DEMULTIPLEXERS
 Digital switches to connect data from one input source to one of n outputs.
 Usually implemented by using n-to-2n binary decoders where the decoder’s enable line is
used for data input of the demultiplexer.
90
2X4
Select
lines
Decoder
One of
four 1-bit
outputs
Input
Enable
data (1bit)
1-TO-4 DEMULTIPLEXER
Outputs
Y0 = D.S1'.S0'
Y1 = D.S1'.S0
Data D
DEMUX
Y2 = D.S1.S0'
Y3 = D.S1.S0
S1 S0
select
MEMORY
A memory unit is a collection of storage cells together with associated circuits needed to transfer
information in and out of the device. The time takes to transfer information in and out of the
91
device. The time it takes to transfer information to or from any desired random location is always
the same; hence the name random access memory abbreviated RAM.
A memory unit stores binary information in groups of bits called words. A word in
memory is an entity of bits that move in and out of storage as a unit. A memory word is a group
of I’s and O’s and may represent a number an instruction one or more alphanumeric characters or
any other binary coded information.
A group of eight bits is called a byte. Most computer memories use words that are
multiples of eight bits in length. Thus a 16 bit word contains two bytes and a 32 bit word is made
up of four bytes. The capacity of memory unit is usually stated as the total number of bytes that it
can store.
The communication between a memory and its environment is achieved through data input
and output lines address lines and control lines that specify the direction of transfer.
K address lines
Read
Memory unit
2K words
n bit per word
Write
n data output lines
92
The n data input lines provide the information to be stored in memory and the n data output lines.
Supply the information coming out of memory. The K address lines specify the particular word
chosen among the many available. The two control inputs specify the direction of transfer
desired.
RAM.
A read only memory (ROM) is essentially a memory device in which permanent binary
information is stored. The binary information must be specified by the designer and is then
embedded in the unit to form the required interconnection pattern.
Once the pattern is
established, it stays within the unit even when power is turned off and an again.
K inputs
2K X n
(Address)
ROM
(Data)
It consists of K inputs and n outputs. The inputs provide the address for the memory and the
outputs give the data bits of the stored word which is selected by the address. The number of
words in a ROM is determined from the fact that K addresses input lines are needed to specify 2 k
words.
Note that ROM does not have data inputs because it does not have a write operation.
Integrated circuits ROM chips have one or more enable inputs and sometimes come with three.
State outputs to facilitate the construction of large arrays of ROM.
In the 32 X 8 ROM unit consists of 32 words of 8 bits each. This means that there are 8
output lines and 32 distinct words stored in the unit each of which may apply to the output lines.
The particular word selected that is presently available on the output lines determined from the 5
input lines. There are only 5 inputs in a 32X8 ROM because 25 = 32 and five variables we can
specify 32 addresses or minterm.
93
The number of addressed words n a ROM is determined from the fact that n input lines
are needed to specify 2n words. A ROM is sometimes specified by the total number of bits it
contains, which is 2n Xm. This means that the unit has four lines and 9 input lines to specify 29 =
512 words. The total number of bits stored in the unit is 512 X 4 = 2048.
The ROM is a two level implementation in sum of minterms for. It does not have to be an
AND – OR implementation, but it can be any other possible two level minterm implementation.
PROGRAMMABLE LOGIC ARRAY (PLA)
A programmable logic array (PLA) requires that only the minterms required for a
function be implemented, and allows the implementation of several functions
simultaneously.
The functions can be implemented directly from their minterm forms (although it is
often possible to eliminate some of the minterms, further decreasing the cost of the PLA).
The PLA can be considered as a direct POS (or SOP) implementation of a set of
switching functions, with a set of AND functions followed by a set of OR functions.
A PLA is often said to have an ``AND'' plane followed by an ``OR'' plane. In
practice, either NAND or NOR gates are normally used, with the resulting PLA said to be a
NAND/NAND or a NOR/NOR device.
This often leads to opportunities for minimizing the area of a PLA.Thus the PLA is
an efficient device for the implementation of several functions of the same set of variables.
Boh ROM and PLA can be used to implement arbitrary functions in the sum-ofproduct (SOM, actually OR-of-AND) form.
Example:
Implement
the
following
function
This function is implemented by ROM as the OR of five minterms:
94
by
ROM
and
PLA:
CIRCUIT DIAGRAM :
Simplification using Karnaugh map:
The function can be implemented by a PLA as the OR of three terms:
95
96
FULL ADDER IMPLEMENTATION USING PLA.
HDL FOR COMBINATIONAL CIRCUITS
The module is the basic building blocks of Verilog HDL. A module can be described in any
one of the following methods.
 Gate Level Modeling
 Dataflow Modeling
 Behavioral Modeling
Gate-Level Modeling:
97
 Gate-Level Modeling Describes the circuit by specifying the gates and how they are
connected.
 It provides the textual description of schematic diagram.
 Verilog recognizes 12 basic gates as predefined primitives.
 Four primitive gates are of the three state type.
 The other 8 gates are and , nand , or , nor , xor , xnor , not ,buf
Three State (Tri-State) Buffers:
 Three state buffers are CMOS and TTL devices whose outputs may be in one of three
states: 0, 1 or Hi-Z (high impedance, or floating state.
 Have an extra input called “output enable” or “output disable”.
 When enables the device transmits the input value or its complement to the output.
Control
Control
Out
Out
In
In
bufifl
bufifo
notifl
notifo
Gate-Level description of 2-to-4 line decoder:
98
module decoder-g1(A,B,E,D);
input A,B,E;
output [0:3]D;
wire Anot,Bnot,Enot;
not
n1(Anot,A)
n2(Anot,A)
n3(Anot,A)
nand
n4(D[0],Anot,Bnot,Enot),
n5(D[1],Anot,B,Enot),
n6(D[2],A,Bnot,Enot),
n7(D[3],A,B,Enot),
endmodule
Gate Level Implementation of MUX:
Here is the gate level implementation of the given multiplexer.
module multiplexor4_1(out, in1, in2, in3, in4, cntrl1, cntrl2);
output out;
input in1, in2, in3, in4, cntrl1, cntrl2;
wire notcntlr1, notcntrl2, w, x, y, z;
not (notcntrl1, cntrl1);
not (notcntrl2, cntrl2);
and (w, in1, notcntrl1, notcntrl2);
and (x, in2, notcntrl1, cntrl2);
99
and (y, in3, cntrl1, notcntrl2);
and (z, in4, cntrl1, cntrl2);
or (out, w, x, y, z);
endmodule
Logic Statement Implementation of multiplexer:
module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1, cntrl2);
output out;
input in1, in2, in3, in4, cntrl1, cntrl2;
assign out = (in1 & ~cntrl1 & ~cntrl2) |
(in2 & ~cntrl1 & cntrl2) |
(in3 & cntrl1 & ~cntrl2) |
(in4 & cntrl1 & cntrl2);
endmodule
HDL FOR ENCODERS:
Encoders An encoder creates a data output set that is more compact than the input data.
A decoder reverses the encoding process
There are different ways. We can write by using If statement, Case Statement or Loop
Statement.
// A. If statements
always @(A)
begin
if(A == 8'b 00000001) Y=0;
else if (A == 8'b 00000010) Y=1;
100
else if (A == 8'b 00000100) Y=2;
else if (A == 8’b 00001000) Y=3;
else if (A == 8’b 00010000) Y=4;
else if (A == 8’b 00100000) Y=5;
else if (A == 8’b 01000000) Y=6;
else if (A == 8’b 10000000) Y=7;
else Y = 3’bX;
end
endmodule
// B. Case Statement
always @(A)
begin
casex(A)
8’b 00000001: Y=0;
8’b 00000010: Y=1;
8’b 00000100: Y=2;
8’b 00001000: Y=3;
8’b 00010000: Y=4;
8’b 00100000: Y=5;
8’b 01000000: Y=6;
8’b 10000000: Y=7;
101
default: Y=3’bX;
endcase
end
endmodule
// C. For Loop
reg [7:0] Test;
integer [2:0] N;
always @(A)
begin
Test=8’b00000001;
Y=3’bX;
for(N=0; N < 8; N = N+1)
begin
if(A == Test)
Y=N;
Test = Test << 1;
end
end
endmodule
The Stimulus Module
 Once a module has been designed it can be tested by applying test inputs. This is
idea of the stimulus module.
102
 It calls the design module and uses its functionality, then results can be monitored
to verify its design.
 A well written stimulus will be able to put the whole design through its paces.
stimulus for MUX
module muxstimulus;
reg IN1, IN2, IN3, IN4, CNTRL1, CNTRL2;
wire OUT;
multiplexor4_1 mux1_4(OUT, IN1, IN2, IN3, IN4, CNTRL1, CNTRL2);
initial begin
IN1 = 1; IN2 = 0; IN3 = 1; IN4 = 0;
$display("Initial arbitrary values");
#0 $display("input1 = %b, input2 = %b, input3 = %b, input4 = %b\n",
IN1, IN2, IN3, IN4);
{CNTRL1, CNTRL2} = 2'b00;
#1 $display("cntrl1=%b, cntrl2=%b, output is %b", CNTRL1, CNTRL2, OUT);
{CNTRL1, CNTRL2} = 2'b01;
#1 $display("cntrl1=%b, cntrl2=%b output is %b", CNTRL1, CNTRL2, OUT);
{CNTRL1, CNTRL2} = 2'b10;
#1 $display("cntrl1=%b, cntrl2=%b output is %b", CNTRL1, CNTRL2, OUT);
{CNTRL1, CNTRL2} = 2'b11;
#1 $display("cntrl1=%b, cntrl2=%b output is %b", CNTRL1, CNTRL2, OUT);
end
endmodule
 module muxstimulus; This is a top level module it, ie. nothing else calls it to use
its functionality, so it doesn't need a port list.
 The keyword module remains and the module name should be chosen to to indicate that
it is a stimulus module.
reg IN1, IN2, IN3, IN4, CNTRL1, CNTRL2;
103
wire OUT;
The inputs to the multiplexor are in1, in2, in3, in4, cntrl1 and cntrl2; and the
output from
the multiplexor is out.
The idea of the stimulus is to apply artificial stimulus to the inputs and see what values are
assigned to out by the multiplexor4_1 module.
It follows that the inputs must be reg data types and the output must be a wire.
multiplexor4_1 mux1_4(OUT, IN1, IN2, IN3, IN4, CNTRL1, CNTRL2);
This calls the multiplexor4_1 module, the syntax is
<module_name> <instance_name> (port list);
The instance name is necessary when calling user defined modules, this is to aid the
traversal down the hierarchy of design (but we will not cover this aspect of the language).
initial begin
IN1 = 1; IN2 = 0; IN3 = 1; IN4 = 0;
$display("Initial arbitrary values");
#0 $display("input1 = %b, input2 = %b, input3 = %b, input4 = %b\n",
IN1, IN2, IN3, IN4);
The main part of the simulation is enclosed in the construct initial begin ... end.
 The #0 before the display statement ensure that the display is made after the
assignment of values to the input.
 The assignments are made at simulation time 0, putting a #0 ensures that the
$display is executed at the end of the 0 time slice.
 The execution of an assignment using = is always in the order given so these don't
have to be time controlled.
The syntax of the $display is similar to that of printf in C,
104
$display( expr1, expr2, ...., exprN);
exprN can be variables, expressions or quotes strings.
{CNTRL1, CNTRL2} = 2'b00;
#1 $display("cntrl1=%b, cntrl2=%b, output is %b", CNTRL1, CNTRL2,
OUT);
The first line is an assignment to the control signals and is the same as saying
CNTRL1 = 0;
CNTRL2 = 0;
The concatenation operator { } can be used to make group assignments.
The number of bits in the assignment must be the same as the number of bits in the
variables.
{CNTRL1, CNTRL2} = 2'b01;
#1 $display("cntrl1=%b, cntrl2=%b output is %b", CNTRL1, CNTRL2, OUT);
{CNTRL1, CNTRL2} = 2'b10;
#1 $display("cntrl1=%b, cntrl2=%b output is %b", CNTRL1, CNTRL2, OUT);
{CNTRL1, CNTRL2} = 2'b11;
#1 $display("cntrl1=%b, cntrl2=%b output is %b", CNTRL1, CNTRL2, OUT);
end
endmodule
In the same way the values of the control signals are changed and the value of the output is
checked via the display.
105
UNIT –IV
SYNCHRONOUS SEQUENTIAL LOGIC
Combinational logic refers to circuits whose output is strictly depended on the
present value of the inputs.
Circuits whose outputs depend not only on the present input value but also the past
input value are known as sequential logic circuits. The mathematical model of a
sequential circuit is usually referred to as a sequential machine.
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Registers
Q
Next state
D
CLK
The sequential circuit consists of combinational circuit to which memory elements are
connected to form a feedback path. The memory elements are devices capable of storing binary
information within them.
Synchronous and Asynchronous Operation
Sequential circuits are divided into two main types depends on the timing of their
signals
 Synchronous sequential circuits
 Asynchronous sequential circuits
Synchronous sequential circuits:
Synchronous sequential circuits change their states and output values at discrete
instants of time, which are specified by the rising and falling edge of a free-running clock
signal.
Clock period is the time between successive transitions in the same direction, that
is, between two rising and two falling edges.
106
Clock Signal
The reciprocal of the clock period is referred to as the clock frequency. The clock
width is defined as the time during which the value of the clock signal is equal to 1.
The memory elements used in synchronous sequential circuits are usually flip-flops.
Flip- Flop are binary cells capable of storing one bit of information. A flip-flop
circuit has two outputs, one for the normal value and one for the complement value of the
bit stored in it.
Asynchronous sequential circuits:
In asynchronous sequential circuits, the transition from one state to another is
initiated by the change in the primary inputs; there is no external synchronization.
The memory commonly used in asynchronous sequential circuits is time-delayed
devices, usually implemented by feedback among logic gates.
Thus, asynchronous sequential circuits may be regarded as combinational circuits
with feedback.
FLIP-FLOPS AND THEIR BEHAVIORS
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in
the number of inputs and in the response invoked by different value of input signals.
FLIPFLOP
NAME
FLIP-FLOP SYMBOL CHARACTERISTIC TABLE
107
CHARACTERISTIC
EQUATION
EXCITATION TABLE
S
R
Q(next)
Q Q(next)
S R
0
0
Q
0 0
0 X
0
1
0
0 1
1 0
1
0
1
1 0
0 1
1
1
?
1 1
X 0
J
K
Q(next)
Q Q(next)
J K
0
0
Q
0 0
0 X
0
1
0
0 1
1 X
1
0
1
1 0
X 1
1
1
Q'
1 1
X 0
Q(next) = S + R'Q
SR
SR = 0
JK
D
T
Q(next) = JQ' + K'Q
D
Q(next)
0
0
1
1
Q(next) = D
T
Q(next)
0
Q
1
Q'
Q(next) = TQ' + T'Q
108
Q
Q(next)
D
0
0
0
0
1
1
1
0
0
1
1
1
Q Q(next)
T
0 0
0
0 1
1
1 0
1
1 1
0
DESIGN OF SEQUENTIAL CIRCUITS
The design of a synchronous sequential circuit starts from a set of specifications and
culminates in a logic diagram or a list of Boolean functions from which a logic diagram can
be obtained.
A synchronous sequential circuit is made up of flip-flops and combinational gates.
The design of the circuit consists of choosing the flip-flops and then finding the
combinational structure which, together with the flip-flops, produces a circuit that fulfils
the required specifications.
State Tables and State Diagrams
109
The relationship that exists among the inputs, outputs, present states and next states
can be specified by either the state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections
labeled present state, next state and output.
The present state designates the state of flip-flops before the occurrence of a clock
pulse.
The next state shows the states of flip-flops after the clock pulse, and the output
section lists the value of the output variables during the present state.
State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be
represented graphically by a state diagram.
In this diagram, a state is represented by a circle, and the transition between states is
indicated by directed lines (or arcs) connecting the circles.
An example of a state diagram is shown below.
The binary number inside each circle identifies the state the circle represents. The
directed lines are labeled with two binary numbers separated by a slash (/).
The input value that causes the state transition is labeled first. The number after the
slash symbol / gives the value of the output.
For example, the directed line from state 00 to 01 is labeled 1/0, meaning that, if the
sequential circuit is in a present state and the input is 1, then the next state is 01 and the
output is 0.
If it is in a present state 00 and the input is 0, it will remain in that state. A directed
line connecting a circle with itself indicates that no change of state occurs.
110
The state diagram provides exactly the same information as the state table and is
obtained directly from the state table.
EXAMPLE:
Design a synchronous sequential circuit whose
state diagram is shown below. The type of flipflop to be use is J-K.
STEP 1: STATE TABLE
Present State
Next State
x=0
x=1
00
00
01
01
10
01
10
10
11
11
11
00
Q0 Q1
Excitation table for JK flip-flop
Output Transitions
Flip-flop inputs
Q
JK
0
0
0 X
0
1
1 X
111
1
0
X 1
1
1
X 0
Excitation table of the circuit
Present State
Next State
Input
Q0 Q1
Q0 Q1
x
00
00
00
Flip-flop Inputs
J0K0
J1K1
0
0X
0X
01
1
0X
1X
01
10
0
1X
X1
01
01
1
0X
X0
10
10
0
X0
0X
10
11
1
X0
1X
11
11
0
X0
X0
11
00
1
X1
X1
The simplified Boolean functions for the combinational circuit can now be derived.
The input variables are Q0, Q1, and x; the outputs are the variables J0, K0, J1 and K1. The
information from the truth table is plotted on the Karnaugh maps
The flip-flop input functions are derived:
J0 = Q1*x'
K0 = Q1*x
J1 = x
The logic diagram
112
COUNTERS
DESIGN OF COUNTERS
A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a counter.
The input pulses, called count pulses, may be clock pulses. In a counter, the
sequence of states may follow a binary count or any other sequence of states.
Counters are found in almost all equipment containing digital logic. They are used
for counting the number of occurrences of an even and are useful for generating timing
sequences to control operations in a digital system.
A counter that follows the binary sequence is called a binary counter. An n-bit
binary counter consists of n flip-flops and can count in binary from 0 to 2n - 1.
Example
A counter is first described by a state diagram, which is a show the sequence of states
through which the counter advances when it is clocked.
State diagram of a 3-bit binary counter
113
The circuit has no inputs other than the clock pulse and no outputs other than its
internal state (outputs are taken off each flip-flop in the counter).
State table
Present State
Next State
Q2 Q1 Q0
Q2 Q1 Q0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
0 0 0
Excitation table
Output State Transitions
Present State
Next State
Q2 Q1 Q0
Q2 Q1 Q0
0 0 0
0 0 1
Flip-flop inputs
J2 K2
J1 K1
J0 K0
0X
0X
1X
114
0 0 1
0 1 0
0X
1X
X1
0 1 0
0 1 1
0X
X0
1X
0 1 1
1 0 0
1X
X1
X1
1 0 0
1 0 1
X0
0X
1X
1 0 1
1 1 0
X0
1X
X1
1 1 0
1 1 1
X0
X0
1X
1 1 1
0 0 0
X1
X1
X1
SIMPLIFICATION OF BOOLEAN EXPRESSION:
Simplified Boolean Expressions:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0
The complete logic of a 3-bit binary counter:
115
SYNCHRONOUS COUNTERS
A bit will toggle if all the low-order bits in the previous state are 1
 Flip-flops toggle at the same time - but only if J-K’s are high.
 J-K’s are formed by ANDing the output of the previous bits.
 Because the new output comes after the toggle by a few nanoseconds
 The new state is not involved in any of the inputs
 The AND gates are sampling the previous state.
 We are deliberately using to our advantage the gate delay time.
Shift Register Counters
There are two types of Shift Registers:
 Ring counter
 Johnson counter
RING COUNTERS:
116
A ring counter is basically a circulating shift register in which the output of the most
significant stage is fed back to the input of the least significant stage. The following is a 4-bit ring
counter constructed from D flip-flops
 Since the count sequence has 4 distinct states, the counter can be considered as a mod-4
counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient
in terms of state usage.
 But the major advantage of a ring counter over a binary counter is that it is self-decoding.
No extra decoding circuit is needed to determine what state the counter is in.
JOHNSON COUNTERS:
117
 Johnson counters are a variation of standard ring counters, with the inverted output of
the last stage fed back to the input of the first stage. They are also known as twisted ring
counters.
 An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered
to be a mod-2n counter. The state sequence for the counter is given in the table as well
as the animation on the left.
Analysis of Sequential Circuits
The behavior of a sequential circuit is determined from the inputs, the outputs and
the states of its flip-flops. Both the output and the next state are a function of the inputs and
the present state.
STEPS IN ANALYSIS OF SEQUENTIAL CIRCUITS:
118
Example: Derive the next state, the output table and the state diagram for the sequential
circuit shown below.
SOLUTION:
119
Excitation equations:
D0 = Cnt
Q0 = Cnt'*Q0 + Cnt*Q0'
D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
Next-state equations:
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'
Q1(next) = D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
Output equation:
Y = Q1Q0
As this equation shows, the output Y will equal to 1 when the counter is in state Q1Q0 =
11, and it will stay 1 as long as the counter stays in that state.
Next-state and output table:
Present State
Next State
Output
Cnt=0
Cnt=1
00
00
01
0
01
01
10
0
10
10
11
0
11
11
00
1
Q1 Q0
State diagram:
120
Z
Timing diagram:
The counter will
reach the state Q1Q0 = 11 only in the third clock cycle, so the output Y will equal 1 after
Q0 changes to 1. Since counting is disabled in the third clock cycle, the counter will stay in
the state Q1Q0 = 11 and Y will stay asserted in all succeeding clock cycles until counting is
enabled again.
SHIFT REGISTERS
 Register is a semiconductor device that is used for storing several bits of digital
data.
 Registers basically consists of a set of flip-flops. Thus, an n-bit register has n flipflops. A basic register is also known as a 'latch.'
 A special type of register, known as the shift register, is used to pass or transfer
bits of data from one flip-flop to another
 Clocking all the flip-flops at the same time will cause the bits of data to shift or
move to the right in one direction (i.e., toward the last flip-flop) .
A Simple Shift Register Consisting of D-type Flip-flops
Some forms of Shift Registers:
121





Serial In - Serial Out Shift Registers
Serial In - Parallel Out Shift Registers
Parallel In - Serial Out Shift Registers
Parallel In - Parallel Out Shift Registers
Bidirectional Shift Registers
Serial In - Serial Out Shift Registers
A basic four-bit shift register can be constructed using four D flip-flops, as shown below.
Operation of the circuit:
The register is first cleared, forcing all four outputs to zero. The input data is then applied
sequentially to the D input of the first flip-flop on the left (FF0).
During each clock pulse, one bit is transmitted from left to right. Assume a data word to
be 1001. The least significant bit of the data has to be shifted through the register from FF0 to
FF3.
Parallel In - Parallel Out Shift Registers
 For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits.
122
 The following circuit is a four-bit parallel in - parallel out shift register constructed by D
flip-flops.
 The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is
clocked, all the data at the D inputs appear at the corresponding Q outputs
simultaneously.
 Shift registers are used mostly to communicate with serial I/O devices. In general you find
these embedded inside UART's rather than as discrete circuits.
Serial to Parallel Converter:
 This register takes a serial data stream and converts it to a parallel data bus.
 The clock pulse would have to be synchronized to the data stream so that it toggles in the
middle of the data word.
 Every time the clock toggles, the data present at the input is clocked into the first flip-flop.
 Whatever was in the first flip-flop is latched into the second one. The third one becomes
equal to what the second one used to be.
Parallel to Serial Converter:
 This register takes a parallel data bus and converts it to serial data stream. It would most
likely be used to output data to a serial device.
123
 The Mode signal determines whether the register is loading the parallel data bus or
shifting the data out.
 When it is a "0", the register loads from the parallel bus. A "1" tells it to shift out. A logical
"0" is shifted into the register as each shift takes place.
 The clock pulse is used to latch the data from the parallel bus and to shift the data out. A
Multiplexer is used to send the correct data to the latches. The circuit is as follows:
Bidirectional Shift Registers
A bidirectional, or reversible, shift register is one in which the data can be shift either left or right.
Four-bit bidirectional shifts register using D flip-flops
124
Arithmetic Operation Using Shift Register: Multiplication by 2
 Multiplication can be done by shifting to the left.
 Higher powers of two can be done by shifting several times.
 An extra flip-flop can be added to the ends of the chain.
 In the case of division by 2, this flip-flop will contain the remainder.
 In the case of multiplication the flip-flop will flag whether an overflow has occurred.
HDL FOR SEQUENTIAL CIRCUITS:
4-bit binary counter
module counter4_bit(q, d, increment, load_data, global_reset, clock);
output [3:0]
q;
input [3:0] d;
input load_data, global_reset, clock, increment;
wire
t1, t2, t3; // internal wires
wire
see12, reset; // internal wires
125
et_ff etff0 (q[0], d[0], increment, load_data, reset, clock);
et_ff etff1 (q[1], d[1], t1, load_data, reset, clock);
et_ff etff2 (q[2], d[2], t2, load_data, reset, clock);
et_ff etff3 (q[3], d[3], t3, load_data, reset, clock);
and a1(t1, increment, q[0]); // increment signals are derived from the
and a2(t2, t1, q[1]);
// the previous increment signal by and-ing
and a3(t3, t2, q[2]);
// with the output form the previous
recog12 r1(see12, q);
// everytime the output changed this
or or1(reset, see12, global_reset); // reset to 0 if 'global_reset'
endmodule // counter4_bit
module et_ff(q, data, toggle, load_data, reset, clock);
output q;
input data, toggle, load_data, reset, clock;
wire
m1, m2;
mux mux0(m1, ~q, q, toggle);
mux mux1(m2, data, m1, load_data);
dff dff0(q, m2, reset, clock);
endmodule // et_ff
126
module mux(out, in1, in2, cntrl);
output out;
input in1, in2, cntrl;
assign out = cntrl ? in1 : in2;
// this is a continuous assignment so it is renewed everytime an
// operand changed. if (cntrl==1) out = in1, else out = in2.
endmodule // mux
module dff(q, data, reset, clock);
output q;
input data, reset, clock;
reg
q;
always @(posedge clock) // at every clock edge, if reset is 1, q is
if (reset == 1)
q = 0;
// reset to 0, else it is set to data, which
// as we said earlier can be either data, q or ~q
else q = data;
endmodule
module recog12(flag, in);
127
input [3:0] in;
output
flag;
assign flag = (in == 4'b1100) ? 1: 0;
endmodule // recog12
module stumulus;
wire [3:0] q;
reg [3:0] d;
reg
load_data, global_reset, clk, increment;
counter4_bit mod1 (q, d, increment, load_data, global_reset, clk);
initial begin
global_reset = 0;
clk = 0;
increment = 0;
load_data = 0;
d = 4'b0100;
#10 global_reset = 1;
#20 global_reset = 0;
#20 load_data = 1;
#20 load_data = 0;
#20 increment = 1;
#200 global_reset = 1;
#20 global_reset = 0;
#50 load_data = 1;
#20 load_data = 0;
128
#10 increment = 0;
#20 $finish;
end // initial begin
always #5 clk = ~clk;
always #10 $display ($time," %b %b %b %d -> %b %d",
increment, load_data, global_reset, d, q, q);
endmodule // stumulus
129
Unit V
ASYNCHRONOUS SEQUENTIAL CIRCUIT
Asynchronous Sequential Circuits
Do not use clock pulses. The change of internal state occurs when there is a change in the input
variable. Their memory elements are either unclocked flip-flops or time-delay elements.They often
resemble combinational circuits with feedback. Their synthesis is much more difficult than the
synthesis of clocked synchronous sequential circuits. They are used when speed of operation is
important. The communication of two units, with each unit having its own independent clock, must
be done with asynchronous circuits.
Analysis Procedure
The analysis of asynchronous sequential circuits proceeds in much the same way as that of
clocked synchronous sequential circuits. From a logic diagram, Boolean expressions are written
and then transferred into tabular form.
Transition Table
The analysis of the circuit starts by considering the excitation variables (Y1 and Y2) as outputs and
the secondary variables (y1 and y2) as inputs.
The Boolean expressions are:
Y1 xy1 x y 2
Y2 xy1 x y 2
The next step is to plot the Y1 and Y2 functions in a map:
Combining the binary values in corresponding squares the following transition table is obtained:
The transition table shows the value of Y = Y1Y2 inside each square. Those entries where Y = y
are circled to indicate a stable condition.
130
The circuit has four stable total states – y1y2x =
000, 011, 110, and 101 – and four unstable total
states – 001, 010, 111, and 100.
In order to obtain the circuit described by a flow
table, it is necessary to assign to each state a
distinct value.
The state table of the circuit is shown below:
This assignment converts the flow table into a
transition table. This is shown below:
This table provides the same information as the
transition table.
The resulting logic diagram is shown below:
1.2 Flow Table
In a flow table the states are named by letter
symbols. Examples of flow tables are as follows:
primitive flow table
The transition tables below illustrate critical races:
1.3 Race Conditions
A race condition exists in an asynchronous circuit
when two or more binary state variables change
value in response to a change in an input variable.
When unequal delays are encountered, a race
condition may cause the state variable to change
in an unpredictable manner.
If the final stable state that the circuit reaches
does not depend on the order in which the state
variables change, the race is called a noncritical
race. Examples of noncritical races are illustrated
in the transition tables below:
Races can be avoided by directing the circuit
through a unique sequence of intermediate
unstable states. When a circuit does that, it is said
to have a cycle. Examples of cycles are:
131
1.4 Stability Considerations
2. Circuits with SR Latches
An asynchronous sequential circuit may become
unstable and oscillate between unstable states
because of the presence of feedback. The
instability condition can be detected from the
transition table. Consider the following circuit:
The SR latch is used as a time-delay element in
asynchronous sequential circuits. The NOR gate
SR latch and its truth table are:
The excitation function is:
The feedback is more visible when the circuit is
redrawn as:
Y ( x1y )x2 ( x1 y )x2
x1x2 x2 y 
and the transition table for the circuit is:
The Boolean function of the output is:
Y [(S y )R ](S y )R SR R y
Those values of Y that are equal to y are circled
and represent stable states. When the input x1x2 is
11, the state variable alternates between 0 and 1
indefinitely.
and the transition table for the circuit is:
The NAND gate SR latch and its truth table are:
The behaviour of the SR latch can be investigated
from the transition table.
The condition to be avoided is that both S and R
inputs must not be 1 simultaneously. This condition
is avoided when SR = 0 (i.e., ANDing of S and R
must always result in 0).
The transition table for the circuit is:
When SR = 0 holds at all times, the excitation
function derived previously:
Y SR R y
can be expressed as:
Y S R y
132
The condition to be avoided here is that both S
and R not be 0 simultaneously which is satisfied
when S′R′ = 0.
The excitation function for the circuit is:
Y [S(Ry )]S Ry
The next step is to derive the transition table of the
circuit. The excitation functions are derived from
the relation Y = S + R′y as:
2.1 Analysis Example
Consider the following circuit:
Y1 S1
R1y1
x1y 2 ( x1 x 2 )y1 x1y 2 x1y1 x 2 y1
Y2 S2 R2 y
2 x1x 2 ( x 2 y1 )y 2 x1x 2
x 2 y 2 y1y 2
Next a composite map for Y = Y1Y2 is developed:
The first step is to obtain the Boolean functions for
the S and R inputs in each latch:
S1 x1y 2
S2 x1x 2
R1 x1x 2
R2 x 2 y 1
Investigation of the transition table reveals that the
circuit is stable.
The next step is to check if SR = 0 is satisfied:
There is a critical race condition when the circuit is
initially in total state y1y2x1x2 = 1101 and x2
changes from 1 to 0. If Y1 changes to 0 before Y2,
the circuit goes to total state 0100 instead of 0000.
S1R1 x1y 2 x1x
2 0
S2R2 x1x 2 x 2
The result is 0 because
y1 0 x1x′1 = x2x′2 = 0
2.2 SR Latch Excitation Table
Lists the required inputs S and R for each of the
possible transitions from the secondary variable y
to the excitation variable Y.
X represents a don’t care condition.
The maps are then used to derive the simplified
Boolean functions:
S x1x 2 R x1
Useful for obtaining the Boolean functions for S
and R and the circuit’s logic diagram from a given
transition table.
The logic diagram consists of an SR latch and
gates required to implement the S and R Boolean
functions. The circuit when a NOR SR latch is used
is as shown below:
2.3 Implementation Example
Consider the following transition table:
Y x1x2 x1y
From the information given in the transition table
and the SR latch excitation table, we can obtain
maps for the S and R inputs of the latch:
133
With a NAND SR latch the complemented values
for S and R must be used.
3. Design Procedure
3.1 Design Example – Specification
Design a gated latch circuit with two inputs, G
(gate) and D (data), and one output Q. The gated
latch is a memory element that accepts the value
of D when G = 1 and retains this value after G
goes to 0. Once G = 0, a change in D does not
change the value of the output Q.
There are a number of steps that must be carried
out in order to minimize the circuit complexity and
to produce a stable circuit without critical races.
Briefly, the design steps are as follows:
1.
Obtain a primitive flow table from the given
specification.
2.
Reduce the flow table by merging rows in
the primitive flow table.
3.
Assign binary states variables to each row of
the reduced flow table to obtain the
transition table.
4.
Assign output values to the dashes
associated with the unstable states to obtain
the output maps.
5.
Simplify the Boolean functions of the
excitation and output variables and draw the
logic diagram.
Step 1: Primitive Flow Table
A primitive flow table is a flow table with only one
stable total state in each row. The total state
consists of the internal state combined with the
input.
To derive the primitive flow table, first a table with
all possible total states in the system is needed:
The design process will be demonstrated by going
through a specific example:
Each row in the above table specifies a total state.
The resulting primitive table for the gated latch is
shown below:
Step 2: Reduction of the Primitive Flow Table
The primitive flow table can be reduced to a
smaller number of rows if two or more stable
states are placed in the same row of the flow
table. The simplified merging rules are as follows:
1.
Two or more rows in the primitive flow table
can be merged into one if there are nonconflicting states and outputs in each of the
columns.
2.
Whenever, one state symbol and don’t care
entries are encountered in the same column,
the state is listed in the merged row.
First, we fill in one square in each row belonging to
the stable state in that row.
3.
If the state is circled in one of the rows, it is
also circled in the merged row.
Next recalling that both inputs are not allowed to
change at the same time, we enter dash marks in
each row that differs in two or more variables from
the input variables associated with the stable state.
4.
The output state is included with each stable
state in the merged row.
Next we find values for two more squares in each
row. The comments listed in the previous table
may help in deriving the necessary information.
A dash indicates don’t care conditions.
Now apply these rules to the primitive flow table
shown previously.
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To see how this is done the primitive flow table is
separated into two parts of three rows each:
The circuit has four stable total states – y1y2x =
000, 011, 110, and 101 – and four unstable total
states – 001, 010, 111, and 100.
In order to obtain the circuit described by a flow
table, it is necessary to assign to each state a
distinct value.
This assignment converts the flow table into a
transition table. This is shown below:
The state table of the circuit is shown below:
This table provides the same information as the
transition table.
1.2 Flow Table
The resulting logic diagram is shown below:
In a flow table the states are named by letter
symbols. Examples of flow tables are as follows:
primitive flow table
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