RECONFIGURABLE NOVEL INTEGRATED ANALOGUE COMPUTING CELL (RENIAC)
1.
TRACK RECORD
The applicant and host institution, the University of Cambridge (Department of Engineering) have expertise
and facilities in an extensive range of activities linked to this proposal. The applicant, Dr David Holburn is a
Senior Lecturer in Engineering at Cambridge, and has over twenty years experience in electronic and
microelectronic design. He has been responsible for the development of Cambridge University Engineering
Department's programme of undergraduate and postgraduate IC design projects and currently serves as
representative for the Europractice microelectronics initiative, of which the University is a full member. This
has led to the accumulation of valuable skill and experience in the acquisition and use of industry-strength
computer-aided design tools and of access to semiconductor foundry services.
The applicant and his research group have worked successfully over a number of years in a number of projects
involving full-custom mixed-signal silicon design for a range of applications including optoelectronics, RF and
optical communications.
These include a wide variety of sub-micron CMOS technologies for digital and analogue circuits, including flipchip, and the group has a strong track record in submitting designs for fabrication and evaluating them using a
wide range of test equipment available within the Department. Novel devices successfully fabricated have
included low-noise wideband CMOS receivers and transmitters [1, 2, 3] and flip-chip integrated versions of
these [4] (under EPSRC GR/M29573/01), arithmetic and diversity reception circuits [5], transducer interface
circuits [6], driver circuits for resonant cavity LEDs [7] and laser devices [8] for operation at up to 2.5Gb/s
(under EPSRC GR/R32802/01). The broad experience gained in a wide range of linked technologies will
provide a valuable foundation for the proposal detailed here.
Secondly, the applicant has experience in the development of high performance demountable IC interconnect
systems for versatile electronic systems. Feasibility studies carried out with support from industry have already
established the viability of a demountable modular 3D stacking architecture, based on the use of a substrate with
contacts on its upper and lower surfaces, for the development of versatile electronic systems. The complex
three-dimensional routing possibilities created by this simple modification are the key to the power and
flexibility of this approach. Layers are then simply clipped together using carriers equipped with miniature
latches to form a complete system; compression of the connectors completes mechanical latching and
establishes electrical interconnection of all the carriers in the system. This is believed to offer considerable
promise for implementation of massively parallel processor and other complex analogue or digital systems,
possibly making use of short-range free-space optical links. The applicant was a co-recipient of a DTI SMART
award to demonstrate the feasibility of constructing a modular embedded PC using this technology. The
resultant product occupies under 60 cm3, can readily be dismantled, its circuitry re-used or remanufactured, and
it runs standard PC software. This Demonstrator has been the object of widespread interest [11]. Since this
work was undertaken, advances in IC technology have progressively converged to encourage further
development of this approach.
Further, the applicant and his group have been engaged in the development of circuitry and software for signal
and image processing, for electron microscopy and for medical instrumentation [9, 10].
The researcher
nominated for the studentship has valuable skills in IC design and in the development of novel computer
architectures and microprocessors suitable for embedded computing systems.
Within the Engineering Department there is excellent support for circuit design and fabrication, mechanical
design and manufacture, and strong academic expertise in signal processing, CFD, mathematics and control
engineering.
References
[1]
"Development of a CMOS 310Mb/s receiver for free space optical wireless links", Lalithambika, V.A.,
Joyner, V.M., Holburn, D.M., Mears, R.J. in Optical Wireless Communications III, Eric J. Korevaar, Editor,
Proceedings of SPIE Vol. 4214 (Feb 2001), pp 133-143.
[2]
"A CMOS 155 MB/s optical wireless transmitter for indoor networks", Holburn, D.M., Mears, R.J.,
Samsudin, Joyner, V.M., Lalithambika, V.A. in Optical Wireless Communications III, Eric J. Korevaar, Editor,
Proceedings of SPIE Vol. 4214 (Feb 2001), pp 124-132.
[3]
"An integrated CMOS transceiver for indoor optical wireless links", Holburn, D.M., Lalithambika, V.A.,
Joyner, V.M., Samsudin, Mears, R.J., in Optical Wireless Communications IV, Eric J. Korevaar, Editor,
Proceedings of SPIE Vol. 4530 (2001), pp 154-159.
[4]
"Flip-chip integrated optical wireless transceivers", O’Brien, D.C., Faulkner, G.E., Zyambo, E.B.,
Edwards, D.J., Stavrinou, P., Parry, G., Bellon, J., Sibley, M.J., Lalithambika, V.A., Joyner, V.M., Samsudin,
R., Holburn, D.M., Mears, R.J., in Optical Wireless Communications V, Eric J. Korevaar, Editor, Proceedings of
SPIE Vol. 4873 (Dec 2002), pp 23-29.
[5]
"Integrated CMOS transmitter driver and diversity receiver for indoor optical wireless links", Holburn,
D.M., Lalithambika, V.A., Samsudin, R. J., Joyner, V.M., Mears, R.J., in Optical Wireless Communications IV,
Eric J. Korevaar, Editor, Proceedings of SPIE Vol. 4873 (Dec 2002), pp 13-22.
[6]
"A closely integrated digital image capture device for embedded applications", D S Jordan and D M
Holburn; paper presented at Europto International Symposium on Advanced Imaging and Network
Technologies, 7-11 Oct 1996, Berlin.
[7]
"A 2.5Gb/s Low-Power CMOS VCSEL Transmitter with Clipping Distortion Suppression for Analogue
Optical Fibre Data Links", Lin, Fu-Chuan, Lalithambika, V. A., Holburn, D. M., and Mears, R. J., in
Proceedings of The 5th International Conference on ASIC, Beijing, China, October 2003.
[8]
"Fully integrated CMOS VCSEL driver with nonlinearity suppression for RF optical fibre links", Lin,
Fu-Chuan, Lalithambika, V. A., Holburn, D. M., Mears, R. J., Hum, C. H. and Walker, S. D., in Proceedings of
SPIE Vol. 5356, Optoelectronic Integrated Circuits VI; Louay A. Eldada; Ed., pp. 56-64. Publication date: Jun
2004
[9]
"Sharpness search algorithms for automatic focusing in the scanning electron microscope", Batten, C.F.,
Holburn, D.M., Breton, B.C. and Caldwell, N.H.M., in Scanning, Vol. 23 No. 2, March-April 2001. Proceedings
of SCANNING 2001, pp 112.
[10] "A combined heart rate and movement sensor: proof of concept and preliminary testing study", Rennie,
K., Rowsell, T., Holburn D.M. and Wareham, N.J. in European Journal of Clinical Nutrition, May 2000, 54, pp
409-414.
[11] "Chiprack: A novel architecture to facilitate disassembly and reuse of electronic components and subassemblies", D M Holburn, M Anstey, D S Jordan & C E Hawkins, Proceedings of the 1st International
Conference on Clean Electronics Products and Technology, pp 214-217, October 1995, Edinburgh.
[12] "A Low-Bounce Adaptive CMOS Output Buffer for 310Mb/s Optical Wireless Receiver", Lin, FuChuan, Lalithambika, V. A., Holburn, D. M., and Mears, R. J, in Proceedings of XVIII Conference on Design of
Circuits and Integrated Systems, Ciudad Real, Spain, November 2003.
2.
CASE FOR SUPPORT
2.1
INTRODUCTION
There are considerable attractions in applying to the field of Analogue Computing several of the process
advances and design methodologies that have been so successfully applied to other applications of
microelectronics. Analogue computing has advanced little since the 1960’s when it was eclipsed by the
burgeoning advances in digital computing. Arguably these are now slowing, and it is now timely to consider
other alternative and complementary approaches to computing. This proposal aims to demonstrate these
possibilities, and to investigate methods of achieving configurable integrated analogue processing elements.
The potential benefits are substantial and include true real-time, high speed computation, massive parallel
computing, and low cost of implementation and operation.
The classic analogue computer, is the General Purpose Analogue Computer (GPAC) as proposed by Claude
Shannon [SHA41], with the differential analyzer as its prime specimen.. In 1993, Rubel, proposed a model for
analogue computers called the Extended Analogue Computer (EAC) [RUB93] after showing that GPAC, had
very real mathematical limitations that prohibit its use in general computing [RUB88]. For one, GPACs are
unable to solve partial differential equations and required different techniques that were illustrated elsewhere
[KAR59]. It is recognized that extensions to the GPAC are needed in order to make generic analogue computers
a reality [GRA02]. The EAC model, extended the GPAC, and is suitable as a model for general purpose
analogue computing, but it is still not clear if the EAC can be realised completely [CMC00]. A fast electronic
PDE solver, which is an important component of the EAC has been realised in VLSI [MIL95].
Analogue computing has been described by some as a ‘dead science’. In the 1960s there were heated debates on
whether analogue or digital was better. Ultimately, analogue lost owing primarily to cost as digital computers
were cheap to produce and adapt from one application to another by merely changing the software, while
analogue computers were traditionally one-shot and cumbersome to modify. Moore's Law ensured continuous
digital dominance, but has rapidly pushed up it against fundamental physical limits.
Analogue electronic computers enjoyed little more than a decade of popularity. It was therefore, still in its
infancy, and suffered a retarded development when digital computing took over. In a twist, it is now possible to
exploit advanced digital technology to build analogue circuits, due to the spur of RF technology. Analogue
computing, can now be given due consideration as an alternative form of computing that can be used to provide
results of great potential value in future applications.
Today, analogue computers find niche applications that are ‘difficult’ for digital computers: for example, the
exploration of Chaos [ES99] and Artificial Intelligence [ML99]. EACs are now being considered for a broader
range of applications [MIL03] including internet traffic routing & QoS, target recognition, protein folding,
neurobiological modelling, gait generation, evolution of galactic structure, and self-evolving reconfigurable
hardware.
Our research proposes to design and build a programmable analogue computing cell in CMOS VLSI while
addressing the fundamental challenges faced by analogue computing. We will study and exploit various
techniques and technologies available today such as field resistance, floating gate- and translinear devices.
Methods will be developed for interconnecting computing cells in configurable clusters, to perform computing
functions. Some applications that we will explore include the areas of MRI, aerospace and MEMS.
2.1.1
ADVANTAGES OF ANALOGUE COMPUTING

True real-time computation: Outputs are calculated on changes to input in real-time. Also able to perform
parallel computations by simultaneously manipulating the different electrical properties such as amplitude,
frequency and phase.

High speed computation: Analogue computers only need to work at the speeds of the inputs they are
manipulating. Digital computers need to work several times faster than the inputs they are manipulating
owing to sampling and quantisation processes.

Massive parallel computing: Analogue computers do not have the same performance bottlenecks as digital
computers when they are parallelised. Their non-sequential architecture lends well to parallel computing.

Low cost: Analogue computing circuits are simpler and directly translate into cost savings in terms of
smaller circuit size (higher yield), lower power consumption (lower system cost) and better performance
(computations/watt) using comparable digital technology.
2.1.2
CHALLENGES OF ANALOGUE COMPUTING

Specificity of purpose: Analogue computers are typically ‘one-shot’ computers developed for a specific
purpose only and are expensive to maintain and modify. Software and hardware are traditionally separate
and cumbersome to implement.
Solution: Integrating software and hardware, programmable for different functions.

Resilience to process change: Traditionally poor. Analogue circuits have to be redesigned for each and
every application for which they are required do not benefit substantially from design reuse.
Solution: Programmable analogue software upgrades to improve functions.

Accuracy: Typically capable of producing results that are within 0.05% of the actual value. Also known to
be imprecise. Note that quantisation noise and sampling effects also set a clear limit to the accuracy that can
be achieved by digital means. Analogue computers may sacrifice accuracy for speed.
Solution: Enhancements in accuracy and stability by judicious use of modern circuit design techniques; use
of embedded digital hardware to facilitate calibration and dynamic adjustments to improve accuracy and
precision.
2.2
PROGRAMME & METHODOLOGY
2.2.1
OBJECTIVES

To evaluate a novel architecture for an integrated analogue computing cell based on high performance
floating-gate CMOS devices

To develop a novel integrated switching fabric to support reconfiguration of the analogue cell

To show the feasibility of dynamically reconfiguring the analogue cell to allow it to perform multiple
operations

To demonstrate that a number of programmable cells of this kind may be organised as an arrayed computing
entity that can be used to solve complex mathematical functions.

To show how these cells can be combined into a massively parallel computing system that can be applied to
complicated multi-dimensional computations and applications.

To identify and explore new applications that will benefit from the incorporation of integrated analogue
computing elements

To develop human capital in the re-emerging field of analogue computing.
2.2.2
INTEGRATED ANALOGUE COMPUTING CELL
Our definition of analogue computing is the process of computing in an analogous fashion, i.e. using natural
electrical properties to compute. The values can be both discrete and continuous. The computing functions
include but are not limited to, summation, differentiation, integration, multiplication and logical functions.
The research will commence with an evaluation of the best available IC technologies. For example:

For the cell, we will investigate the use of suitable techniques to solve multi-dimensional problems including
novel methods such as using field resistance and trans-linear circuits elements. A floating-gate transistor
(FGMOS) can be readily used as a memory, switch, resistor and capacitor element. Combining these will
allow us to create various finite difference networks for solving PDEs. We will investigate what other
valuable functions we can build with these.

For the switching fabric, we will investigate hybrid techniques such as nearest-neighbour combined with
short and medium length transmission lines. Besides serving as data paths, these lines also serve as summing
junctions for additions and subtractions.

For the test structure we will investigate the use of external field-programmed devices to perform the
complex signalling necessary to program the device. External memory may be required to store
configuration elements and data. External data converters will be required for I/O purposes in order to
interface the chip with existing digital equipment/peripherals.

For applications, we will identify and build a number of highly parallel and compute-intensive applications
on the analogue processor in order to assess its feasibility as a general purpose computing platform. We will
identify suitable benchmarks for measuring its performance, since MIPS/MFLOPS do not seem particularly
apt.
2.2.3
ARRAYS OF ANALOGUE COMPUTING CELLS
The device we ultimately envision will in one sense resemble a multi-processor system, with many individual
computing cells interconnected via a communication data path that is linked externally via suitable input/output
converters. However, instead of a microprocessor, each cell is a stand-alone, reconfigurable, analogue
computer. Each cell stores its own program in memory which serves to configure it for a specific function. The
necessary programs will be compiled on a digital computer with special compilers and downloaded onto the
device, so determining the behaviour of each cell, the function it provides and the way it interacts with other
cells and external signals. The concept of such an analogue computing element is itself believed to be entirely
novel; however, we seek in addition to integrate multiple cells in a manner not previously attempted. In this
sense, it will be resemble a Field Programmable Gate Array (FPGA) or a Field Programmable Analogue Array
(FPAA), though based on a fundamentally different processing element, developed specifically to meet the
requirements of analogue computing. The programmable chip will be suited for building advanced computing
functions and to model complicated mathematical and real world systems in real time. It is expected that
systems based upon it will be capable of being scaled in 2 or 3 dimensions to implement still more elaborate
multi-dimensional systems. Such a multi-dimensional system will take full advantage of available modular 3D
electronic stacking systems.
Illustration 1: Proposed device structure
2.2.3
TIMELINESS & MEASURABLES
For a detailed plan of the project, please refer to the Gantt chart attached at the end of the document. The project
is expected to see real world benefits with future applications within the medium term to long term, as digital
computers come closer to their physical limits. Taking advantage of advances in microelectronic processing and
design methodologies, we expect to address many of the problems that plagued analogue computers in the past
and to build in capabilities that could not be contemplated even a few years ago. The duration of the project will
allow us to design and build a prototype programmable arrayed analogue computing chip with supporting
software and hardware in order to program it. It is expected that a demonstrator will also be developed to allow
direct comparison with current computing solutions.
The project will generate both soft and hard measurables. Hard measurables including the software, chips and
boards that will be built and any applications that are developed on it. The soft measurables will include patents
and generated knowledge that may be shared publicly. The schedule for these deliverables are noted in the chart
as “Delivery” and coincide with the schedule for chip fabrication.
2.3
BENEFICIARIES
2.3.1
ACADEMIC RESEARCH
Analogue computing cells will facilitate a wider range of mathematical and logical functions, allowing
researchers to solve a wider range of problems and to model a wider range of systems. Analogue computing will
become general purpose and can fully complement digital computing in high speed scientific applications such
as fast computation, simulation, and modelling for research purposes.
Programmable analogue cells will bring the benefits of reusable intellectual property (IP) similar to the concept
of reusable software libraries and reusable digital cores. This will encourage the sharing of resources for
academic and economic purposes to accelerate the development of useful devices.
There is an emerging trend of using analogue computing in the fields of neural networks, fuzzy logic and other
areas of research. The ability of analogue computing to perform massively parallel computations at once, lends
itself well to the creation of huge arrays of cognitive/intelligent systems.
2.3.2
COMMERCIAL INDUSTRY (Signal Processing/Cognitive Systems)
Virtually all analogue front ends provide signal processing functions using analogue computing techniques. Any
change in specification typically requires a complete redesign of the entire analogue front end. Programmable
analogue front ends with intrinsic computing capabilities can be used in different regions with different
regulatory systems. This shortens commercial design and implementation cycles.
On-the-fly programming allows devices to perform different functions based on need, offering savings in chip
resources and power. Also, analogue systems will run faster while consuming less power and space than
comparable digital systems. This is expected to lead to improvements in consumer electronics, especially in
portable multimedia and communication devices as image and audio processing techniques are inherently
analogue in nature.
MEMS are now well established and offer enormous potential for the development of miniaturised machines
and mechanisms for a vast range of tasks. Such devices are expected to require elaborate control systems. The
small size of analogue circuits envisioned here would allow high performance control systems to be placed in
close integration with the MEMS devices. Analogue computers would be able to drive these machines based on
inputs directly received, once more using analogue computers for their original primary purpose.
2.3.3
GENERAL PUBLIC (Health/Medical/Biological)
The massively parallel nature of analogue computing lends itself well for applications such as real-time, high
speed MRI/NMRI and ultra sound scanning that require massive amounts of computations. At the moment, even
the best scanning machines using the fastest computers available still suffer from a lack of computing speed due
to the massive amount of complicated computation required. Similar considerations apply to meteorology and
forecasting; the availability of high performance analogue computing elements is likely to give direct benefits
here.
Analogue computing can be used to build models of biological mimicry to drive other devices. Better artificial
limbs can be designed to mimic natural human movements accurately and interface better with human systems.
This can be applied to enhance prosthetic devices as well as to build robots that are more articulate. Artificial
limbs that perform as well as or better than their original limbs will change the lives of the disabled everywhere.
2.4
EXPLOITATION & DISSEMINATION
2.4.1
PUBLICATION/PATENT
We will actively publish our work in printed journals/magazines as well as at relevant conferences to open our
research to peer review, as well as gather input from research done elsewhere in this world. We expect that this
work will give rise to novel devices, and will work in close conjunction with the University’s Technology
Transfer Office to protect any IP arising from this research. We will build a website in order to make the key
features of our work publicly available. The website will serve as a repository for publications and also other
relevant materials including design files, simulation and test results. It can also serve as a focal point for
discussion and active participation from other interested parties to hopefully spur application development and
improvements on our platform. We will investigate the possibility of developing an animated multimedia
representation of the target design for publication on the web site. Subject to IP issues, we expect to compile a
development kit to include the necessary software and hardware to allow interested parties to build
programmable analogue computing applications and devices based on our devices.
2.5
JUSTIFICATION OF RESOURCES
2.5.1
CHIP FABRICATION
It is anticipated that two sequential rounds of IC manufacture will be called for. Initially, foundry services will
be required to manufacture test structure devices designed to show feasibility of the basic analogue computing
device and switching fabrics, and to validate models. The resultant devices are expected to demonstrate
functionality and reconfigurability of a basic cell. A second phase of fabrication will be used to manufacture a
chip that has interconnected cells and will be used to investigate computational operations based on
communicating cells, including parallel operation.
2.5.2
TEST TOOLS AND DEVELOPMENT SOFTWARE
Custom circuit boards with additional circuit components will need to be designed and constructed to serve as
test jigs. Some of the additional circuit components needed would probably include external FPGA, FPAA,
along with D/A and A/D converters. Also, specialised test equipment will either need to be rented to conduct the
necessary tests. Industrial-strength electronic CAD tools for full-custom design and verification will be
required to undertake the complex IC design operations. Accordingly a dedicated licence for Cadence IC design
tools is requested, together with the recurrent costs to maintain this suite, and a PC design workstation suitable
for IC CAD work, in conjunction with a department server. We expect to build the necessary software and
hardware development tools to undertake application research. This includes software compilers as well as
development hardware. The development tools will be used to build complete system prototypes that will be
integrated in real-world applications to illustrate the proper use of a general purpose analogue computer. We can
then perform benchmarking and comparison between analogue and digital computing performances.
2.5.3
STUDENTSHIP AND STAFF
A full-time three-year research studentship is sought for this investigation. The student proposed for this
application offers skills in IC design as well as embedded systems and microprocessor architectures. There
exists the possibility that during the course of this investigation other avenues may open up, calling for
additional projects to be undertaken. These would be the subject of further applications. We anticipate that a
number of Master’s students will undertake one-year projects that will add significant value to this investigation,
and will be potential applicants for future research posts. A 10% share in an experienced Computer Officer is
sought. We anticipate the need for significant reconfiguration and adaptation of CAD design tools as well as
installation and maintenance of a range of foundry design kits. The nominated staff member has considerable
experience of this kind of work. A 10% share in an (unnamed) administrative secretarial assistant is sought, for
assistance with web site maintenance, publications and project administration.
2.6
REFERENCES
[CMC00]
M L Campagnolo, C Moore, J F Costa; Iteration, Inequalities, and Differentiability in Analog
Computers; Journal of Complexity 16(4); 2000; p642-660.
[EL99]
B J MacLennan; Field Computation in Natural & Artificial Intelligence; University of
Tennessee Technical Report UT-CS-99-442; 1999.
[ES99]
A S Elwakil, A M Soliman; Current Conveyor Chaos Generators; IEEE Transactions on
Circuits & Systems I Vol 46 No 3; 1999; p393-398.
[GRA02]
2002.
D d S Graca; The General Purpose Analog Computer and Recursive Functions over the Reals;
[KAR59]
Edition; 1959;
W J Karplus, W W Soroka; Analog Methods Computation and Simulation; McGraw-Hill; 2nd
[MIL03]
2003.
J Mills; High Performance Polymer Processor; Second Workshop on Non-Silicon Computing;
[MIL95]
J Mills; Programmable VLSI Extended Analog Computer for Cyclotron Beam Control;
Indiana University Computer Science Technical Report 441; 1995.
[RUB93]
p39-50.
L A Rubel; The Extended Analog Computer; Advances in Applied Mathematics 14; 1993;
[RUB88]
L A Rubel; Some Mathematical Limitations of the General Purpose Analog Computer;
Advances in Applied Mathematics 9; 1998; p22-34.
[SHA41]
p337-354.
C Shannon; Mathematical Theory of the Differential Analyzer; J. Math. Phys. MIT 20; 1941;