John J. Granacki, Ph.D. 38 Rollingwood Drive Rolling Hills Estates, CA 90274 (310) 378-3383 granacki@isi.edu Education University of Southern California, Los Angeles, California Ph.D., Electrical Engineering, November 1986 Major Field: Computer Engineering Minor Field: Computer Science Dissertation: Understanding Digital System Specifications Written in Natural Language University of Southern California, Los Angeles, California Engineer Degree, Electrical Engineering, May 1982 Major Field: Computer Engineering Minor Field: Solid State Science Drexel University, Philadelphia, Pennsylvania M.S., Physics, May 1970 Rutgers University, New Brunswick, New Jersey B.A., Physics, June 1968 Honors Hughes Engineer Fellowship “Best Minds, Best Ideas” Award, EE Times Research Focus Expertise in systems, high performance embedded-computing systems, micro-power embedded real-time computing systems, VLSI and Systems on a Chip and wireless systems. Major research themes include advanced computer architectures, many-core processors, distributed memory systems and bio-inspired architectures. Potential applications: biomedical prostheses and devices, military systems and sensor networks Appointments Director Advanced Systems, USC Information Sciences Institute, 2010-present Division Director, USC Information Sciences Institute, 1993-2010 Research Associate Professor of Electrical Engineering Systems and Biomedical Engineering, University of Southern California, 2003-present Technology Thrust Leader, Mixed-Signal Systems on a Chip, BMES (Biomimetic MicroElectronic Systems) Engineering Research Center, 2003-present Associate Director, CiSoft (Center for interactive Smart oilfield technology), 2006-2009 Research Assistant Professor of Electrical Engineering-Systems, University of Southern California, 1993-2003 Project Leader, USC Information Sciences Institute, 1989-1993 Research Computer Scientist, USC Information Sciences Institute, 1988-1989 Research Scientist, The Aerospace Corporation, El Segundo, CA, 1987-1988 Senior Scientist, Hughes Aircraft Company, El Segundo, CA, 1981-1987 Senior Staff Engineer, Hughes Aircraft Company, El Segundo, CA, 1977-1981 Member of the Technical Staff, RCA Solid State Division, Somerville, NJ, 1970-1977 Professional Experience USC Information Sciences Institute 4676 Admiralty Way Marina del Rey, CA 90292-6695 Computational Science and Technology Group Director Advanced Systems 4/2010 to present Research Associate Professor, Electrical Engineering Systems and Biomedical Engineering Dr. Granacki is a Co-Principal Investigator on the DARPA-sponsored REMIND project that is developing a hippocampal prosthesis for demonstration in nonhuman primates. Dr.Granacki is continuing in his role in the BMES (Biomimetic Microelectronics Systems( ERC (Engineering Research Center) as the Thrust Leader for Mixed-Signal Systems on a Chip. Dr. Granacki also leads research efforts in VLSI Microsystems, Collaborative Computing, the Space Engineering Research Center, and a STEM-CoOp Program focused on the Intelligence Community. Advanced Systems Division Division Director 11/1993 to 45/2010 Research Associate Professor, Electrical Engineering Systems and Biomedical Engineering Led a multidisciplinary research staff of more than twenty-six people, including four Ph.D.s and seven graduate research assistants, in developing advanced high performance computing systems. Dr. Granacki was the Principal or Co-Principal Investigator on several major research efforts including: the DARPA-sponsored Brain-Implantable Biomimetic Electronics for Restoration and Augmentation of Cognitive Function that has successfully replaced the biological CA3 subregion of the hippocampus of a rat-brain slice with an FPGA/VLSI-based model of the nonlinear dynamics of CA3, such that the propagation of spatio-temporal patterns of activity from dentateVLSI modelCA1 reproduces that observed experimentally in the biological dentateCA3CA1 circuit; the DARPA-sponsored MONARCH (Micro-Networked ARCHitecture) Project that is developed a new hybrid architecture that can efficiently process stream-based and thread-based applications; NSF ANISE (Architectures for Neuromimetic Information System Engineering) grant that researched biologically-realistic neural circuits for pattern-matching applications and new “biologically-inspired” computer architectures; the DARPA-sponsored DIVA (Data IntensiVe Architecture) Project that demonstrated the effectiveness of PIM technology in ameliorating the traditional processor-memory bottleneck and also the capability to speed-up irregular applications; the DARPA-sponsored DEFACTO (Design Environment For Adaptive Computing TechnOlogy) Project that has demonstrated the use of high-level parallel-compiler techniques and area estimation techniques to automatically synthesize board-level FPGA-based systems. The Center for Grid Technology in the Advanced Systems Division was recognized as a worldwide leader in this area. As a Research Assistant and Research Associate Professor, Dr. Granacki served on several Qualification/Dissertation Committees and supervised both Masters and Ph.D. Directed Research in Computer Architecture, Design Automation, Grid Technology and VLSI. Dr. Granacki also served on the Recruitment Committee for Computer Architecture and as a representative of EESystems and ISI to the Bio Technology Initiative Working Group. Advanced Systems Division Project Leader 10/89 to 10/93 Established the ARPA-sponsored Systems Assembly Project, an automated system enabled system architects with limited fabrication experience to build systems and to validate their architectural concepts. The Systems Assembly Project integrated commercial off-the-shelf and university-developed computer-aided design tools into an automated system that accepted highlevel descriptions (e.g., a register-transfer language specification) and produced the necessary data for fabricating and assembling the ASICs, multichip modules and printed circuit boards. The tools developed as part of the System Assembly Project synthesized subsystems, for example, memories and bus controllers using table-based descriptions and expert system technology based on CMU's MICON system. Sophisticated statistical-based models were developed to predict routability of packaging substrates and allow rapid iteration of design layouts. Intelligent Systems Division Research Computer Scientist 1/88 to 9/89 Developed a tool to aid expert systems users who need to perform extended tasks. The research in this area was incorporated into the DRAMA (Data Review Analysis and Monitoring Aid) System under a DARPA program funded by the Defense Logistics Agency. The tools developed as part of the DRAMA effort are generic tools for time management, prioritization, and scheduling with application to other domains. These tools allow system developers to include facilities for activity tracking and management in other systems with a minimum of software development. These tools included: a domain-independent interpreter of application-specific declarations describing extended tasks; scenarios, a language in which declarations are expressed; agendas, an interface for recording goals and tasks in a form interpretable by both system and user. These tools support the interleaving of a user’s activities over many days, weeks, or even months. The underlying mechanism ensures the proper handling of contingencies within each activity and across activities. Publications Journals: Berger, T.W.; Dong Song; Chan, R.H.M.; Dae Shin; Marmarelis, V.Z.; Hampson, R.E.; Sweatt, A.J.; Heck, C.N.; Liu, C.Y.; Wills, J.; LaCoss, J.; Granacki, J.J.; Gerhardt, G.A.; Deadwyler, S.A., "Role of the Hippocampus in Memory Formation : Restorative Encoding Memory Integration Neural Device As a Cognitive Neural Prosthesis," Pulse, IEEE , vol.3, no.5, pp.17-22, Sept. 2012 Theodore W. Berger, Fellow, IEEE, Dong Song, Member, IEEE, Rosa H. M. Chan, Student Member, IEEE, Vasilis Z. Marmarelis, Fellow, IEEE, Jeff LaCoss, Member, IEEE, Jack Wills, Robert E. Hampson, Member, IEEE, Sam A. Deadwyler, Member, IEEE, and John J. Granacki, Senior Member, IEEE, “A Hippocampal Cognitive Prosthesis: Multi-Input, Multi-Output Nonlinear Modeling and VLSI Implementation” in IEEE Transactions On Neural Systems And Rehabilitation Engineering, Vol. 20, No. 2, March 2012 Wentai Liu, Mohanasankar Sivaprakasam, Guoxing Wang, Mingcui Zhou, John Granacki, Jeff LaCoss and Jack Wills, "Implantable Biomimetic Microelectronic Systems Design, IEEE Engineering in Medicine and Biology Magazine, Volume 24, Number 5, September/October 2005 Theodore W. Berger, Ashish Ahuja, Spiros H. Courellis, Samuel A. Deadwyler, Gopal Erinjippurath, Gregory A. Gerhardt, Ghassan Ghholmeih, John Granacki, Robert Hampson, Min Chi Hsiao, Jeffrey LaCoss, Vasilis Z. Marmarelis, Patrick Nasiatka, Vijay Srinivassan, Dong Song, Armand R. Tanguay, and Jack Wills, "Restoring Lost Cognitive Function", IEEE Engineering in Medicine and Biology Magazine, Volume 24, Number 5, September/October 2005 Book Chapters: M. L. Stephens, D. D. Spencer, I. Cavus, M. C. Hsiao, D. Song, S. A. Deadwyler, R. E. Hampson, D. Putz, J. E. Quintero, M. K. Bensalem-Owen, K. N. Hascup, R. E.C., B. K. Day, J. R. Nickell, F. Pomerleau, P. Huettl, J. J. Burmeister, P. M. Talauliker, V. Z. Marmarelis, J. J. Granacki, T. W. Berger, and G. A. Gerhardt, "Microelectrode-based epilepsy therapy: A hybrid neural prosthesis incorporating seizure prediction and intervention with biomimetic maintenance of normal hippocampal function," in Computational neuroscience in epilepsy, 1st ed, I. Soltesz and K. Staley, Eds. Amsterdam; Boston: Elsevier/Academic Press, 2008. Theodore W. Berger, Ashish Ahuja, Spiros H. Courellis, Gopal Erinjippurath, Ghassan Gholmieh, John J. Granacki, Min Chi Hsaio, Jeff LaCoss, Vasilis Z. Marmarelis, Patrick Nasiatka, Vijay Srinivasan, Dong Song, Armand R. Tanguay, Jr., and Jack Wills, Chapter 19: “Brain-Implantable Biomimetic Electronics As Neural Prostheses To Restore Lost Cognitive Function”, Handbook of Neural Enginnering, Wiley-IEEE Press, Metin Akay (Editor), January 2007 Walid Soussou, Ghassan Gholmieh, Martin Han, Ashish Ahuja, Dong Song, Min-Chi Hsiao, Zhuo Wang, Armand Tanguay and Theodore Berger, “Mapping Spatio-Temporal Electrophysiological Activity in Hippocampal Slices with Conformal Planar Multi-Electrode Arrays”, Advances in Network Electrophysiology, Springer, US, Taketani Makoto, and Michel Baudry (Editors), November 2006 Conferences: X. Fang, V. Srinivasan, J. Wills, J. Granacki, J. LaCoss, J. Chroma, "CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC", MWSCAS2009, Aug. 2009, pp.180-183, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009 X. Fang, J. Wills, J. Granacki, J. LaCoss, J. Choma, “CMOS Charge-Metering Microstimulator for Implantable Prosthetic Device,” MWSCAS2008, pp.826-829, Aug. 2008. Chiu-Hsien Chan; Wills, J.; LaCoss, J.; Granacki, J.J.; Choma, J.; “A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier” in Proceedings of IEEE International Symposium on Circuits and Systems, May 2007, pp. 337-340 Xiang Fang; Wills, J.; Granacki, J.; LaCoss, J.; Arakelian, A.; Weiland, J.; “Novel ChargeMetering Stimulus Amplifier for Biomimetic Implantable Prosthesis” in Proceedings of IEEE International Symposium on Circuits and Systems, May 2007, pp. 569-572 Chiu-Hsien Chan, Jack Wills, Jeff LaCoss, John J. Granacki, and John Choma, Jr., “A MicroPower Low-Noise Auto-Zeroing CMOS Amplifier for Cortical Neural Prostheses, In Proceedings of IEEE Biomedical Circuits and Systems Conference, November 2006 Hsiao, M-C., Chan, C-H., Srinivasan, V., Ahuja, A., Erinjippurath, G., Zanos, T.P., Gholmieh, G., Song, D., Wills, J.D., LaCoss, J., Courellis, S., Tanguay, Jr., A.R., Granacki, J.J., Marmarelis, V.Z., Berger, T.W. “VLSI implementation of a nonlinear neuronal model: A ‘neural prosthesis’ to restore hippocampal trisynaptic dynamics, in Proceedings of the IEEE EMBS Conference, August 2006 Michael Vahey, John Granacki, Lloyd Lewins, Drew Davidoff, Jeff Draper, Craig Steele, Gillian Groves, Matt Kramer, Jeff LaCoss, Kenneth Prager, Jim Kulp, Charles Channell, "MONARCH: A First Generation Polymorhpic Computing Processor", In Proceedings of High Performance Embedded Computing, September 2006 Berger, T.W., Gholmieh, G., Hsaio, M-C., Song, D., Granacki, J.J., Wills, J., LaCoss, J., Srinivasan, V., Marmarelias, V.Z., Courellis, S.H., Erinjippurath, G., Tanguay, A.R., Ahuja, A., Nasiatka, P., Deadwyler, S.A., Hampson, R.E., and Gerhardt, G.A. "Implantable Biomimetic Electronics as Neural Prostheses for Lost Cognitive Function", Proceedings of the 6th AsianPacific Conference on Medical and Biological Engineering, Tsukuba, Japan, April 2005. Chiu-Hsien Chan, Vijay Srinivasan, Min-Chi Hsiao, Sharad Khanna, Jack D. Wills, Ghassan, Gholmieh, Jeff LaCoss, Spiros Courellis, John J. Granacki, Theodore Berger, "Real Time Hardware Neural Spike Amplitude Extraction", In Proceedings IEEE Workshop on Biomedical Circuits and Systems 2004, November 2004. Theodore W. Berger, John J. Granacki, Vasislis Z. Marmarelis, Bing J. Sheu, Armand R. Tanguay, Jr., "Brain Implantable Biomimetic Electronics as Neural Prosthesis", In Proceedings of the 1st International IEEE EMBS Conference on Neural Engineering, March 20-22, 2003. John J. Granacki and Michael D. Vahey, “MONARCH: A High Performance Embedded Processor Architecture With Two Native Computing Modes”, In Proceedings of High Performance Embedded Computing, September 2002 Jeff Draper, Jacqueline Chame, Mary Hall, Jeff LaCoss, Craig Steele, John Granacki, Jaewook Shin, Chang-Woo Kang, Chun Chen, Herming Chiueh, Ihn Kim, Jay Moon, "The Architecture of the DIVA Processing-In-Memory Chip", Proceedings of 16th ACM-SIGARCH International Conference on Supercomputing, June 2002: Mary Hall, Peter Kogge, Jeff Koller, Pedro Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss, John Granacki, Jay Brockman, Apoorv Srivastava, William Athas, Vincent Freeh, Jaewook Shin, Joonseok Park, “Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture”, In Proceedings of SC99, November 1999. J. LaCoss, J. Granacki, J. Wills, “ISI research in law enforcement systems”, In Proceedings of SPIE International Symposium on Enabling Technologies for Law Enforcement and Security Vol. 3575, November 1998. Ivan Hom and John Granacki, “Estimation of the Number of Routing Layers and Total Wirelength in a PCB through Wiring Distribution Analysis”, In Proceedings of the European Design Automation Conference, Best Paper Nominee, pp. 310-315, September 1996. Sally A. Hayati, Alice C. Parker and John J. Granacki, “Representation of Control and Timing Behavior with Applications to Interface Synthesis”, In Proceedings of the IEEE International Conference on Computer Design, October 1988. John J. Granacki, Alice C. Parker and Yigal Arens, “Understanding System Specifications Written in Natural Language”, In Proceedings of the Tenth International Joint Conference on Artificial Intelligence, August 1987. Y. Arens, J. Granacki and A. Parker, “Phrasal Analysis of Multi-Noun Sequences”, In Proceedings of the 25th Annual Meeting of the Association for Computational Linguistics, July 1987. John J. Granacki and Alice C. Parker, “PHRAN-SPAN: A Natural Language Interface for System Specifications”, In Proceedings 24th Design Automation Conference, June1987. John J. Granacki and Alice C. Parker, “A Natural Language Interface for Specifying Digital Systems”, In Proceedings of the 1st Conference on Applications of Artificial Intelligence to Engineering Problems April 1986. J. Granacki, D. Knapp, and A. Parker. The ADAM Advanced Design Automation System: Overview Planner and Natural Language Interface, In Proceedings 22nd Design Automation Conference, June 1985. J. J. Granacki and A.C. Parker. “The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance”, In Proceedings 20th Design Automation Conference, June 1983. D.W. Knapp, J.J. Granacki and A.C. Parker. “An Expert Synthesis System, In Proceedings of the ICCAD, ACM-IEEE, September, 1983. Workshops: Kiran Bondalapati, Pedro Diniz, Phillip Duncan, John Granacki, Mary Hall, Rajeev Jain, Heidi Ziegler, “DEFACTO: A Design Environment for Adaptive Computing Technology”, Proceedings of the Reconfigurable Architectures Workshop, IPPS/SPDP'99, April 1999. Professional Activities Senior Member: IEEE Computer Society, ACM, Society for Neural Science Program Chair, IEEE Design Automation Workshop on System Level Modeling, January, 1990 Program Committees: Workshop on Reconfigurable Computing, October 1999, Japan, ICPP99; Intelligent Memory Systems at ASPLOS-IX, November 2000 Reviewer: Design Automation Conference 1986-1988, Computer Magazine 1988, 1989 and 1991, Transactions on Computer-Aided Design 1990 and 1991. Professional Experience (continued) The Aerospace Corporation 2350 East El Segundo Boulevard El Segundo, CA 90245-4691 Computer Science Laboratory Research Scientist 8/87 - 1/88 Technical director for several research projects. These projects included: knowledge-based systems for satellite-subsystem design and telemetry-data interpretation; verification and validation of knowledge bases; VLSI computer-aided design; rapid prototyping of software. Co-principal investigator on a project to develop high-level VLSI design tools for ASICs (Application Specific Integrated Circuits) in satellite-based signal and data processing systems. This project involved integrating conventional CAD tools with expert systems technology to narrow the performance gap between handcrafted chips and semi-custom designs developed with gate arrays or standard cells. Provided technical support to Program Offices. Reviewed contractors' technical proposals, attended contractors' briefings and performed independent studies to determine the technical feasibility of contractors' designs. Hughes Aircraft Company Electro-Optical and Data Systems Group P.O. Box 902 El Segundo, CA 90245 System Engineering Division, Space Systems Laboratory Senior Scientist/Engineer 12/84 - 8/87 Prime manager of research and development project: applied expert system and artificial intelligence technology to problems of building and interfacing to large complex databases. Had complete responsibility for all financial and technical aspects of project, including direct liaison with the customer's technical director. Concurrently, shared responsibility for technical management of system engineering for the BSTS (Boost Surveillance and Tracking System) On Board Processor and SSTS (Space Surveillance and Tracking System). Directed the overall system engineering technical effort including algorithm development and hardware and software development. Served as technical liaison for the Hughes to the prime BSTS contractor, Lockheed and liaison with TRW, the prime contractor for SSTS. Software Engineering Division, Computer Systems Engineering Laboratory Senior Scientist 8/83 - 11/84 System engineer for a large real time system: performed system trade studies to determine suitability of hardware architecture for algorithms; evaluated hardware and derived system performance limitations and cost; developed software system architecture and supporting hardware configurations; assisted in development of requirements, specifications and proposals. Product Integrity Operation, Computer-Aided Design Department Senior Scientist 3/81 - 7/83 Technical manager for a project to develop an automated layout system for VLSI, LSI, hybrids and etched printed circuit boards. Designed of system architecture and interfaces; research and developed methodologies, heuristics and algorithms for partitioning, placement, routing and artwork generation. Space Sensors Division, Electronics Department Senior Staff Engineer/Acting Section Head 9/77 - 2/81 Led a group of twelve engineers in developing LSI and solid state device technology for advanced signal processor implementations. Directed the design activity for a 16K clocked-static CMOS/SOS RAM using two-micron design rules and a set of LSI chips for an array-type processor on the HALO Signal Processor Program. RCA Solid State Division Somerville, New Jersey 08876 LSI Circuit Design Department Member Technical Staff 1975 – 1977 Designed, developed, and provided production support for various large scale integrated circuits for microprocessor systems. These circuits included: custom I/O chips for automotive control, A/D converters and Random Access Memories and were fabricated in four technologies: Closed CMOS Logic, bulk CMOS, Integrated Injection Logic, and CMOS/SOS. Performed device characterization for circuit design in Closed CMOS Logic and reliability investigations, also researched and characterized input protection circuitry. Automotive circuits developed for Bosch and Chrysler were used in production vehicles (the Bosch circuit was used by Volkswagen). Power Transistor Design Department Member Technical Staff 1970 - 1975 Assumed total design and development responsibility for manufacturing support of $20+ million/year Hometaxial transistor operation. Adopted innovative statistical techniques and real time computer analysis, which resulted in cost savings in excess of one million dollars per year. Concurrently, investigated phosphorous deposition and diffusion processes, electroless Ni plating process, emitter efficiency, device thermal management problems and the design of epitaxial devices with improved power handling capability. Solved a major technical problem of gain degradation on large area PNP epitaxial transistors, which allowed production of a viable product. Coordinated data collection and compiled report on causes of yield losses for epi base product; this project provided stimulus for eventual upgrading of all power transistor-manufacturing facilities.