Analysis and Design of High Performance and Low Power
Current Mode Logic CMOS
Phillip Chin, Junjie Su, and Xiaolan Zhong
University of California, Berkeley
Abstract
With the scaling down of CMOS transistors, many issues, once
considered negligible, now have become a factor in design. Some of
these problems are leakage current and power consumption. The
solution this paper will address is using current mode logic as opposed
to traditional voltages. In the early stages of this research, a number of
gates have been implemented and are compared against their static
CMOS counterparts. We also begin by analyzing 90nm MOSFETs and
will continue to work down to lower channel lengths.
I. Introduction
The scaling down of CMOS transistors has posed new
problems for designers. As the limits of size are being
reached, new logic styles will be needed to continue the
trend. Current mode logic (CML) was researched in the
past, but may offer a solution for today’s technology. CML
implements some analog components to compute logic.
Typically, CML refers to a logic style where voltages values
still determine the logic values of the inputs and outputs, but
current is only used as an intermediate variable. The basic
structure consists of differential pairs with dual outputs. The
inputs steer the current down one branch or the other to
compute logic [3].
This paper focuses on “true” CML where the input and
output values are actually currents (throughout this paper,
CML will refer to true CML). The basic method of
computation is current mirrors, which pass values by
mirroring currents through other transistors. CML offers a
number of advantages such as a reduced number of
transistors and a smaller area [1]. A one bit adder cell has
been built with as little as 15 transistors using current mode
logic [2]. Also, given a supply voltage, the performance of a
CML gate can be optimized for delay, power, and the
switching noise. Previously, with static CMOS, the only real
parameter that could be changed was the size. With a
control over the current, current as a parameter can be used
to increase performance [1].
However, there are some drawbacks that will have to be
overcome. The supply current of a CML gate is independent
operating frequency; there will be static power dissipation.
However, at higher frequencies less power is dissipated than
the static CMOS counterparts [5]. This will lead a reduction
in voltage supply and current. However, scaling down these
parameters will lead to a greater impact of leakage current.
In particular if the nanoAmpere level is the target, it will be
about the same magnitude of the leakage current. Thus, the
circuit become less robust and is more prone to errors.
II. CML Logic Gates
As stated before the inputs and outputs to CML gates are
currents. A number of different implementations have been
explored; depending on the gate, logic “1” could be
presence of current with logic “0” being absence of current
or visa versa.
A. Inverter
The CML Inverter is made using an NMOS current mirror,
using a PMOS current source connected to the diodeconnected NMOS. For this structure, the presence of current
is logic “1”. When Iin is high, the current from the PMOS
transistor will flow through that branch, leaving no current
to go through the mirror. This will effectively turn off the
mirror network and Iout will be low. However, depending on
the current going through the PMOS, the leakage current of
the mirror network, when it is turned off, can become a
factor and produce errors in computation [1].
Fig. 1. CML Inverter
B. NAND Gate
The inverter presented above can be modified slightly to
produce a CML NAND gate. At the input node in the
inverter, multiple inputs can be attached to that node. To
account for this the PMOS must be resized such that the
amount of current is multiplied by the number of inputs. So,
if all the inputs are high, the current leaving will be the
number of inputs times the original current (i.e. the amount
supplied by the PMOS). Like the inverter the output will be
low. However, if any of the inputs are low, there will be
enough current to flow through the mirror such that the
output NMOS is turned on to produce an output current. As
long as there is a presence of current, the output is
considered to be high [1].
1
Fig. 4. CML NOR Gate
Fig. 2. CML NAND gate created from Inverter
III. Performance Comparison
As a preliminary test, the static CMOS and CML NOR
gates were compared in performance. As was noted earlier,
for higher frequencies, the CML actually performs better
[5]. The Static CMOS suffers greatly, which would suggest
for high frequency applications, CML would be the best
choice.
Delay*Power vs. Operating Frequency of NOR Gate
2000
1800
1600
1400
1200
1000
800
600
400
200
0
Static CMOS
CML
(ps)
Delay*Power (ps)
A second NAND gate implementation is shown in Figure 3.
The current sources in the bottom left represent the inputs to
the NAND gate. A key feature to this design, is that M5, a
PMOS (bad pull down device), is connected ground,
required a threshold drop, so it can effectively be turned off
when it needs to be. The key component that makes this
work is that when all the inputs are high, all the current
supplied by the upper left current supply and M6’s current
will be drawn through the inputs. This will effectively turn
off M5. The PMOS on the output branch must be sized to
twice M6, because the maximum current flowing through
M6 is 0.5I. Therefore the current at the outputs will equal to
high and be drawn through the current supply at the output
branch making Iout low. If any of the inputs are turned off,
M5 will have to be on and M6 will be off. This will turn off
the PMOS at the output branch, forcing the current to be
drawn from Iout [4].
0
1
2
3
4
Operating Frequency (GHZ)
Fig. 5. Delay-Power Product Comparison between Static CMOS and CML
NOR gate.
Fig. 3. A second implementation of a CML NAND Gate
C. NOR Gate
The CML NOR gate is essentially the reverse of the second
CML NAND Gate as can be seen in Figure 4. The upper left
current supply supplies the opposite of the NAND gate.
Like the NAND gate, an NMOS is connected to the supply
voltage, requiring a threshold voltage drop across it,
allowing it to be turned off when needed. When any of the
inputs are high, M3’s current will rise to supply the current
demanded by the inputs. This will keep M1 off and thus
turning off the NMOS at the output branch. However, when
all the inputs are off, the 0.5I will flow through M1 making
Iout high [4].
As mentioned earlier the robustness of CML gates are
still in question. This is due to the increasing influence of
the leakage current. In the case of the NOR gate, the logic
swing is not perfect. As can be seen from figure 6, the input
switches at a rate of 5 GHz. The high value of current is 10
μA. There are a few noticeable spikes, but it swings from to
the desired values. However, if less than 1 μA, the circuit
becomes difficult to bias and the output is centered at a new
current value.
Many difficulties were experienced when running these
tests. In particular, tests were run on SPICE, but it seems not
to cater well to current. For example, nodes were
inaccessible for currents, where as voltage could be
measured easily. Also, it was very difficult putting a load at
the output of the gate. For voltage mode logic, a capacitor
sufficed, because it held the voltage. Unfortunately, most
2
common devices will not work for the current case. In our
case we used a diode connected MOSFET, but it did not
work perfectly and there was always current flowing
through it, even at times when it should not have been. This
made it difficult to implement the circuit, even though a
partially working one was built.
Fig. 6. CML NOR gate out with input switching at 5GHz.
An inverter chain was also built and tested for
robustness. Due to the difficulties of SPICE, the currents
from each stage could not be measured, but the voltages
were measured. As the signal progressed through the
inverter chain, the voltage signal degraded. This may
suggest that CML circuits do not work well when put in a
long chain. It also seems safe to assume that the current
signal must have been affected as well, which would
suggest poor robustness.
will be first made in layout, with the netlist extracted from
it.
V. References
[1] Ismail Enis Ungan and Murat Askar, A Wired-AND
Current-Mode Circuit Technique in CMOS for LowVoltage, High-Speed and Mixed-Signal VLSIC, Analog
Integrated Circuits and Signal Processing, pp. 59-70,
November 18, 1996.
[2] K. Navi, A. Kazeminejad, and D. Etiemble,
Performance of CMOS Current Mode Full Adders,
Proceedings of The Twenty-fourth International
Symposium on Multiple-Valued Logic, pp.27-34, May
27, 1994
[3] Jason M. Musicer, Jan Rabaey, MOS Current Mode
Logic for Low Power, Low Noise CORDIC
Computation
in
Mixed-Signal
Environments,
Proceedings of ISLPED, 2000, pp.102-107, July 26-27,
2000
[4] Jan Rabaey’s EE241 slides
[5] Vasanth Kakani, Delay Analysis and Optimal Biasing
for High Speed Low Power Current Mode Logic
Circuits, 2004 IEEE International Symposium on
Circuits and Systems. IEEE Part Vol. 2, pp. II-869-872,
May 23-26, 2004.
IV. Conclusions and Proposals
Based on our simulation, if CML is used in a high
frequency, high performance task, it has an advantage over
static CMOS. However, the robustness of the circuit still
remains an issue. It is greatly affected by leakage current
and bias voltage. In these cases static CMOS these problems
for the most part do not exist. These problems also made the
CML gate difficult to implement. From the tests that were
run, it appears that CML circuits may perform poorly if put
in long chain.
In these preliminary tests, we used ideal current sources
whenever they were drawn that way in the figures. These
will have to later be replaced by MOS current sources. We
believe this will actually help, because MOS current sources
themselves have leakage current, whereas ideal current
sources do not. Biasing is another concern with the circuits.
As lower voltage and currents are applied, the precision of
the bias voltage becomes ever more important. It will
clearly have a great effect as the smaller transistors are used.
In the future, we plan to run tests with the 60nm and
45nm models. The results in this regime are normally less
predictable, but we hope that we can develop logic that can
be properly computable. As mentioned above with leakage
currents, we hope to possibly take advantage of leakage
currents and use it to our benefit. We will combine the
implemented building blocks into larger modules and chains
and eventually into a larger structure such as an adder. It
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