Simple thermal analysis of ADC board for MUSIC Readout
David Miller, 9/14/2010
Using the design guidelines and gerber layout files provided by Rick Raffanti, a thermal
resistance model was developed to highlight the heat dissipation from the ADC chip (Texas
Instruments ADS54RF63) to the surrounding PCB and environment. The thermal resistance can
define it as,
R
T
Q
where, T = temperature change between two surfaces, and Q = heat flow between the
two surfaces. At steady state the thermal conductivity is defined as,

Q L
T A
where, L = path length between two surfaces, and A = cross-sectional area of each
surface in which the heat flows thru. Relating these equations gives,
R
1 L
 A
From the PCB design and manufacturing guidelines, the 30 via holes under the ADC
package are 0.014” DIA, with plating wall thickness of 0.001”. These via holes are filled with
conductive material. Also, the 84 via holes scattered between the four mounting holes near the
edges of the PCB are of similar construction. The mounting holes are 0.125” finished diameter,
with a plated wall thickness of 0.001”. Each of the six metal layers is composed of 1 oz. copper
clad, which has a nominal thickness of 0.0014”. The top and bottom layers are reflowed and
built up with tin/lead plating to achieve a total of 1.5 oz of metallization, since their traces are
exposed. In the calculations of thermal resistances, only the thermal conductivity of copper was
used, since most of the effective thermal paths for heat dissipation are along the inner two metal
plane areas – the exception is for the interface between the metal pad on the bottom of the ADC
package and the thermal land area under the package, when the thermal conductivity of 80/20
tin/lead solder was used. The possible contribution of mounting screws to the thermal analysis
were not taken into account. The thermal conductivities used in the calculations were,
 For copper,   385 W
mK
 For solder,   50 W
mK
In modeling the thermal resistance of the via holes, it was assumed that the crosssectional area is a solid cylinder, since the holes were filled with conductive material. Thus, the
thermal resistance for each via hole is found to be,
Rvia _ x 
Lx
Lx
1
100

 Lx * 6.643 *10 2 C W
2
2
  *r
385  * 0.007 2.54
1
Where L x = height of via hole, determined by the thickness of the board material
sandwiched between the two metal layers. The ratio (100/2.54) converts centimeters to inches
and Kelvin to Centigrade. In the PCB layer stack-up, the board material between the six layers
of metal are different thickness, due to the need for designing controlled impedance signal lines.
Table 1 summarizes the board material thicknesses, thermal resistance for each via hole
pertaining to that board material, the number of via holes in parallel, and the resulting thermal
resistance from combining the effects of the individual via holes. The thermal resistances add in
parallel in the same manner as calculations performed with electronic resistor values.
Board
Layer No.
1
2-4
5
2-4
5
Connecting
Metal Layers
Top to Int1
Int1 to Int4
Int4 to Bottom
Int1 to Int4
Int4 to Bottom
x
Lx
Rvia _ x
1
2
3
4
5
0.007”
0.0424”
0.007”
0.0424”
0.007”
4.65
28.166
4.65
28.166
4.65
No. of
vias
30
30
30
84
84
Total Rvia _ x
0.155
0.939
0.155
0.335
0.055
Table 1
To model the thermal resistance of the mounting holes, the cross-sectional area is a
hollowed cylinder, and the appropriate equation gives,
RMT _ x 
1
Lx
  * (ro  ri )
2
2

Lx
1
100
 Lx * 2.583 *10 2 C
0.127 2
0.125 2
W
385  * [( 2 )  ( 2 ) ] 2.54
Table 2 summarizes the characteristics and thermal resistances for each mounting hole
for the respective board and metal layer placement, along with the total thermal resistance for the
occurrence of the number of mounting holes grouped together at that placement.
Board
Layer No.
Connecting
Metal Layers
x
Lx
R MT _ x
2-4
5
Int1 to Int4
Int4 to Bottom
1
2
0.0424”
0.007”
10.953
1.808
No. of
mounting
holes
4
4
Total R MT _ x
2.738
0.452
Table 2
In modeling the metal plane areas between the via holes under the chip package and the
via holes and mounting holes at the edge of the circuit board, several stipulations were
established. For the two inner plane areas, the width of the cross-sectional area for heat flow was
set to the corner-to-corner distance of the thermal land area of the ADC chip package, as defined
on the top metal layer. This distance is 0.6”. The distances from the middle of the thermal land
area and the middle of each mounting hole was used as the length for the path of heat flow, and
the calculation accounted for the total contribution by combining the separate paths in parallel, to
arrive at a single number for the thermal resistance of the metal plane area. Examining how the
ADCs are positioned in respect to each other and the via and mounting holes at the edges of the
PCB, only the mounting holes and via holes closest to each package are accounted for, as it is
reasonable to imagine that once the chips heat up, they would essentially block heat flow
between themselves, with the result that heat would migrate primarily from each chip to the
mounting and via holes on the edge of the circuit board nearest that respective chip package.
The equation for finding the thermal resistance of each heat path is,
RINT _ x 
dx
1 dx
1
100

 d x *1.217 *10 2 C W
 W * t 385 0.6 * 0.0014 2.54
The bottom layer of the PCB also contains a partial metal plane area connecting the
ADCs to the edge of the circuit board, although it is constricted. The width of the cross-sectional
area for the calculation for each thermal path was set to 0.15”, which is the width of the
constriction. The same lengths were used as for the metal plane layers. The equation is the same
as for the inner layers, except for the width used.
RSB 
dx
1 dx
1
100

 d x * 4.870 *10 2 C W
 W * t 385 0.15 * 0.0014 2.54
Table 3 lists the particulars for the metal layers and the resulting thermal resistance for
each layer. The distances for each of the four path lengths on each layer are,
d1 = 2.15”; d 2 = 1.28”; d 3 = 1.23”; d 4 = 2.07”
Metal Layer
No.
2 (INT1)
5 (INT4)
6 (Solder
Bottom)
RPath _ 1
R Path _ 2
R Path _ 3
R Path _ 4
Total
RINT _ 1 ; RINT _ 4 ; RSB
261.737
261.737
155.825
155.825
149.738
149.738
251.998
251.998
47.882
47.882
1046.948
623.300
598.952
1007.992
191.528
Table 3
The model for the thermal resistances of the ADC chips and PCB is,
Figure 1
where:
R_JC = thermal resistance between junction chip and chip case
R_CA = thermal resistance between chip case and ambient temperature
R_JP = thermal resistance from junction chip to metal paddle on bottom of package
R_solder = thermal resistance of the solder joint between the package and thermal land area on
PCB
R_via1 = thermal resistance of 30 via holes between top layer and first interior layer of PCB
R_via2 = thermal resistance of 30 via holes between first interior layer and fourth interior layer
of PCB
R_via3 = thermal resistance of 30 via holes between fourth interior layer and bottom layer of
PCB
R_via4 = thermal resistance of 84 via holes between first interior layer and fourth interior layer
of PCB, located between four mounting holes at edge of PCB
R_via5 = thermal resistance of 84 via holes between fourth interior layer and bottom layer of
PCB, located between four mounting holes at edge of PCB
R_INT1 = thermal resistance of plane copper area on first interior layer, located between the 30
via holes and the four mounting holes/84 via holes at PCB edge
R_INT4 = thermal resistance of plane copper area on fourth interior layer, located between the
30 via holes and the four mounting holes/84 via holes at the PCB edge
R_MT1 = thermal resistance of four mounting holes between the first interior layer and the
fourth interior layer of PCB
R_MT2 = thermal resistance of four mounting holes between the fourth interior layer and the
bottom layer of PCB
R_SB = thermal resistance of copper area on bottom layer of PCB
R_BE = thermal resistance of interface between exposed mounting area on bottom of board and
equipment case (temperature reservoir)
P_in = thermal energy generated in the ADC chip
The specification sheet gives values for the power dissipated by the chip, the junction-toambient thermal resistance, and the junction-to-pad thermal resistance.
P_in = 2.5 Watts
R_JA = R_JC + R_CA = 23.7 C
R_JP = 0.2 C
W
W
To simply the model, combine in parallel the resistances (R_MT1 and R_VIA4) = 0.299,
and (R_MT2 and R_VIA5) = 0.0493  0. Further combining resistances results in the
simplified model in Figure 2,
Figure 2
Note that most of the thermal resistance resides in the metal plane areas! Further
simplification results in the final basic model in Figure 3,
Figure 3
Examining the effects of this model based on R_BE, and setting the ambient temperature to
30 C,
1. If R_BE =  ; essentially the board is not heatsunk, then
Tchip  P * R _ JA  Tamb  (2.5)( 23.7)  30  89.25 C.
2. If R_BE = 0; essentially the board is perfectly heatsunk, then
Tchip




1

  T  (2.5)(11.42)  30  58.55 C.
 P*
 1
 amb
1



 R _ JA R _ PCB 
Conclusions
Two things pop out from this analysis:
1) Most of the thermal resistance that impedes heat getting out of the chip and off the board is
in the two inner metal planes, which are intended to provide the primary thermal path.
2) The thermal resistance of the junction-to-ambient is approximately the same as the thermal
resistance of the PCB.
With the number of ADC, DAC, Roach, and IF boards that will eventually be packaged
in a single electronics box, even with improved heatsinking through the use of thick metal
brackets to capture and clamp the exposed metal areas of the ADC PCB, there should be concern
of the boards and chips operating at elevated temperatures. Thus, lowering the thermal
resistance of the PCB would enhance the possibility of designing and operating the final readout
electronics box without force-air or liquid cooling.
One suggestion is to increase the copper clad of the inner plane areas, INT1 and INT4,
from 1 oz. to 2 oz (or more?). This would decrease the PCB thermal resistance by about 50%,
with a corresponding reduction in chip temperature of roughly 16%. Since new boards are on
the near-term schedule, this should be explored as an option. Is there some limitation to the
thickness of metal that can be used in the inner layers of multilayer PCBs?
Another suggestion is to add metal layers, by increasing the PCB layer count from six to
eight. These could be additional ground layers, for instance. The center board material layer is
0.0236” thick, while the board layers which pertain to the controlled impedance designs are
0.007” and 0.008”, respectfully. This central board material layer could be subdivided into
additional metal and material layers. The additional price for more layers may make this option
too costly. Is the higher price of PCBs with more layers not cost effective for adding internal
metal layers for better thermal performance?