Master’s Project Proposal
“The DES Algorithm Implementing VHDL
and Microsoft Visual C++ 6.0 Programming Language”
24 May 2005
Prepared For:
St. Mary’s University Engineering Department
One Camino Santa Maria
San Antonio, TX 78228-8503
TABLE OF CONTENTS
1. Introduction…………………………….………………………..….4
1.1
Goals & Objectives…………………….………………....4-5
1.2
Statement of Scope…………………………….……….…..6
2. DES Alogrithm Model & Description……………..………..……..6
2.1 DES Algorithm Model………………………..………............7
3. Software Description using Visual C++………..………………...7
3.1 Software Input for Plaintext………………..…………………7
3.2 Software Output for Encrypted Text……..………………….7
4. Hardware Interface Description for VHDL…..……………………8
4.1 Keyboard Interface……………………..…………….............8
4.2 CRT Interface…………………….……………………………8
5. Restrictions and Limitations……………………………………….8
6. Research Materials…………………………………………………9
Table of Figures
Figure 1 DES Algorithm Model…………………………………………7
SOFTWARE REQUIREMENTS SPECIFICATION
1
Introduction
This Master’s Project Proposal establishes the requirements for the “The DES
Algorithm implementing VHDL and Microsoft Visual C++ 6.0 Programming
Language”. This document will describe all data, functional and behavioral
requirements for the Master’s Project.
1.1
Goals and objectives
The goal of the Master’s project is to implement the DES algorithm using VHDL
and Microsoft Visual C++ 6.0 and to state execution times of software versus
hardware. The algorithm and results will be presented in time for the August
graduation deadline.
1.2
Statement of scope
The DES algorithm will be programmatically incorporate the Very High Speed
Integrated Circuit Hardware Description Language using MaxPlus2. The
program in VHDL will accept the plaintext to be encrypted by the user via an
external keyboard that will be interfaced with the VHDL board. The “plaintext”
will be processed by the VHDL board and broken down into a block of 64 bits
that will undergo an initial permutation. The 64 bits of data are transformed by a
64-bit key. The 64 permuted data bits are broken into a left half and a right half of
32 bits each. The key is shifted left by a number of bits and permuted. The key
is combined with the right half, which is then combined with the left half. The
result of these combinations, become the new right half and the old right half
becomes the new left half. The sequence of these combinations, constitute a
cycle which is then repeated sixteen times. After the last cycle is completed, a
final permutation is then executed. The result of the DES algorithm will then be
outputted to a CRT screen that will be connected to the VHDL board. The user
will then see both the encrypted text and the deciphered text on the CRT screen.
In addition to the VHDL code that will be generated, a Microsoft Visual
C++ 6.0 program will also be generated. The MS Visual C++ program will prompt
the user to input a text which will be broken up into a block of 64 bits that will
undergo an initial permutation. The 64 bits of data are transformed by a 64-bit
key. The 64 permuted data bits are broken into a left half and a right half of 32
bits each. The key is shifted left by a number of bits and then permuted. The
key is combined with the right half, which is then combined with the left half. The
result of these combinations, become the new right half and the old right half
becomes the new left half. The sequence of these combinations, constitute a
cycle which is then repeated sixteen times. After the last cycle is completed, a
final permutation is then executed. The result of the encrypted text from the
DES algorithm will then be displayed on a CRT screen along with the
deciphered text.
After execution of the both the VHDL program and C++ program are
complete, execution times will be gathered in VHDL by the timing analyzer within
MaxPlus2 for the VHDL program. Execution times for the C++ program, will be
gathered by a script or “other program”. The results outputted by both programs
will be reported in the final analysis of the Master’s project. Project delivery is
anticipated to be in time for the August graduation deadline.
2
2.1
DES Algorithm Model and Description
DES Algorithm Model
The DES Algorithm model for the Master’s Project, “The DES Algorithm
Implementing VHDL and Microsoft Visual C++ 6.0 Programming Language”
provides a breakdown of the algorithm. Figure 1 illustrates the algorithm for
the DES Encryption algorithm.
Figure 1 DES Algorithm Model
The user will input a text which will be broken up into a block of 64 bits that
will undergo an initial permutation. The 64 bits of data are transformed by a
64-bit key. The 64 permuted data bits are broken into a left half and a right
half of 32 bits each. The key is shifted left by a number of bits and then
permuted. The key is combined with the right half, which is then combined
with the left half. The result of these combinations, become the new right
half and the old right half becomes the new left half. The sequence of these
combinations, constitute a cycle which is then repeated sixteen times. After
the last cycle is completed, a final permutation is then executed. Both the
encrypted and decrypted text from the DES algorithm will be displayed on a
CRT screen.
3
Software Description using Visual C++
The following information describes the software input for the plaintext data
and the software output for the encrypted text. The software will be written in
Visual C++.
3.1 Software Input for Plaintext
The software that will be written in Visual C++ will prompt the user to input a
plaintext message. The plaintext message will be broken up into a block of
64 bits that will undergo an initial permutation. The initial permutation will be
the first step of the DES algorithm. The rest of the algorithm is defined in
section 2.1 above.
3.2 Software Output for Encrypted Text
3.3 The Visual C++ program that will be developed, will prompt a user to input a
plaintext message. After clicking an encryption button within the software
application, the encrypted message will be displayed from the plaintext
message that is inputted by the user. To view the deciphered message from
the encrypted text, a user will click another button that will display the
plaintext message on the CRT screen.
4 Hardware Interface Description for VHDL – The following information
describes the keyboard Interface to capture the plaintext information from the
user into the VHDL board. In addition to this, the description of the CRT
monitor and how it will be connected to the VHDL board to output the
encrypted text is also defined.
4.1 Keyboard Interface - The keyboard interface will be attached to the serial
port of the VHDL board. The serial port for the keyboard will have a
keyboard_clk, keyboard_data, a 25MHZ clock, a reset, a read, a scan code
that accepts a standard logic vector, and a scan_ready signal. The keyboard
process will filter the raw clock signal coming from the keyboard using a shift
register and two AND gates. The data coming from the terminal process will
look up scan codes that will represent the letters ‘a’' through ‘z’. Once the
scan codes are retrieved for the input received from the keyboard, the data
will be stored into a 64-bit data block that will process the DES algorithm.
4.2 CRT Interface for Encrypted Text Output – In order to display the output
from the VHDL board, the CRT screen will be interfaced with the VHDL board
via a video port. The encrypted text and the deciphered text will be displayed
on the CRT monitor by controlling a series of signals from the VHDL board.
5
Restrictions, Limitations, and Constraints
There are no specific restrictions, limitations, or constraints at this time.
6
Research Materials
Roth Jr., Charles H. Digital Systems Design Using VHDL. PWS Publishing
Company. 1998.
Stallings, William. Cryptography and Network Security: Principles and Practices.
Third Edition. Prentice Hall. 2003.