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Chip Designer
January 24, 2008
Power
www.chipdesignmag.com/chipdesigner
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In this Issue:
1. The Hidden Impact of Circuit Activity on Power
2. DC-DC Converter Extends Battery Life in Portable Devices
3. Power Management IC Solution for MIDs
4. JTAG Support Extended for OCTEON Plus
5. WiCkeD Tool Family for Analog Mixed-Signal Design Flow
6. Linde Expands Business with Semiconductor Manufacturers in China
7. UpZide Developing Multi-Core VDSL2 Modem Chipset
8. In-Depth Coverage Links
> New Look at an Old Standard: Current Conveyor in Today's Designs
> Generating C-code from MATLAB Functions
9. Featured Book
> Design for Manufacturability and Statistical Design: A Constructive Approach
10. Happenings -- Conferences
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1. Viewpoint - Exclusive
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The Hidden Impact of Circuit Activity on Power
Marc Swinnen, director of product marketing, Azuro Inc.
(http://www.azuro.com/)
[headshot: 0108_CD_MSwinnen.JPG]
Do you have a standard activity profile to optimize and sign-off your design power? You probably think
you don’t, but in fact you do.
With all the discussion by the semiconductor industry on delivering lower-power chips, it is surprising
how often the central role of circuit activity as a key input to almost all forms of power calculation is
underappreciated. I believe we should actively embrace and manage the reality of circuit activity by
deploying statistical activity generators to present each optimization step in the flow with the best
possible activity profile. This will avoid wasted optimization effort, correct misdirected trade-offs, and
ultimately lower the real-world power consumption of chips.
To understand why activity is so important to all power measurements, we should first clarify what is
meant by "activity." Two key components of activity need to be quantified for power measurement: the
probability of a node changing level (Pswitch) and the probability of a node having a logic level of 1 or
0 (Phigh). Most designers understand that Pswitch is required to compute dynamic power; for example,
it determines the "f" in P = ½CV^2f. What is often not appreciated is how leakage power also depends
on the Phigh part of activity. Because p-type transistors leak much more than n-types, leakage power is
highly state dependent. Other examples of the impact of activity on power measurement are: RTL and
gate-level clock gating, which can increase or decrease the power depending on activity; reducing the
capacitance (and hence power) of very active wires by giving them wide spacing preferentially over
inactive wires; and the calculation of maximum currents to properly dimension power supplies for IRdrop.
Most design teams today do not explicitly consider activity during power analysis optimization. But
ignoring a problem doesn’t make it go away. Since the fundamentals of power calculation rely on
activity, if it is not quantified explicitly by the designer, then power analysis or optimization tools must
be making assumptions about activity somewhere "under the hood." Often this hidden assumption is
that Pswitch=Phigh=50%. These unrealistic assumptions can tilt trade-offs in the wrong direction and
may, for example, misdirect much of the optimization effort to parts of the design that are, in reality, not
very active, leaving a lot of potential power savings lying on the table.
Some may argue that, absent any good activity profile, it is a "safe" and prudent worst-case design
practice to focus instead on simply minimizing the capacitance throughout the design. But this is not the
case. For example, assuming that a test or reset signal has a 50% Pswitch is almost guaranteed to give a
meaningless power measurement. Wireless design teams are sometimes surprised to find their standby
leakage power to be much higher than they had anticipated because their analysis tools had implicitly
assumed a Phigh of 50% on all nodes, when in fact the level of many critical signals in standby is well
known and closer to 0% or 100%. So, you do indeed have a standard activity profile for optimization
and sign-off, whether you know it or not. And if you don’t know it, then it is probably a very bad one.
So what alternatives are there to relying on fixed Phigh and Pswitch? There are two possible solutions.
The first is to generate a true activity profile by running a well-considered real-world simulation on the
design. The problem with this approach is that such simulations are almost never available prior to
tapeout, and there is almost never the resources or time available to run them. The alternative is to use a
statistical "vectorless" activity generator. The problem here is finding one that delivers credible results.
To produce reliable results, the statistical activity generator must meet two requirements. First, it must
make use of any information that is already available in the design flow that can provide vital insights
into activity. For example, the SDC file contains a wealth of information about clocks and fixed control
signals. Library files clearly identify clock-gates, reset pins, and test pins. If an RTL-level simulation is
available, then the activity can be annotated to the gate level netlist for the invariant points (for example,
flip-flops). The second requirement for reliable statistical activity generation is a good activity
propagation engine. When feedback paths are considered, statistical propagation gets very hard, but it is
not unsolvable. By combining an effective propagation engine with solid heuristics for inferring activity,
a cutting edge statistical activity generator can deliver activity profiles that are significantly more
reliable than the alternative of relying on fixed Pswitch and Phigh and can do it without any impact on
tapeout schedules or resource plans.
My conclusion is that power analysis and power optimization depend directly on the activity of a circuit,
and this dependency exists whether or not a design team embraces an explicit methodology for activity
profile creation. Furthermore, by adopting an appropriate statistical activity generation tool, a design
team can reliably create credible activity profiles for designs without any impact on schedules or
resources. By deploying such a tool within a design flow, design teams can more accurately predict
silicon power prior to tapeout and perform more effective power optimizations during implementation.
Marc Swinnen is the director of product marketing at Azuro Inc.
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2. News
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DC-DC Converter Extends Battery Life in Portable Devices
Semtech has announced two new dual-output synchronous DC-DC buck converters, the SC198 and
SC198A, each with eight VID programmable output voltage settings that let portable systems
manufacturers lower processor voltages and extend the battery life of devices. The SC198 and SC198A
provide options for powering core ICs in fixed 5V, single Li-ion cell portable systems or three-cell
NiMH/NiCd systems, such as mobile and cordless phones, MP3 players, and handheld game consoles.
Each channel from either converter operates with a fixed 1MHz oscillator frequency, which maximizes
the efficiency under normal loads. Under light loads, the regulators automatically transition to powersave mode to maintain high efficiency.
Semtech >> http:// www.semtech.com/
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3. News
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Power Management IC Solution for MIDs
Freescale Semiconductor is developing a high-performance audio and power management solution for
Intel-based mobile Internet devices (MIDs). The integrated chip set is designed to manage power,
enabling smaller form factors and longer battery life. The audio and power management chipset will be
manufactured on Freescale’s SMARTMOS technology, a high-voltage CMOS-based process that
enables integration of precision analog, power devices, and logic. When paired with Intel’s low-power
processors and chipsets, the forthcoming power management chipset will provide an energy-efficient
processing solution for a range of MIDs.
Freescale Semiconductor >> http://www.freescale.com/
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4. News
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JTAG Support Extended for OCTEON Plus
Mentor Graphics has announced extension of EDGE MAJIC JTAG debug probe support for the Cavium
Networks OCTEON Plus multi-core processor family. Designed for a multi-core environment, the
MAJIC series probes provide JTAG connection to the debug support unit designed into each OCTEON
Plus cnMIPS core. The MAJIC-MT model supports concurrent connections to the multiple cnMIPS 64bit cores to facilitate code development and debugging for any combination of cnMIPS cores. MAJIC
includes software interfaces to support multiple development tool environments, including any Linux
environment such as Cavium’s SDK implementation as well as control of Octeon’s Global-Stop on-chip
hardware support to enable hardware-synchronized debugging for user-specified core combinations.
Mentor Graphics >> http://www.systemc.org/
Cavium Networks >> http://www.cavium.com/
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5. News
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WiCkeD Tool Family for Analog Mixed-Signal Design Flow
Hynix has licensed MunEDA’s enhanced DFM-DFY analysis and optimization tool suite WiCkeD for
use in Hynix's analog mixed-signal design and foundry flow. WiCkeD is a software tool suite for
interactive, manual, semi- and full-automatic analysis, sizing, and yield optimization of analog and
mixed signal circuits. Hynix intends to use MunEDA’s technology in all design business units, such as
computing, consumer, and graphics memory as well as mobile applications and flash technology. Hynix
will also use MunEDA’s design validation and yield verification tools for design-kit quality assurance.
Hynix >> http://www.hynix.com/
MunEDA >> http://www.muneda.com/
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6. International News
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Linde Expands Business with Semiconductor Manufacturers in China
The Linde Group is expanding its business with semiconductor manufacturers in China, signing
multiple, multi-year contracts to supply high purity gases to the country’s wafer fabrication plants. In
China, Linde has supported the semiconductor manufacturing industry, by contracting to supply wafer
fabs located in Chengdu, Shanghai, and Suzhou. It will add Dalian to its list, entering into a new, multiyear agreement to supply high-purity bulk gases to the new 300mm wafer fabrication being built by a
major IC manufacturer. Using its Spectra technology, Linde will build an integrated ultra-high purity
nitrogen and oxygen plant as well as a hydrogen generator and supply systems for argon and helium.
Linde will also install additional infrastructure for purification, filtration, and quality assurance
functions.
The Linde Group >> http://www.linde.com
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7. International News
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UpZide Developing Multi-Core VDSL2 Modem Chipset
Tensilica and Swedish firm UpZide Labs have announced an expanded business relationship under
which UpZide will take its reference vectorized VDSL2 (second-generation, very high-speed digital
subscriber line) design to market in a chipset using more than 50 Xtensa LX2 configurable processors.
Vectorized VDSL2 technology is used to deliver VoIP (voice over Internet protocol), VoD (video on
demand), and HDTV (high-definition television) simultaneously over standard telephone lines.
UpZide’s solution builds on the existing and continued roll-out of FTTN (fiber-to-the-network) VDSL2
deployment by increasing data rates and reach over the existing copper network and providing operators
with an alternative to FTTH (fiber-to-the-home).
UpZide >> http://www.upzide.com/
Tensilica >> http://www.tensilica.com/
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8. In-Depth Coverage Links
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Thanks to newer current conveyors, high-frequency devices like operational amplifiers no longer have to
be limited by conventional gain bandwidths. To learn more, read John Robinson's "New Look at an Old
Standard: Current Conveyor in Today's Designs."
Chip Design Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=1677
Using the Catalytic Function Library and MCS, developers can automatically generate redistributable C
code that is functionally equivalent to an original MATLAB algorithm. To learn more, read Luc
Semeria's "Generating C-code from MATLAB Functions."
iDesign Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=1848
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9. Featured Book
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Design for Manufacturability and Statistical Design: A Constructive Approach
By Michael Orshansky, Sani Nassif, and Duane Boning
ISBN: 0387309284
Publisher: Springer
Design for Manufacturability and Statistical Design: A Constructive Approach provides a thorough
treatment of the causes of variability, methods for statistical data characterization, and techniques for
modeling, analysis, and optimization of integrated circuits to improve yield. The objective of the
constructive approach developed in the book is to formulate a consistent set of methods and principles
necessary for rigorous statistical design and design-for-manufacturability from device physics to largescale circuit optimization. The segments of the book are devoted to understanding the causes of
variability, design of test structures for variability characterization, statistically rigorous data analysis,
techniques of design for manufacturability in lithography and in chemical mechanical polishing, and
statistical simulation, analysis, and optimization techniques for improving parametric yield.
Springer >> http://www.springer.com/
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10. Happenings -- Conferences
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ISSCC
San Francisco, CA
February 3-8, 2008
http://www.isscc.org/isscc/
DesignCon 2008
Santa Clara Convention Center, Santa Clara, CA
February 4-7, 2008
http://www.designcon.com/2008/
Parallel and Distributed Computing and Networks (PDCN 2008)
February 12-14, 2008
Congress Innsbruck, Innsbruck, Austria
http://www.iasted.org/conferences/home-597.html
DVCon 2008
DoubleTree Hotel, San Jose, CA
February 19-21, 2008
http://www.dvcon.org/
International Symposium on Field Programmable Gate Arrays
Monterey Beach Resort, Monterey, CA
February 24-26, 2008
http://www.ece.wisc.edu/~kati/fpga2008/
Design Automation & Test in Europe (DATE)
March 10-14, 2008
ICM, Munich, Germany
http://www.date-conference.com/
ISQED '08: The 9th Annual Symposium on Quality Electronic Design
March 17-19, 2008
DoubleTree Hotel, San Jose, CA
http://www.isqed.org/
System Level Interconnect Prediction (SLIP 2008)
Newcastle University, Newcastle. U.K.
April 5-6, 2008
http://www.sliponline.org/
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008)
April 7-9, 2008
Montpellier Convention Centre, Le Corum, Montpellier, France
http://www.lirmm.fr/isvlsi2008/
International Symposium on Networks-on-Chip (NoCS 2008)
Newcastle University, Newcastle, U.K.
April 7-11, 2008
http://async.org.uk/nocs2008/
14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2008)
Newcastle University, Newcastle, U.K.
April 7-11, 2008
http://async.org.uk/async2008/
15th Annual Reconfigurable Architectures Workshop (RAW 2008)
Miami, FL
April 14-15, 2008
http://www.ece.lsu.edu/vaidy/raw/
International Symposium on Physical Design (ISPD 2008)
Embassy Suites, Portland, OR
April 13-16, 2008
http://www.ispd.cc/
COOLChips XI
April 16-18, 2008
Yokohama Joho Bunka Center, Yokohama, Japan
http://www.coolchips.org/
International Symposium on VLSI Technology, Systems, and Applications
April 21-23, 2008
Ambassador Hotel, Hsinchu, Taiwan
http://vlsitsa.itri.org.tw/2008/General/
International Symposium on VLSI Design, Automation & Test
April 23-25, 2008
Ambassador Hotel, Hsinchu, Taiwan
http://vlsidat.itri.org.tw/2008/General/
Great Lakes Symposium on VLSI (GLSVLSI)
May 4-6, 2008
Orlando, FL
http://www.glsvlsi.org/
International Symposium on Circuits and Systems (ISCAS 2008)
Sheraton Seattle Hotel, Seattle, WA
May 18-21, 2008
http://www.iscas2008.org/
Semicon West
Moscone Center, San Francisco, CA
July 15-17, 2008
http://semiconwest.semi.org/index.htm
Signal and Image Processing (SIP 2008)
Kailua-Kona, HI
August 18-20, 2008
http://www.iasted.org/conferences/ipc-623.html
Circuits and Systems (CS 2008)
Kailua-Kona, HI
August 18-20, 2008
http://www.iasted.org/conferences/ipc-625.html
Intel Developer Forum
Moscone Center West, San Francisco, CA
August 19-20, 2008
http://www.intel.com/idf/index.htm
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