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Note: All questions carry equal marks.
Q. 1 a) b) Explain the process of following conversions with examples: i) ii) Binary to Octal and Hexadecimal Octal and Hexadecimal to Binary Differentiate Map method and Tabulation method in detail. Also discuss difference better Adder and Subtractor.
Q. 2 a) b) Define Boolean Algebra and Logic Gates. What is difference between canonical form and standard form? Which form is preferable when implementing a Boolean function with gates?
Q. 3 Given the Boolean function:
F = xyz + xy’z’ + y’z
implement it with: (a) (c) Q. 4 a) b) AND, OR, and NOT Gates Only AND and NOT Gates (b) Only OR and NOT Gates Write down the ASCII codes (in Hex.) for the characters in the string “This is a wonderful course!” excluding the quotation marks.
Write down the ASCII codes (in Dec.) for the characters in the string “Hello, hope you are doing well!” excluding the quotation marks.
Q. 5 a) b) Implement the following SOP function using NAND gate only F = XZ + YʹZ + XʹYZ Implement the following POS function using NOR gates only F = (X + Z) (Yʹ+Z) (Xʹ+Y+Z)
Total Marks: 100 Pass Marks: 50 Note: All questions carry equal marks.
Q. 1 Design an excess-3-to-BCD code converter using a 4-bit full-adders MSI circuit.
Q. 2 Using MSI circuits, construct a binary parallel adder to add two 16-bit binary number and label all carries between the MSI circuits.
Q. 3 a) Differentiate Ripple Counters and Synchronous Counters with the help of an b) example. Differentiate between multiplexer and de-multiplexer.
Q. 4 Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, 4. Use JK flip-flops.
Q. 5 a) b) Design a counter that has the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6, 7. Use RS flip-flops.
Write a note on each of the following: i) Memory ii) Decimal Adder
Recommended Book: Digital Logic Design by Morris Mano
Course Outlines: Unit–1: Binary System
Binary Numbers Based Conversion of Octal, Hexadecimal and Binary, Complements, Binary Codes, Binary Logic and ICs
Unit–2: Boolean Algebra and Logic Gates
Definitions, Theorems and Properties, Boolean Functions, Canonical and STD Forms, other Logical Properties, Gates
Unit–3: Simplification of Boolean Function
Map Method, NAND and NOR Implementation, Tabulation Method, Prime Implement 2
Unit–4: Unit–5: Unit–6: Unit–7: Unit–8: Unit–9: Combination Logic
Design Procedure, Adder, Subtractors, Code Conversation Analysis Procedure, NAND and NOR Functions, Ex-OR and Ex-NOR Function
Combination Logic with MSI and LSI
Binary Parallel Adder, Decimal Adder, BCD Counter, Magnitude Compactor, Decoders, Demultiplexers, Encoder, Multiplexer, ROM, PLA
Introduction, Flip Flop, Triggering, State Reduction Excitation Table, Design Procedure, Design of Counter
Register, Counter, and Memory Unit
Register Counter, Timing Sequence, Memory Unit
Asynchronous Sequential Logic
Analysis Procedure, Circuits with Latches, Design Procedure, Reductions of State and Flow Tables, Race Free State Assignment
Digital Integrated Circuits
Bipolar Transistor Characteristics, RTL and DTL Circuits, Transistor, Transistor Logic, Emitter Coupled Logic (ECL), Metal Oxide Semiconductor (MOS), CMOS ========== 3