Experiment E7 DC Power Supply
Worst-Case Design for Half-Wave Rectifier Circuit
James J. Whalen
Fall 2000
Experiment No. 7 DC Power Supply (Half-Wave Rectifier Circuit) provides an opportunity
to perform a worst-case design. Since design is the distinguishing characteristic of the engineering
profession, ABET recommends the teaching of design at every opportunity. Unfortunately, there is
no easy way to teach design. Design, by its very nature, requires iteration. Usually, several designs
are necessary. The design values given in the Lecture Slides for EE 312 & EE 352 in Fall 1999 are
but a first step. The initial power supply design might not perform well for a +10% & -10%
variation in ac voltage and a 100% variation in dc load current. The Zener Diode could burn up at
110% ac voltage when the load resistor is removed. That is not good. The Zener Diode could cut
off at 90% ac voltage when the load resistor connected. That is not good. A second design was
done in Fall 1999 to deal with these problems. The design procedure developed is called a worstcase design.
Important Design Rules
1. Avoid destroying the Zener diode.
2. The design must work for any Zener Diode with VZ = 12 V  10%.
3. The design must work with the load resistor connected or disconnected.
4. The design must work for an isolation transformer rms ac output voltage = 18 VAC  10%.
5. The design must work for resistors with a  10% tolerance.
6. The best design would have the best combination of the following factors:
A. The highest allowable value of dc load current at 100% ac voltage.
B. Low peak-to-peak ripple voltage under all conditions of
load variation and ac voltage variation.
C. Small change in dc load voltage under all conditions of
load variation and ac voltage variation.
Procedure
1. Design the dc power supply and enter your design in your lab notebook. Be as complete as
possible. Include the circuit schematic, design equations, and design values. Note that the
circuit schematic for a half-wave rectifier circuit is given in the References.
2. In your lab notebook create a table of design values that includes values for the following
components: RL, RF, RS, CI, & CF. You will be required to show your table to the Staff before
you are allowed to assemble the dc power supply. You may be required to explain some aspects
of your design if your design values seem unreasonable.
3. Assemble the entire dc power supply and test it as an assembly. Note that this procedure is
different from the procedure used previously in Exp. No. 8 in which the dc power supply was
assembled and tested section by section.
4. Test the entire dc power supply at 100% ac voltage (18 VAC) with the load resistor connected.
Measure the dc voltages and ac peak-to-peak ripple voltages at the nodes 1, 2 & 3 in Figure 1.
Demonstrate to Staff your results. Staff must witness all six values of voltages and sign off on
each in a space below the entry. Staff must also check and initial calculations for IZ + IL, IZ, & +
IL.
5. Repeat Step 4 with load resistor removed. No demonstration required.
6. Repeat Step 4 at 90% ac voltage (16.2 VAC) with the load resistor connected. Staff must
witness dc voltage and ac peak-to-peak ripple voltage at the node 3 and sign off on each in a
space below the entry. Staff must also check and initial calculations for IZ + IL, IZ, & + IL. Is the
Zener Diode cutoff?
7. Repeat Step 4 at 90% ac voltage with the load resistor removed. No demonstration required.
8. Repeat Step 4 at 110% ac voltage (19.8 VAC) with the load resistor connected. No
demonstration required.
9. Repeat Step 4 at 110% ac voltage with the load resistor removed. Staff must witness dc voltage
and ac peak-to-peak ripple voltage at the node 3 and sign off on each in a space below the entry.
Staff must also check and initial calculations for IZ + IL, IZ, & + IL. Is the Zener Diode
maximum current rating exceeded?
10. Enter your result from Steps 4-9 in a TABLE: DC & AC RIPPLE VOLTAGES
11. Also enter in the table the percent dc load voltage regulation. The percent dc load voltage
regulation is calculated using the dc load voltage obtained in Step 4 as the standard and using
the following equation:
Load Regulation = {VL (Step N)) - VL (Step 4)}  VL (Step 4) X 100%
where N = 5 to 9.
12. Summarize in 250 words or less the important results.
13. Submit the copies of your lab notebook pages and any PSPICE or ELECTRONIC
WORKBENCH simulations done in support of the design done prior to the lab.
Zener Diode Information
1N4742
Maximum Ratings
DC Power Dissipation
1 Watt
Derating Factor
6.67 mW per degree C
Junction Temperature
200 degree C
Electrical Characteristics at 25 C
Nominal Zener Voltage VZ @ IZT
12 V
Test Current IZT
21 mA
Max Zener Impedance ZZT @ IZT
9 ohms
Test Current IZK
0.25 mA
Max Zener Impedance ZZT @ IZK
700 ohms
Max Reverse Leakage Current IR
5 uA @ VR = 9.1 V
Max DC Zener Current IZM
76 mA
Additional Design Information
TABLE 1 VALUES OF DC VOLTAGES AT NODES 1-3 AS A FUNCTION OF VAC
%
VAC
Peak
(rms)
Rectifier
V1(dc)
V3(dc)
V1(dc)-
Diode
0.9 X (Peak
 10%
V3(dc)
Voltage
- 0.7)
V
V
V
V
V
V
100
18
25.5
0.7
22.3
12.01.2
10.31.2
90
16.2
22.9
0.7
20.0
12.01.2
8.01.2
110
19.8
28.0
0.7
24.6
12.01.2
12.61.2
Important Design Considerations
1. If the load resistor is removed, all the dc current must flow through the Zener Diode. That
current must not exceed IZM = 76 mA. The worst case is at 110% ac voltage. The dc voltage drop
across the resistors RF + RS is then given by V1(dc) - V3(dc) = (RF + RS) X IZ. The worst case
occurs at 110% ac voltage where V1 (dc) - V3 (dc) has a maximum value given by max {V1 (dc)V3 (dc)} = 12.6 + 1.2 = 13.8 V. To limit the dc current that flows through the Zener Diode to a
value less than IZM = 76 mA, the value for (RF + RS) must exceed a minimum value for RF + RS
given by
Min {RF + RS} = max {V1 (dc)- V3 (dc)}  IZM = 13.8 V/76mA = 0.1816 kohm
Min {RF + RS} = 13.8 V/76mA = 0.1816 kohm
If we allow for a 10% tolerance on the resistors, then
Min {RF + RS} = 0.1816 kohm + 10% X 0.1816 kohm = 0.1997 kohm
Min {RF + RS} = 0.1997 kohm
The nominal values available include 100 ohms. Thus an available choice is
RF = RS = 0.100 kohm = 100 ohm
2. Another important consideration is that the dc current through the Zener Diode must not fall
below some minimum value IZmin. The worst case occurs at 90% ac voltage with the load resistor
connected. The voltage V1(dc)- V3(dc) has a minimum value min{V1(dc)- V3(dc)} = 8.0 - 1.2 =
6.8 V. The current through RF + RS is a minimum and is given by
Min {IZ + ILOAD} = min {V1 (dc)- V3 (dc)}  (RF + RS)
Min {IZ + ILOAD} = 6.8V  0.200k = 34 mA
3. A value for IZ = 0.25 mA where the Max Zener Impedance ZZT = 700 ohms is obviously too low.
The dc voltage regulation will be poor, and the ac peak-to-peak ripple voltage will be high. As an
initial design decision a value for IZmin = 0.5 X IZT = 0.5 X 21 mA = 10.5 mA is selected.
IZmin = 10.5 mA
It should be noted that no design decision is final. The value selected for IZmin can be changed in a
subsequent design.
4. The value for the load current ILOAD can be determined from
ILOAD = min {IZ + ILOAD} - IZmin
ILOAD = 34 mA - 10.5 mA = 23.5 mA
ILOAD = 23.5 mA
5. The value for the load resistor RL can be determined from
RL = VZ  ILOAD
RL = 12V  23.5mA = 0.5106 kohm
RL = 511 ohm
The variable resistor available for RL should be set at 511 ohms. Use the DMM.
6. The resistors available have nominal values as given the Appendix.
7. The capacitors available have values 200 F, 100 F, and 50 F.
8. Initially the 200 F capacitor & 50 F capacitor are connected in parallel for the capacitor CI in
Figure 1, i. e. the capacitor CI = 250 F.
CI = 250 F = 0.250 mF
9. The maximum droop V across the capacitor across CI in Figure 1 can be estimated. See figure ?
in Lecture Slides. Using the expression Q = CV where Q is the charge on a capacitor C and V the
across the capacitor, the droop V can be calculated from
V = Q/C = It/C
where I = IZ + ILOAD is the discharge current for the capacitor. The worst case droop would be
obtained where I = IZ + ILOAD has a maximum value max{IZ + ILOAD} . Since the value for the sum
of the resistors (RF + RS) was chosen to limit the value of the current through them to a value IZ +
ILOAD  IZM = 76 mA, the maximum value for I is IZM = 76 mA. The maximum droop max{V} is
given by
Max {V} = IZM/60C
Max {V} = 76mA /(60 X 0.250mF) = 5.1 V
where t has been set equal to 1/f where f = 60 Hz. Actually, as shown in the Lecture slides, the
value for t will be less than 1/f. For example, for V/V = 0.8 (20% droop), the value for t is given
by t = 0.9/f. Thus the maximum droop calculated with the equations above would be overestimated by 10%.
The filter capacitor also contributes charge to the current that flows through the Zener diode and the
RL. If the value of the filter capacitor CF = 100 F = 0.100 mF is added to the value of CF = 250 F =
0.250 mF, the value obtained is
CF + CI = 250 F + 100 F = 350 F = 0.35 mF
If the value CF + CI = 0.35 mF is used to calculate the droop, the droop value is given by
Max {V} = 76mA /(60 X 0.350mF) = 3.6 V
Which value is the better choice: 5.1 V or 3.6 V? That is a question best answered using PSPICE.
Since the capacitors have 20% tolerance, the droop calculated or predicted using PSPICE
could differ from that measured by 20%.
10. The final design decision that must be made is how to divide the sum of the resistors (RF + RS).
The filter capacitor CF and the filter resistor RF form a low pass RC filter and cause a reduction in
the ac voltage between the input at node 1 and the output at node 2. The reduction in the ratio
V2/V1 for a sinusoidal signal at frequency f is given by
V2/V1 = 1/{1 + (RF 2fCF)2}0.5
One of the value used for f can be f = 60 Hz. Harmonics at 120 Hz and higher are also present.
They harmonics will be attenuated more. Previously, an initial assignment RF = 100 ohms was
made. Using RF = 100 ohms, CF = 100 F, & f = 60 Hz, the value for V2/V1 is given by
V2/V1 = 1/{1 + (100X2X60X100)2}0.5 = 0.256
Since the harmonics are attenuated even more, the variation in voltage across CF will be even less
then 0.256 times the variation in voltage across CI. Again this is a question best answered using
PSPICE.
11.
The Zener diode also causes a reduction in the ac voltage between the input at node 2 and
the output at node 3. . The reduction in the ratio V3/V2 is given by
V3/V2 = {RLrd}  {RS + RLrd}
where rd is the dynamic resistance of the Zener Diode. In E6 Dynamic Impedance a value rd = 5.6
ohms at IZ = 10 mA was measured. Using RS = 100 ohms and RLrd = 5115.6 = 5.5, the value for
V3/V2 is given by
V3/V2 = 5.5  {100 + 5.5} = 0.052
Thus the ac voltage at V3 should be more than an order of magnitude less than that at V2. Usually,
voltage at V3 is a few mV. Averaging and manual adjustments of the cursors are the best
experimental techniques to use to measure voltage at V3.
12. The ac voltage at V3 can be now be estimated. Multiple the results obtained for the droop in V1
and the voltage ratios V3/V2 & V2/V1. The results are
V3pp = 5.1V X 0.256 X 0.052 = 0.067 V = 67 mV
V3pp = 3.6V X 0.256 X 0.052 = 0.048 V = 48 mV
These results are much larger than that observed. . Again this is a question best answered using
PSPICE.
13. The division of the sum of the resistors (RF + RS) should have as its goal making the overall
reduction in the ac voltage large by making the product of the two voltage expressions small. That
is make V3/V1 small where V3/V1 is given by
V3/V1 = 1/{1 + (RF 2fCF)2}0.5 X {RLrd}  {RS + RLrd}
The values for RF & RS are limited to what is available on the Heathkit Resistance Substitution
Boxes. There are not too many combinations to test. It is recommended that neither RF nor RS be
set equal to zero. Remember that RF + RS must exceed the minimum value calculated previously to
prevent zapping the Zener Diode. The first set of values recommended for E7 may be summarized
as follows:
RF = RS = 0.100 kohm = 100 ohm
RL = 511 ohm
CI = 250 F
CF = 100 F
TABLE 2 DATA FOR DC POWER SUPPLY WITH FULL-WAVE RECTIFIER
The Fluke 8000A DMM was used to measure VT. The HP54600B CRO was used to
measure V1(avg), V1(pp), V2(avg), V2(pp), and V3(pp). The Fluke 8010A DMM was used to
measure the dc load voltage V3(avg). The load current IL was calculated using IL = V3(avg)/RL. The
current IL + IZ was calculated using IL + IZ = {V3(avg) - V1(avg)}  {RF + RS}. The Zener Diode
current was calculated using IZ = IL + IZ – IL.
TABLE 2 DATA FOR DC POWER SUPPLY WITH FULL-WAVE RECTIFIER
C = RL CONNECTED & NC = RL NOT CONNECTED
X DENOTES INITIALS REQUIRED
%
VT
VAC
rms
RL
V

100
18
C
Staff
Must
Initial
100
18
NC
90
16.2
C
90
16.2
110
19.8
C
110
19.8
NC
V1
V1
V2
V2
V3
V3
IL
IL+IZ
IZ
avg
pp
avg
pp
avg
pp
V
V
V
V
V
V
mA
mA
mA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PSPICE (or ELECTRONIC WORKBENCH) SIMULATION: Week 2
During the second week a PSPICE EXAM on the dc power supply circuit will be
conducted. PSPICE will be used to simulate the half-wave rectifier dc power supply circuit and to
determine values for all the voltages and currents measured.
The 50 F capacitor was connected in parallel with the 200 F. However, it may be that a
better dc power supply results by connecting the 50 F capacitor in parallel with the 100 F
capacitor and using the parallel combination as the filter capacitor CF. This is one of the alternative
designs that can be checked using PSPICE. Other alternative designs compatible with the worstcase design procedure such as using 150 ohms & 47 ohms for RF
&
RS can also be checked.
References:
1.
Sedra/Smith, “Microelectronics Circuits,” 4th ed. New York: Oxford University Press, 1998,
Section 3.7 Rectifier Circuits, pp. 179-191.
2.
EE 352 Fall 1999 Lecture Slides on Experiment No. 8 DC Power Supply
3.
EE 312 Fall 2000 Lecture Slides on Experiment No. 7 DC Power Supply
Appendix: Resistance Values Available
There are 29 Heathkit boxes that are available. The Heathkit resistance substitution box resister
choices are:
Low value:
15, 22, 33, 47, 68, 100, 150, 220, 330, 470, 680, 1k, 1.5k,
2.2k, 3.3k, 4.7k 6.8k 10k
A different resistance box is used to augment the 29 Heathkit boxes (20 boxes are available).
Low Values:
10, 47, 100, 220, 470, 1k, 2.2, 3.3k, 4.7k 6.8k 10k