The MINOS Far Detector : A Tutorial for Beginners
Draft 1.0
R. Rameika
June 5, 2003
Introduction
The purpose of this document is to provide an introductory
guide for those wanting to learn about the configuration and
operation of the far detector. In particular this document is
intended to give the reader a working understanding of the naming
conventions and geographical location of the hardware of the far
detector as well as some basic introduction to looking at data.
References to more detailed documentation are given where
appropriate. A general list of documents related to the far detector
can be found at http://minos-crl.minos-soudan.org/fddocs_list.html.
To gain some insight into the process of taking and analyzing
data please see the companion document : Using the MINOS Far
Detector : A Tutorial for Beginners. (coming soon...)
[Note : At this time this document does not address the hardware
related to the Veto Shield; it will be incorporated into a later
version.]
Plane Configuration
The MINOS Far Detector contains 486 planes of steel and 484
planes of scintillator. The planes are configured into two super
modules, SM1 and SM2, as shown in Figure 1. The first steel plane
of SM1, Plane 0 is not instrumented. The 248 instrumented planes
of SM1 are Planes 1 to 248. The first plane of SM2, Plane 249 is
also not instrumented. The 236 instrumented planes of SM2 are
Planes 250 to 285.
0
1
2
3 …… 248
SM1
249 250 ………………285
SM2
Figure 1 Plane Numbering Convention
Scintillator Strips
Each plane of scintillator contains 192 strips (numbered 0 to
191). Strips are oriented in either the U or V direction. (U planes
provide the V-coordinate, while V planes provide the Ucoordinate). In a U plane the top of a strip is on the East side of
the plane, and in a V plane the top of a strip is on the West side of
the plane. This is illustrated in Figure X.
TOP
U plane
V plane
Figure 2 Orientation of strips and definition of TOP and BOTTOM read out
Supermodule 1 Plane 1 is a V strip, so that in SM1 odd numbered
strips are V and even numbered strips are U. However, in SM2, the
first instrumented plane, 250 is a V strip (since 248 was a U). So in
SM2 even numbered strips are the V strips.
Scintillator Strip Readout
Each scintillator strip is read out on each end. Strips are
readout by 16-channel (pixel) photomultiplier tubes (PMTs). Strips
are connected to the PMTs by clear fiber cables. Each plane has 8
fiber cables going into a MUX box (described below). Each MUX
box takes input from 2 planes. 8 fibers are fed to a single pixel
(multiplexed). 1.5 PMT’s are required to read out a single plane.
Three PMT’s, which read out the two planes are packaged into a
single MUX Box. A schematic drawing of this is shown in Figure
X. A detailed mapping of strips to pixels can be found in
http://www-soudan.minos-soudan.org/plex/muxbox.php.
Figure 3 Schematic of scintillator plane modules connected to clear fiber cables
input to MUX boxes
16 pixels
per PMT
8 fibers per
pixel
Plane 1
West TOP
Plane 3
West TOP
1.5 PMTs
needed per
each side
of a plane
Figure 4 Schematic diagram showing PMT pixels, fiber placement within a pixel
and the sharing of PMTs between planes.
Front End Electronics (VA Chips)
On the outside of each MUX box is mounted the VA Front
End Board (VFB). Each VFB contains 3 VA chips, one for each
of the PMTs in the MUX Box. The VFB also contains an AmpShaper-Discriminator (ASD) chip which uses the single dynode
signal from each of the PMTs to processes triggers. See the
schematic (not to scale) in Figure xx. The Users Guide to the Far
Detector Electronics can be accessed from the http://minoscrl.minos-soudan.org/fddocs_list.html NuMI Note Number 901.
MUX Box
PMT s and
Bases
VFB containing
VA chips and
ASD ASD
Figure 5 Schematic diagram showing MUX Box with PMTs and the VFB board
containing the VA chips
Electronics Racks
There are three levels of relay racks located on the EAST and
WEST sides of the detector. The upper and lower levels are where
the MUX boxes containing the PMTs and Front End Boards
(VFBs) are situated. The middle level is where the High Voltage
(HV), Light Injection Pulser boxes, the
VME readout crates
containing the VA Readout Controllers (VARCs) are located.
These levels are shown schematically in Figure 3 (looking
NORTH towards the shaft and beam direction).
WEST
SIDE
MUX Boxes for
WEST Side TOP
strips
HV, PULSER and
VME electronics
for WEST Side
strips
MUX Boxes for
WEST Side
BOTTOM strips
EAST
SIDE
MUX Boxes for
EAST Side TOP
strips
HV, PULSER and
VME electronics
for EAST Side
strips
MUX Boxes for
EAST Side
BOTTOM strips
Figure 6 Schematic layout of the three decks on either side of the detector
MUX Box Arrangement
The typical MUX box rack holds 8 MUX boxes which means that it services
16 detector planes in one view. The exception is at the ends of each of the
Supermodules, where the last racks for SM1 have only 6 boxes and the last
racks for SM2 have only three boxes. The racks as arranged on each side of
the detector are shown in Figure 4. Each of these racks may be referred to as
a “Bay”.
S
N
FEE
EAST
TOP
13
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
16
Figure 7 Layout of MUX Box racks along the TOP EAST side of the detector. The
same layout is repeated for the TOP WEST, BOTTOM EAST and BOTTOM
WEST
High Voltage
The PMTs receive their High Voltage from LeCroy 1440 units
located on the middle deck. Eight mainframes are used for the
entire detector. The mainframes are situated in pairs
[(1,2),(3,4),(5,6),(7,8)] with each pair being serviced by a Ferrup
UPS. The region of the detector serviced by each mainframe is
listed in Table 1.
Mainframe
1
2
3
4
5
6
7
8
Side
EAST
EAST
WEST
WEST
EAST
EAST
WEST
WEST
Level
Bottom
Top
Top
Bottom
Bottom
Top
Top
Bottom
Two PC’s are used to control the mainframes. dcshv1 controls
mainframes 1 thru 4 which service SM1, and dcshv2 controls
mainframes 5 thru 8 for SM2. dchsv1 is located on the West side of
the detector at the racks for mainframes 3 and 4. dchsv2 is located
on the East side of the detector at the racks for mainframes 5 and 6.
These PC’s can be accessed from the DCS computer console
located in the control room. Instructions can be found in
http://www.hep.umn.edu/~jkn/install/HV%20operation.doc
A map of HV channels to PMTs can be found in the database file
/home/minos/hvmap.db, located on each of these computers. There
one will find the following information (several lines shown as an
example) :
Label
------1001-E0
1001-E1
1001-E2
MF
---1
1
1
Cd
--00
00
00
ch
--00
01
02
HV
----768
-774
-774
PMT ser#
-----------KA0566
KA0528
KA0767
1005-E0
1005-E1
1005-E2
1
1
1
00
00
00
03
04
05
-857 KA0696
-851 KA0751
-818 KA0815
MUX ID
----------EBM-0
EBM-1
EBM-2
Ser#
-----2014
2014
2014
Bottom
readout of
planes 1
and 3
EBM-0
EBM-1
EBM-2
2008
2008
2008
Bottom
readout of
planes 5
and 7
Note again that one mux box contains three PMT’s which will read out two
planes. So in the above example the East/Bottom MUX Box #1 serves the
bottom readout of planes 1 and 3.
Detector Front End Read Out
Analog signals from the VFBs are transported from the upper
and lower deck relay racks to the middle level VME Racks over a
26’ shielded twisted pair cable. A schematic drawing of the VME
Rack is shown in Figure XX. The signals enter the VME crate via
the VARC Meszzanine Modules (VMMs) which are mounted on
the VA Readout Controllers (VARC). One VMM services two
VFBs. A single VARC contains up to six VMMs and can thus
service up to 36 PMTs. Each VARC can hold up to 6 VMM
modules, and each VME crate typically holds 3 VARCs. Sixteen
crates service the entire detector.
The main function of the VMM is to digitize the VA signals
from the VFBs and to then send the digitized data to the VARC.
Each VMM is also paired with an Event Timestamp Controller
(ETC) which timestamps and coordinates the VA chip readout.
Data from the ETC is buffered into a FIFO. Each VARC holds a
sparcifier which sparcifies the data from each of the FIFOs.
Sparcified data is then sent to one of two VME buffers which are
then read out via the VME bus. Read out is contrilled by the data
acquisition system (DAQ).
Data Acquisition
A Users Guide to the DAQ can be found in the http://minoscrl.minos-soudan.org/fddocs_list.html, NuMI note #900.
Each VME Crate houses a Read Out Processor (ROP). The ROP is
[ ??] computer which interfaces to the DAQ Branch Readout
Processors (BRP) via an optical PVIC interface. (PVIC is the name
of the link that is used to allow high speed communication between
the ROPs and the BRPs and between the BRPs and TPs.)
Rack Protection System
Alarm
Warning
 Normal
Pulser Box
RS 232
w-i-e-n-e-r
0
|
Status
 overheat
 sys fail
on
off
VME Power
Supply and
CRATE
w-i-e-n-e-r
ROP
R
O
P
VARCS
MINOS FAN PACK
FILTER
Power Distribution Panel
oooooooooooo
oooooooooooo
oooooooooooo
Detector Numerologies
The Basics :
16 pixels/PMT
8 fibers/pixel
192 strips (fibers) /plane
 128 fibers/PMT  1.5 PMTs/plane side  2sides/strip 3 PMTs/plane
248 planes/SM1  744 PMTs in SM1
236 planes/SM2  708 PMTs in SM2
 484 planes in detector  1452 PMT’s in detector
484 planes  192 strips/plane  2 ends/strip
 185,856 channels in the detector
8 multiplexing  23,232 read out channels
3PMT’s/plane and 3PMT’s/MUX Box  484 MUX Boxes in detector
Detector Operation
The current status of the Far Detector Data Acquisition can be
observed from the web based status page http://minos-crl.minossoudan.org/cgi-bin-daq/daq_status.org. One can also access the control room
logbook from the MINOS CRL web interface http://minos-crl.minossoudan.org/crl.
The Control Room
User accessible monitors for Run Control and Online Monitoring are
located in the Northeast corner of the Control Room. Along the middle of
the west wall are the Detector Control System (DCS) and the Control Room
Logbook (CRL) computers.
The DAQ Room
[Still need to add this.]