MODELING AND SIMULATION OF 4H SiC MOSFETS AS A FUNCTION OF
TEMPERATURE
Submitted To: The ARL PEER (Power and Energy Electronics Research) Program
Principal Investigator: University of Maryland (UMD):
Neil Goldsman (Faculty),
Gary Pennington (Post Doctoral Research Associate)
Siddharth Potbhare (Ph.D Candidate UMD)
ECE Dept. University of Maryland, College Park, MD 20742
Army Research Laboratory Collaborators:
Charles (Skip) Scozzie
Aivars Lelis (ARL & UMD Ph.D Student), Bruce Geil (ARL & UMD M.S. Student),
Gabriel Lopez (ARL, former Merit), Dan Habersat(ARL, former Merit)
Background
We propose to continue our investigation of the design of new high-temperature/high-power
electronics based on silicon carbide (SiC), a material which shows great promise for use in power
electronics.
The ARL is designing power-conversion/motor-control systems which can operate at high
power densities and high temperatures. To control these systems, we are investigating the design
and development of high temperature voltage-controlled electronics. As was demonstrated in
industry for room-temperature applications, the optimal component for electronic control circuits
was the silicon MOSFET. For high temperature we intend to build on this strategy by developing
SiC MOSFETs. SiC is unique in the sense that it appears to be the only semiconductor capable of
operating at high temperatures, which can also be used as a basis for MOSFET fabrication.
The relatively recent commercial availability of SiC wafers has significantly increased the
possibility of electronics based on SiC MOS technology. Silicon dioxide (SiO2) can now be grown
on SiC, thus enabling the fabrication of SiC MOSFETs. By analogy with Si MOSFETs, the
realization of SiC MOSFETs provides the potential for extending the electronic revolution to high
power and high temperature applications. However, before SiC can be routinely used in electronics,
various obstacles must be overcome. As was the case with Si, early SiC MOSFETs have SiO2
interfaces that are subject to high interface trap density, which usually degrades device
performance. Interface traps can also be generated during device operation, which may give rise to
unstable current-voltage characteristics. Other phenomena affecting SiC MOSFET performance
include surface phonon scattering, surface roughness scattering and incomplete dopant ionization.
To develop robust SiC MOSFETs, these phenomena must be understood and quantified.
Our research groups at ARL and UMD have established a strong collaboration in a combined
experimental-theoretical investigation to understand and quantify phenomena affecting SiC
MOSFET performance. Measurements of interface traps and surface mobility were performed at
ARL. At UMD, computer-based simulation tools were developed to help understand the results of
these experiments, and to design new SiC devices. We have developed a custom drift-diffusion
numerical simulator to accurately model physical conditions within SiC MOSFETs. We also
developed a Monte Carlo (MC) simulator for electron transport in the bulk as well as the surface
channel in SiC .
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Key results from our investigations for the previous year (2004) [1-5]:
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Excellent agreement between the SiC 2D Model and the MOSFET measurements at low
fields from room temperature to 200C for 6H SiC devices. This agreement helped to
demonstrate that our temperature-dependent mobility model, and our temperaturedependent interface trapped model were indeed accurate. The information provided by the
model indicates the precise mechanisms responsible for performance degradation in SiC
MOSFET, and thus gives engineers specific directions for solving this problem.
Evidence from the high field, high temperature data suggest that the channel saturation
velocity is dependent on the interface trapped charge as well as temp in 6H SiC MOSFETs.
Improvements were made to the numerical solutions to the Poisson and continuity equations
in the 2D model for application to 4H SiC devices. This improvement allows for the use of
a much finer mesh in our simulations. The finer mesh will allow for greater accuracy, as
well as higher resolution in pinpointing device problem areas.
In our Monte Carlo simulations, we investigated the effects of inversion layer quantization
at the 4H-SiC MOS interface for the (0001) and the (1120) directions. Simulations show
that the mobility does increase as a direct result of the reduction of interface traps at the
(1120) surface. The simulations show the sub-band structure for different surface
orientations. The sub-band structure is a key component in determining the position of the
channel relative to the interface. The calculations indicate that the channel distance from the
interface is very similar in both orientations. This result indicates that the band-structure
differences are less important than the interface trap density in determining mobility
degradation.
Approach
Having established a foundation, where we have developed specially tailored SiC software,
obtained a variety of new experimental devices, and identified key mechanisms governing SiC
MOSFET operation, we are ideally situated to perform investigations which can help give rise to
high-peformance SiC MOSFETs. To this end, we plan to continue to develop and verify the 2D
model for 4H SiC MOSFETs. which appear promising for high-voltage, high-power, hightemperature device applications. In addition, having identified interface traps as the key mechanism
responsible for reduce surface mobility in SiC MOSFFETs, we plan to investigate the fundamental
physics underlying the occupation and generation of interface traps and oxide charge, especially
that which occurs during device operation. We also plan to develop a detailed understanding of the
fundamental physics governing coulombic scattering from interface traps.
ARL will continue to perform measurement of SiC MOS and MIS capacitors, MISFETs,
and MOSFETs. New devices will be characterized using CV, GV, I-V, and charge pumping
techniques for interface, fixed, and trapped-charge densities, and how they depend on temperature
and stressing. By working closely with the UMD computer modeling effort, details of the oxide
and interface structure will be deciphered (fast states, slow states, energy spectrum, etc.). Using
software that we have developed, we will determine the precise physical environment which exists
at the interface during device operation and stressing. The drift-diffusion simulator will help to
provide the electrostatic potential, carrier concentration and trap concentration at any point along
the interface, before and after stressing. We plan to then couple this information into our SiC Monte
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Carlo simulator, which gives the quantum states of the electrons at the interface. By correlating the
electron energy states with trap generation, we expect to develop an atomic model which predicts
interface-trap generation. This information will then be used to suggest methods for reducing
interface trap generation, and the development of more stable 4H-SiC MOSFETs.
Technical Barriers
Many technical barriers must be overcome before SiC MOSFETS can be used in circuits.
While Cree Inc. (the leader in SiC materials and devices) has produced SiC MOSFETs, these
devices’ performance are far from optimal. The problems to be surmounted include low surface
mobility, high interface-trap concentrations, high fixed-oxide charge, relatively low oxide and
insulator breakdown fields, and material defects.
In addition to technical barriers associated with the development of SiC MOSFETs, we
must overcome barriers to develop our research tools. The drift-diffusion simulator solved a very
complex system of nonlinear differential equations. This system becomes increasingly complex as
more and more realistic physics is incorporated into the model. Our challenges are to develop a
realistic model, and then to develop the numerical algorithms which can solve the mathematical
model, and do so efficiently.
Impact of Proposed Research
A new comprehensive, physical model and simulator which significantly enhances design
capabilities SiC MOSFET based electronics will be available. The new model can be used for
designing SiC MOSFETs to operate over a wide temperature range (-55 to 300C). With the
simulator we will be able to probe inside the device, where experimental measurements cannot be
taken, and determine the roots of the performance degradation of SiC MOSFETs under the required
operating conditions. Once these causes are identified, steps can be taken to modify either the
fabrication techniques or the devices’ designs.
Statement of work for 2005:
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Continue to upgrade the numerical solutions for the 2D Model to include a finer mesh at the
SiO2/SiC interface to more thoroughly examine the effects of interface trapped charge on
carrier transport in the channel as a function of temperature.
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Include the new experimental results from ARL on interface trap density as a function of
energy in the bandgap to model the 4H MOSFETs.
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Use the model to determine the best values for the oxide trapped charge in the SiC
MOSFETs. There are currently no good experimental methods to get this information. As
the Nit is reduced , the Nf will control the Vth.
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Develop improved model for separating trapped oxide charge between slow and fast states.
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Use Monte Carlo and drift-diffusion device simulator to develop deeper understanding of
the effect of interface traps on saturation velocity. Work on developing a detailed physics
based model for mobility due to interface traps that is derived using coulomb scattering and
the Fermi golden rule.
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Investigate source of sloped current-voltage curves in saturation region of new 4H
MOSFET.
Quarterly Milestones/Deliverables:
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1Q. Report on the final 6H results.
2Q. Complete coulomb scattering derivation for interface charge. Compare 2D model with
4H measurements.
3Q. Improve extraction and separation between fixed and non-fixed trapped charge.
4Q. Use the Drift Diffusion and Monte models and to examine 4H SiC carrier mobility in
the channel as a function of temperature. Submit 4H results from 2005 for publication
and/or presentation.
Referenced Publications for previous year
1) G. Pennington and N. Goldsman, ``Self-Consistent Calculations for n-Type Hexagonal SiC
Inversion Layers,” Journal of Applied Physics, Vol. 95, No. 8, pp 4223-4234, 2004.
2) G. Pennington, N. Goldsman, J. McGarrity, A Lelis and C. Scozzie, ``Comparison of 1120 and
0001 Surface Orientation in 4H SiC Inversion Layers,” Semiconductor Interface Specialists
Conference, 2003.
3) S. Potbhare, N. Goldsman, A. Lelis, “Characterization and Simulation of Novel 4H SiC
MOSFETs”, UMD Research Review Day Poster, March 2004.
4) G. Pennington, N. Goldsman, J. McGarrity, A. Lelis, C. Scozzie, ``(001) Oriented 4H-SiC
Quantized Inversion Layers," International Semiconductor Device Research Symposium, pp. 338339, 2003.
5) Stephen K. Powell, Neil Goldsman, Aivars Lelis, James M. McGarrity and Flynn B. McLean, ``High Temperature
Modeling and Characterization6H SiC MOSFETs,” submitted to Journal of Applied Physics, 2004.
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BUDGET
Completing our objectives will require the full time efforts of one UMD graduate student,
the part-time effort of one postdoctoral associate, and UMD faculty member, as well as the work of
ARL scientists. One student will be responsible for Drift-Diffusion type simulations and assistance
to the ARL experimental effort. The post doc. will be involved in Monte Carlo type modeling and
analysis at the detailed quantum atomic level. The UMD faculty member will work on model
development, provide overall direction, and maintain close collaboration with ARL.
1 Graduate Research Assistants (GRA),
40K
Post Doctoral Associate
25K
Faculty Support
10K
-------------------------------------------------------------------Total
75K
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