Rasit Onur TOPALOGLU, Ph.D.
Work: 1050 Arques Dr. MS 79, Sunnyvale, CA, 94085
Home: 2600 Cortez Dr. Apt. 8204 Santa Clara, CA, 95051
Office: 408 749 4373
Cell: 858 366 2301
Email: rasit.topaloglu@globalfoundries.com
topalogluro@gmail.com
URL: www.cs.ucsd.edu/~rtopalog
EDUCATION
I have received my Ph.D in the area of design for manufacurability (DFM).
Ph.D. in Computer Engineering, University of California, San Diego, 2008,
"Characterization, modeling and optimization of fills and stress in semiconductor
integrated circuits."
C.Phil. in Computer Engineering, University of California, San Diego, 2006.
M.S. in Computer Science, University of California, San Diego, 2005.
B.S. in Electrical & Electronic Engineering, Bogazici University, Turkey, 2002.
RESEARCH INTERESTS
Electronic Design Automation and Design for Manufacturability (DFM)
PROFESSIONAL
Sr. Technology and Integration Engineer at GLOBALFOUNDRIES, Inc. (spin-off
from AMD) since 2009.
Sr. Technology and Integration Engineer at Advanced Micro Devices 2006-2009.
AMD, 2005
National Semiconductor, 2004
Qualcomm, 2003 and 2005
Alcatel, 2002
Nortel Networks, 2001
PATENTS
6 pending patents, all applied through AMD.
AWARDS/RECOGNITION
Advanced Micro Devices Author of Merit Award, 2008.
Advanced Micro Devices Technology Development Group Technical
Achievement Award, 2008.
IEEE International Symposium on Quality Electronic Design Best Paper Award
2007.
GRE Score : Analytic : 790/800 Quantitative : 800/800
STATEMENT OF PURPOSE
I like providing innovative solutions to challenging problems. I like interacting with
and positively influencing other people. I am looking for an opportunity for this.
PUBLICATIONS
2009
[C21] K. Jeong, A. B. Kahng and R. O. Topaloglu, "Is Overlay Error More
Important Than Interconnect Variations in Double Patterning?," Proc. ACM
International Workshop on System-Level Interconnect Prediction, 2009.
[C20] A. Sultan, J. Faricelli, S. Suryagandh, H. VanMeer, K. Mathur, J. Pattison,
S. Hannon, G. Constant, K. Kumar, K. Carrejo, J. Meier, R. Topaloglu, D. Chan,
U. Hahn and T. Knopp, “CAD utilities to comprehend layout-dependent stress
effects in 45 nm high-performance SOI custom macro design,” Proc. IEEE
International Symposium on Quality Electronic Design, 2009.
2008
[C19] R.O. Topaloglu, "Interconnect variability analysis for double patterning
lithography," VLSI Multilevel Interconnection Conference, Invited Paper, 2008.
[C18] A.B. Kahng, K. Samadi and R.O. Topaloglu, "Recent topics in CMP-related
IC Design for Manufacturing," Proc. Advanced Metallization Conference, Invited
Paper, 2008.
[J6] A.B. Kahng, P. Sharma and R.O. Topaloglu, "Chip optimization through STI
stress-aware placement perturbations and fill insertion," accepted for publication
in IEEE Trans. on Computer-Aided Design, 2008.
[C17] R.O. Topaloglu, "Process variation characterization and modeling of
nanoparticle interconnects for foldable electronics," Proc. IEEE International
Symposium on Quality Electronic Design, 2008.
[J5] A.B. Kahng and R.O. Topaloglu, "DOE-based extraction of CMP, active and
via fill impact on capacitances," IEEE Trans. on Semiconductor Manufacturing,
21(1), 2008, pp. 22-32.
2007
[C16] R.O. Topaloglu, "Via chamfering modeling for improved MIM capacitance
silicon correlation," Proc. International VLSI/ULSI Multilevel Interconnection
Conference (VMIC), 2007.
[C15] A.B. Kahng and R.O. Topaloglu, "Performance-aware CMP fill pattern
optimization," Invited Paper, Proc. International VLSI/ULSI Multilevel
Interconnection Conference (VMIC), 2007.
[C14] A.B. Kahng, P. Sharma and R.O. Topaloglu, "Exploiting STI stress for
performance," Proc. IEEE/ACM International Conference on Computer-Aided
Design, 2007, pp. 83-90.
[C13] R.O. Topaloglu, "Standard cell and custom circuit optimization using
dummy diffusions through STI width stress effect utilization," Proc. IEEE Custom
Integrated Circuits Conference, 2007, pp. 619-622.
[C12] A.B. Kahng and R.O. Topaloglu, "A DOE set for normalization-based
extraction of fill impact on capacitances," Best Paper Award, Proc. IEEE
International Symposium on Quality Electronic Design, 2007, pp. 467-474.
[C11] R.O. Topaloglu, "Energy-minimization model for fill synthesis," Proc. IEEE
International Symposium on Quality Electronic Design, 2007, pp. 444-451.
[C10] A.B. Kahng and R.O. Topaloglu, "A TCAD-based study of fill pattern and
via fill impact on low-k dielectric stress," Invited Paper, Proc. International
Chemical-Mechanical Planarization for ULSI Multilevel Interconnection
Conference (CMP-MIC), 2007, pp. 337-346.
[J4] R.O. Topaloglu, "Process variation-aware multiple-fault diagnosis of
thermometer-coded current-steering DACs," IEEE Trans. on Circuits and
Systems-II: Analog and Digital Signal Processing, 54(2), 2007, pp. 191-195.
2006
[C9] A. B. Kahng and R. O. Topaloglu, "Interconnect matching design rule
inferring and optimization through correlation extraction," Proc. IEEE International
Conference on Computer Design, 2006, pp. 222-229.
[C8] R.O. Topaloglu, "Monte Carlo-alternative probabilistic simulations for analog
systems," Proc. IEEE International Symposium on Quality Electronic Design,
2006, pp. 249-253.
[C7] A.B. Kahng and R.O. Topaloglu, "Generation of design guarantees for
interconnect matching", Proc. IEEE/ACM System Level Interconnect Prediction
Workshop, 2006, pp. 29-34.
[C6] R.O. Topaloglu, "Early, accurate and fast yield estimation through Monte
Carlo-alternative probabilistic behavioral analog system simulations," Proc. IEEE
VLSI Test Symposium, 2006, pp. 136-142.
[C5] V. Wason, J.X. An, J.-S. Goo, Z.-Y. Wu, Q. Chen, C. Thuruthiyil, R.
Topaloglu, P. Chiney, and A. Icel, "Statistical compact modeling and Si
verification methodology," Invited Paper, Proc. International Conference on
Solid-State and Integrated-Circuit Technology (ICSICT), 2006, pp. 1198-1201.
[J3] E.S. Erdogan, R.O. Topaloglu, O. Cicekoglu, H. Kuntman and A. Morgul,
``Novel multiple function analog filter structures and a dual-mode multifunctioni
filter ," International Journal of Electronics, 93(9), 2006, pp.637-650, DOI:
10.1080/00207210600711713. Listed as #5 in 2006 most downloaded
articles.
2005
[C4] R.O. Topaloglu and A. Orailoglu, "Forward discrete probability propagation
method for device performance characterization under process variations," Proc.
Asia and South Pacific Design Automation Conference, 2005, pp. 220-223.
[C3] R.O. Topaloglu and A. Orailoglu, "A DFT approach for diagnosis and
process variation-aware structural test of thermometer coded current steering
DACs," Proc. IEEE/ACM/EDAC Design Automation Conference, 2005, pp. 851856.
2004
[C2] R.O. Topaloglu, A. Orailoglu, "On mismatch in the deep sub-micron era from physics to circuits," Proc. Asia and South Pacific Design Automation
Conference, 2004, pp. 62-67.
[J2] E.S. Erdogan, R.O. Topaloglu, O. Cicekoglu and H. Kuntman, "New currentmode special function continuous time active filters employing only OTAs and
OPAMPs," International Journal of Electronics, 91(6), 2004, pp. 345-359.
2003
[J1] R.O. Topaloglu, H. Kuntman and O. Cicekoglu, "Current-input current-output
notch and bandpass analog filter structures as alternatives to active-R circuits,
Frequenz," 57(5-6), 2003, pp. 123-127.
2001
[C1] R.O. Topaloglu, H. Kuntman and O. Cicekoglu, "Novel notch and bandpass
filter structures using OTAs and OPAMPs," Proc. International Conference on
Electrical and Electronics Engineering, 2001, pp. 63-67.
DETAILED WORK EXPERIENCE
Globalfoundries, Inc., 2009
Advanced Micro Devices, Sunnyvale, 2006-2009
Worked under supervision of Ali Icel
Project lead in two DFM projects:
Devised, deployed and supported a circuit reliability simulation and QA
methodology as the project lead.
Project lead on RLC-aware test structure design, device modeling and parasitic
extraction.
Provided design support for 65, 45 and 32nm technologies
Devised and deployed a circuit leakage simulation methodology
Designed and drawn in layout stress test structures for 45nm SOI technology
Worked on stress, inductor and interconnect modeling and simulation
University of California San Diego
Graduate Research Assistant, 2005-2008. Advisor: Prof. Andrew B. Kahng
Research on CAD and DFM.
Advanced Micro Devices, Sunnyvale, 2005
Worked under supervision of Ali Icel and Judy An
Worked on mathematical stress modeling for 65nm SOI devices.
Qualcomm, San Diego
Coop Engineer in QCT RF Department, 2005
Working under supervision of: Seyfi Bazarjani
Work Experience: test cost reduction, BIST and DFT implementation for analog
circuits through microprocessor programming
National Semiconductor, Santa Clara
Engineering Coop in CAD Group, 2004 summer
Worked under supervision of: Dennis Lau, Hosam Haggag
Work Experience: Process variation modeling; analog modeling
Developed and incorporated a process variation model in the static timing
analysis tool PrimeTime
Qualcomm, San Diego
Interim Engineering Intern in QCT Department, 2003 summer
Worked under supervision of: Rich Nagle, Michael Leisne
Work Experience: Analog behavioral modeling
Developed hierarchical Verilog-A models for their latest base-band analog chip to
ensure fast mixed-signal verification and test
University of California San Diego
Graduate Research Assistant, 2002-2005. Advisor: Prof. Alex Orailoglu
Research on analog and RF mismatch modeling; simulation, CAD tool design,
optimization
Refereed papers for a number of design automation and VLSI conferences and
proposals for NSF (National Science Foundation)
University of California San Diego
Graduate Teaching Assistant, 2003 summer and 2005 winter
Teaching Experience: Digital Design
Held problem solving classes, office hours and conducted grading
Bogazici University, Istanbul, Turkey
Research with Prof. Oguzhan Cicekoglu
Research on design of current mode analog filters
Bogazici University, Istanbul, Turkey
Research with Prof. Gunhan Dundar
Research on analog VLSI CAD and fast simulators
Alcatel Microelectronics Manufacturing Dept., Istanbul, Turkey, Summer 2002
Attended training on System C design language
Implemented and tested circuits in System C
Designed parallel encoder, decoder, interleaver, de-interleaver block with
communication buffers
Attended training on VHDL
Implemented, synthesized and verified circuits in VHDL
Alcatel Manufacturing Department, Istanbul, Turkey, Summer 2001
Experience:
Experience in control and testing of circuit fabrication and manufacturing
Nortel Networks Research and Development Dept., Istanbul, Turkey, Summer
2000
Experience:
Attended SDH (Synchronous Digital Hierarchy) course
Learned techniques for implementing this technology in software
COMPUTER/HARDWARE SKILLS
I am proficient with most of the below languages/tools.
I have drawn 45nm test structure layouts that went onto production
Programming languages: C, C++, Java, Assembly (Intel 8086, Sparc, Qualcomm
DSP), C#, ML
Hardware & system description languages: VHDL, VHDL-AMS, Verilog-A,
System C
Circuit simulation languages: HSPICE, Spectre
Layout tools: Calibre Workbench, Calibre, IC Station, Astro
Analog/RF design: ADS, Analog Design Environment
RC Extraction tools: StarRCXT, Assura
Timing tools: PrimeTime
Scripting languages: Perl, Tcl, C-shell
Math Applications: MATLAB, Mathematica
Altera FPGA Synthesis tools
Parallel programming and linear algebra: PBLAS, LAPACK, POSIX threads
GPGPU programming: ATI FireStream series