A Multi-FPGA Demonstrator with POF-based Optical Area
Interconnect
M. Brunfauta, J. Depreiterea, W. Meeusa, J. M. Van Campenhouta, H. Melchiorb, R. Annenb, P.
Zenklusenb, R. Bockstaelec, L. Vanwassenhovec, J. Halld, A. Neyere, B. Wittmanne, P.
Heremansf, J. Van Koetsemg, R. Kingh, H. Thienpontj, R. Baetsc
Universiteit Gent – IMEC, Department ELIS, St. Pietersnieuwstraat 41, B-9000 Gent;
Eidgenössische Hochschule Zürich, Institute of Quantum Electronics;
c
Universiteit Gent – IMEC, Department INTEC;
d
GEC Marconi Materials Technology;
e
University of Dortmund;
f
IMEC, Department MAP;
g
Framatome Connectors International;
h
University of Ulm;
j
University of Brussels
a
b
It is our goal to demonstrate the viability of massively parallel optical interconnects
between electronic VLSI chips. This is done through the development of the
technology necessary for the realisation of such interconnections, and the definition
and realisation of a systems architecture in which these interconnections play a
meaningful role. Multi-FPGA systems have been identified as a good candidate for
the introduction of low level optoelectronic interconnects, from both the systems and
the purely demonstrator related points of view[1].
FPGAs are electronic components that can be programmed to implement arbitrary
electronic designs. As programming can be done in-situ and repetitively, FPGAs are
being applied in quickly growing numbers in a large variety of applications [2]. They
are currently being used as replacements for random logic in situations where ASIC
design is not indicated; as configurable processors and coprocessors; and as fast
prototyping platforms for real-time or near real-time prototyping of VLSI designs
before actual chip fabrication. In these last two applications, invariably multi-FPGA
systems are required. Not suprisingly, their flexibility (programmability) comes with a
price. For a given silicon area, the sizes of designs that FPGAs can harbour are much
smaller then ASIC implementations and to make things worse, FPGAs are frequently
plagued by a lack of interconnect capabilities[3] . Multi-FPGA systems in particular
suffer from the lack of inter-chip interconnect capability. On the one hand,
optoelectronic area-I/O for multi-FPGA systems would offer a definite advantage in
terms of interconnect capability[4]. On the other, the speed of the (programmable)
electrical on-chip or off-chip interconnect system is lower than that of dedicated
ASICs. As a result, optical interconnects, even if they are not optimised for latency,
[1]
J. Van Campenhout, H. Van Marck, J. Depreitere, and J. Dambre, Optoelectronic FPGAs, IEEE Journal of
Selected Topics in Quantum Electronics on Smart Photonic Components, Interconnects, and Processing, to appear.
[2] J. Cong, and C. Ebeling, guest editors. Special Section on Field Programmable Gate Arrays. IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, 6(2), June 1998.
[3]
S. Hauck. The Roles of FPGAs in Reprogrammable Systems, Proceedings of the IEEE, 86(4):615–
638, April 1998
[4]
J. Depreitere, H. Van Marck, and J. Van Campenhout, A quantitative analysis of the benefits of the use of areaI/O pads in FPGAs, Microprocessors and Microsystems, 21(2):89–97, October 1997.
provide a viable substitute and extension of the electrical interconnect system in
multi-FPGA systems[5].
In demonstrator terms, FPGAs have the following advantages: only one type of
silicon chip has to be designed and produced. Virtually the entire chip can be tested
electrically before the hybridisation with the optical components takes place. FPGAs
have a regular internal structure that blends well with the ultimate goal of regularly
spaced and interlaced optical components across the surface of a silicon chip. FPGAs
contain a lot of redundancy due to their programmability and regularity. This provides
a badly needed robustness against local defects in the demonstrator system. No prior
limits are imposed onto the actual demonstrator functionality. FPGAs are generic
components allowing implementation of several applications. FPGAs further allow a
meaningful demonstration of logic-level optical interconnect, which is desirable for
its relative simplicity, but which does not seem to be a sensible approach outside the
context of programmable logic.
An optoelectronic FPGA demonstrator along these lines is currently being realised.
This involves besides the actual CMOS FPGA, the design and implementation of
various light sources and detectors, as well as the analogue CMOS interface circuits;
the building blocks of the optical pathways, which are based upon plastic optical
fibre; and the methodology for hybrid assembly, packaging and passive alignment of
all components.
The optoelectronic FPGA demonstrator aims at using a smart-pixel like interconnect
structure to create a logically 3-dimensional architecture. This architecture
conceptually consists of a number of electronic planes (electrical FPGAs), that are
interconnected bi-directionally along a regular pattern that runs across the chip
surface. This pattern consists of quadruplets, two transmitters and two receivers. One
pair connects to the upper layer, the other to the lower. Prior research[1] has indicated
that such an architecture has a higher routing capacity than traditional 2-D systems;
hence, very complex (fast) designs are much easier to place and route in such an
architecture, and result in faster circuit realisations. Figure 1 shows a conceptual view
of this architecture.
The full-custom CMOS FPGA circuit is an 8  8 array of a simple configurable logic
blocks (a 4-bit function table, one flip-flop), interconnected by a programmable 6  6
switch matrix fabric. The switch matrices, traditionally responsible for the on-chip
interconnections, have now been extended to include the off-chip optical
interconnections. The optical components consist of two 8  8 source arrays (either
LEDs or VCSELs) and two 8  8 InP detector arrays, which are flip-chip bonded to
the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving
and receiving circuits are realised in CMOS, and are intermixed with the digital
circuits.
Each of the 256 optical channels is designed to operate at an information rate of 80
Mbit/s, a typical data rate for high-end commercial FPGAs. To ensure reliable
communication over so many parallel channels in a noisy digital environment, ACcoupled communication with Manchester coded data is used in the design. Hence, the
information rate of 80 Mbit/s requires a signalling rate of 160 Mbaud.
The optical pathways between the central chip and its two neighbours consists of
removable 8  16 POF ribbons as shown in figure 3. The two outer chips are equipped
with 2  8  8 ribbons with horizontal insertion POF-ribbon connectors allowing a
[5]
J. M. Van Campenhout, Optics and the CMOS interconnection problem: a systems and circuits
perspective, International Journal of Optoelectronics, 12(4):145–154, 1998
closed, toroidal interconnect, or an open optical I/O access to the system. The three
packaged FPGA chips will also be interconnected electrically, through commercially
available programmable interconnection chips, in such a way that the largest variety
of tests with both electrical and optical interconnections is possible.
The CMOS FPGA chips containing approx. 165,000 transistors on 6.3 mm  8.3 mm,
have been fabricated in the AMS three metal 0.6 μm technology (figure 2).
Preliminary tests of the CMOS functionality have been completed with good results.
The hybridisation and packaging steps of the CMOS chips and the optical components
are under way.
driver and receiver
Fig.1 Concept of a 3-D FPGA demonstrator
areasin PGA package
Fig. 2 CMOS FPGA chip mounted
Optical pathway blocks (encapsulated+mounted)
(fibers only)
Control port
Electrical
I/O
FPGA
assembly
Electronic
interconnect
chip
Electrical
I/O
Fig. 3 CAD rendering of the demonstrator design with the three optoelectronic FPGA chips (145 pin PGA) on sockets. On the left, a
mounted and encapsulated optical pathway; and on the right, an unmounted 8  16 fibre bundle with end plates only are shown.
Barely visible on the bottom right is one of the cooling fans attached to the bottom of the PGA package of each FPGA chip.
Acknowledgement
This paper presents results of the ESPRIT MEL–ARI Project 221 641 OIIC, initiated
by the European Commission and of the Inter University Attraction Poles Program
IUAP/IV-13, initiated by the Belgian State, Prime Minister’s Service, Science Policy
Office.