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10399
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狀態 G0496505153
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輔仁大學
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電子工程學系
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學號 496505153
研究
生(中 吳信宏
)
研究
生(英 Shin Hung Wu
)
論文
名稱( 可即時偵測錯誤之乘法器之設計與實現
中)
論文
名稱( On-line Detection of Faults in Multipliers
英)
其他
題名
指導
教授( 林寬仁 呂學坤
中)
指導
教授( Kuan-Jen Lin Shyue-Kung Lu
英)
校內
2012.7.16
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01
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學位
碩士
類別
畢業
學年 98
度
出版
99
年
語文
中文
別
關鍵
字(中 加法器 乘法器 TSC 檢查器
)
關鍵
字(英 On-line fault detection Carry-select adder Multiplier TSC
)
本研究主要探討在乘法器架構上加入即時偵測錯誤之機制，透過這個方式的運用
便能夠即時的檢測到錯誤之發生，避免得到錯誤的運算結果，提高乘法器電路之
可靠度。我們的研究所使用的乘法器架構係由進位選擇加法器 (Carry-select adder)
所組成，因為其具有較短的延遲時間以及不同進位的加法結果，此特性可拿來搭
配一個內建兩線輸出的檢查器 (2-rail checker) 以及一些反多工器來做選擇使用，
摘要(
透過組合邏輯之計算就能分辨出此運算結果是否正確。但是這個做法並不能保證
中)
所有的錯誤點都能被涵蓋，仍有部分節點的錯誤是無法被即時偵測的，因為此設
計主要是以加法之結果來做為判斷依據，如果在輸入位元就受到錯誤影響的話，
就不能保證能被偵測到。除此之外，經我們分析與確認後，其它內部故障點都能
有效被偵測出來。而透過 Cell-based 設計流程的使用，我們實現了一具即時錯誤
偵測機制之 16位元乘法器，額外的硬體成本為 33.23%，操作頻率為 100 MHz。
In this paper, we present an efficient scheme to implement on-line fault detection
circuits for multipliers. The multiplier is composed of carry-select adders (CSA’s).
Carry-select adder is one of the faster types of adders. The proposed detection structure
uses a scheme that encodes the sum bits using two-rail codes. The encoded sum bits are
摘要(
then checked by self-checking checkers (2-rail checker). The multiplexers used in the
英) adder are also totally self-checking. The proposed scheme is illustrated with the
implementation of a 16-bit multiplier that can detect all single stuck-at faults
concurrently. However, the detection of double faults is not guaranteed. The extra area
overhead is 33.23% and the maximum operational frequency is 100 MHz。
摘要 i 英文摘要 ii 目 錄 iv 表目錄 v 圖目錄 vi 第一章 導 論 1 1.1 研究動機 3 1.2 研
究目的 4 1.3 論文架構 5 第二章 乘法器架構簡介 6 2.1 串並式乘法器 7 2.2 陣列式
論文 乘法器 9 第三章 即時偵測技術 11 3.1 偵測架構說明 11 3.2 加法器的架構及技術
目次 13 3.3 即時偵測技術 15 第四章 乘法器的即時偵測架構 23 4.1 乘法器的即時偵測
作法 23 4.2 乘法器的即時偵測實例說明 27 第五章 實驗結果 31 5.1 晶片設計流程
31 5.2 模擬結果 34 5.3 晶片實作結果 38 第六章 結論 46 未來研究 47 參考文獻 48
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論文
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