Section 7.2
Worksheet
Section 7.2: Design
Example design section
This is a partially completed design section for the scenario provided below. It is not detailed enough
for you to implement the program from it. The task is to add the detail and complete the design. This
exercise should help you understand the amount of detail needed in the design section of a Computing
Project. The programming language for this exercise is not specified. Whichever language is selected
may dictate which sections need to be completed. For example, a class diagram will be required if the
language is object oriented (e.g. Java, C++).
Scenario: Interactive Teaching Aid for Logic Gates
The computing teacher at your school would like an interactive tool to create logic gate diagrams,
including the adding and deleting of gates and creating a truth table for each circuit. The program must
be able to use AND, NAND, OR, NOR, XOR and NOT. It must be capable of having up to 5 inputs
and up to 10 gates on any one diagram.
1. Outline System Design: System flow chart
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Section 7.2
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2. Hierarchy chart
3. Structure chart
4. Algorithms using structured English or pseudo code
Add logic gate
10 of each type of logic gate images will be put on the screen in a stack on top of each other,
one stack for each type of gate. Each one can then be selected and moved into the work area.
When a logic gate is moved into the work area, the position and type of logic gate is added to
an array to record that it is in use.
As the logic gate is moved the drag drop properties are set so that the drag image is a logic
gate.
The array will be used to keep count of the number of logic gates added.
The maximum number of gates is ten so when the array has 10 elements, logic gate images
can be disabled.
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Section 7.2
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Add connector
A connector must connect an input to a logic gate or an output from a logic gate to another
logic gate. These positions are recorded in the array of logic gates so a connector can only be
placed in the correct position.
Only one connector can be dropped on each position of a logic gate.
More than one connector can be connected to an input.
The start and end positions of the connections are also recorded in an array which is used to
check connectors do not have more than one position.
Object diagrams and class definitions
6. Design Data Dictionary and data structures (Query from TS: 5 not 6?)
List of all the variables to be used in the Logic Gates project.
Name
Data Type
Logic Gate Array(0,10)
String
Type of logic gate
Logic Gate Array(1,10)
Integer
Input position 1
Logic Gate Array(2,10)
Integer
Input position 2
Logic Gate Array(3,10)
Integer
Output position
Connector (0,10)
String
Type of connector
Connector (1,10)
Integer
Start position
Connector (2,10)
Integer
End position
Input (0,10)
String
Name of input
Truthtablearray(3,8)
Integer
Stores values of truth tables for
each gate
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Section 7.2
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File organisation
This project will be stored on the school network during development. The school backs up
their servers daily so I will not be making daily backups but will transfer the project to my
memory stick at key stages.
I have estimated the size of a form to be 1 kB and each image is also approximately 1.5 kB.
This means that the form should be approximately 1 + 1.5 x 6 x 10 = 91 kB. Thus the form
when all the connectors are in place should have a maximum size of 100 kB. The size of the
arrays I have estimated to be 2 kB assuming an integer is 2 bytes and a string is 50 bytes. I
have estimated the size of the project should not exceed 150 kB and therefore will easily fit
on a memory stick for transfer and on the hardware I have specified.
The software should be able to be installed easily on any of the school computers so all the
members of the sixth form can use it. I will compile it into .exe format (when it is complete)
for easy transfer.
The user manual will also be transferred with the software. I am not familiar with creating
.hlp files so I shall create this document in Word and transfer it as a pdf document. This
should be no more than 2Mb.
Human–Computer-Interface design
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