1. Background Module (BKG.A)
The background manager is the heart of the software, splitting a 256 Hz timer
interrupt into a number of subtasks that all run on a fixed timebase. It also
provides some reprogrammable vectors for temporary or permanent use by
subsequent functional layers of software.
1.1 Initialization
1.1.1 Vector Initialization
While the BKG module has the 256Hz interrupt vector filled in the 8085 location
for the RST7.5 interrupt, the BKG module provides several optional interrupt
vectors planned for use by the rest of the program. These are the Housekeeping
vector, the Background vector and the Spin vector (HSK, BKG and SPN,
respectively.
BKG and HSK vectors are tasks from within the 256 Hz RST7.5 interrupt, while
the SPN vector is actually the RST6.5 interrupt of the 8085. Thus, BKG_INIT()
initializes BKG and HSK vectors to point to “RET” (return) instructions, while
initializing the SPN vector to a routine to reset the RST6.5 interrupt.
1.1.2 Interrupt Initialization
Once the module vectors are initialized, BKG_INIT() enables the BKG module
tasks by the enabling of the 256 Hz interrupt, and enables the high speed
telemetry packet interrupts. Spin interrupts are disabled since the spin angle is
sampled in the 256 Hz routine.
1.2 Operation
A majority of the processor tasks are handled under the following interrupts:
Interrupt
Description
Max (Hz)
RST7.5 (CLOCK)
256 Hz Clock Circuit
256
RST6.5 (TMDMA) High Speed Telemetry Packet DMA done
200
RST5.5 (SPNSEC) Spin Sector (32 sectors/spin)
62.5
The RST7.5_CLOCK interrupt is 256 Hz, driven off the 223 Hz clock from the
BAU, and in sync with the 1-second ticks. Command processing, telemetry buffer
management, time-tagging of the sun sensor inputs, etc, are time-sliced activities
performed in this interrupt.
The RST6.5_TMDMA interrupt occurs whenever a High Speed Telemetry packet
has completed being transferred from memory, and the HST circuit is ready for
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another packet address. The BKG module provides this interrupt to the TM
module to handle the interrupt.
When enabled, RST5.5_SPNSEC interrupt occurs 32 times per spin
1.3 Time Determination
IDPU software receives and maintains Universal Time (UT) and ensures that all
time stamps have the correct time in the following manner. Time packets from
the BAU regularly update the IDPU time structure, defined as 4 bytes of seconds
and 2 bytes of sub-seconds. The packet is delivered to the IDPU within 500
milliseconds of the 1-second tick mark. IDPU software adds 1 to determine the
time at the next tick mark, saves this in a temporary register called Next-Second.
When the 1-second tick mark is observed, the Next-Second register is latched
into the IDPU Time register by the interrupt software.
During each second, the IDPU software receives 256 interrupts per second
based upon the spacecraft-provided 223 Hz clock. Using these interrupts, the
Time register is maintained to 1/256ths of a second. For packets requiring the
most precise time possible, the input clock register may be read by FSW and
stamped on each packet header.
1.4 Watchdog
The watchdog handler shall reset the watchdog circuit each time it is called (once
per second). A watchdog reset pulse is generated if the CPU does not write to
the Watchdog Reset Clear register for a period of 3 seconds.
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