CET270 – Intro. to Microprocessor Design
Notes 18
INTERRUPT CONCEPTS
I. Introduction
When programming a CPU to perform I/O operations, we normally rely on various “status”
bits within I/O interfaces to signal when certain external events occur. Once these status bits
activate, it is up to the software to notice this and react accordingly. We can do this with bit
masking and program loops as we have seen previously; this then is known as the polling I/O
technique. One problem with polling is if the processor is off executing code other than the
polling loop, it can easily miss fast changing events. An analogy here would be trying to
receive a phone call on a telephone that does not ring.
In contrast, the interrupt I/O technique allows the CPU to not have to constantly watch for
some event; instead an asynchronous interrupt will be sent to the CPU when the event
occurs as a signal for its attention. Now the phone can ring.
Thus, interrupts provide a most useful mechanism in computer systems in which high
priority events may be handled most efficiently with improved CPU utilization; also used in
synchronization situations.
 Interrupts are used in real-time applications (i.e. scheduled/"timed" interrupts).
 Interrupts require both hardware and software to be used effectively.
In terms of execution, an enabled interrupt causes the CPU to stop normal program
execution and perform an appropriate interrupt service routine to handle the interrupt.
Normal program execution resumes upon completing the service routine.
[ref: Miller, fig. 6-30]
II. Terminology
 Interrupt: a high-priority, asynchronous event occurring in a computer system that requires
(immediate) servicing by the processor.
 Interrupt Request (IRQ): a high-priority, asynchronous signal (message) sent from an I/O
device/interface to the processor indicating that the device/interface needs processor
attention.
 Interrupt Service Routine (ISR): an asynchronously executed (never "called" by the
programmer) routine performed by the processor in response to an IRQ.
 Interrupt Vector: a reserved memory location that contains the address of the ISR to be
invoked for the respective interrupt.
 Interrupt Vector Table: a table of all interrupt vectors for a particular CPU.
 RTI: the special “ReTurn from Interrupt” instruction that must be used at the end of an ISR.
III. Interrupt Details
Instruction execution timeline: controller-sequencer checks for interrupt condition between
(but not within) instruction execution. Thus: a pending interrupt can only be serviced after
completion of any given instruction, never during!
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CET270 – Intro. to Microprocessor Design
Notes 18
Interrupt Operation: given an enabled IRQ, the CPU performs the following sequence of
events.
1. finishes current instruction
2. pushes [all] registers on the stack, starting with the PC
3. identifies source of pending interrupt and starting address of respective ISR
4. vectors to appropriate ISR
4. executes ISR code normally until RTI is encountered
5. recalls [all] registers from stack ending with the PC, thus returning to next instruction in
interrupted (main) program
Again, interrupts are asynchronous – note how their operation is very different from
subroutine calls.
IV. Interrupt Sources
Early processors typically supported only one or two interrupt sources; modern processors
support many interrupt causes, sometimes more than 100.
The HC11 support 16 hardware interrupts, 2 software interrupts (SWI, illegal opcode) and 3
“reset” interrupts (Reset, COP fail, clock monitor fail).
Two of the hardware interrupts are external, i.e. ̅̅̅̅̅
𝐼𝑅𝑄 and ̅̅̅̅̅̅̅
𝑋𝐼𝑅𝑄 pins.
When multiple interrupt sources occur simultaneously, interrupts may be prioritized – those
with higher priority receives CPU attention sooner.
V. Interrupt Masking
̅̅̅̅̅̅̅).
Most interrupts are maskable, while a few are not (illegal opcode fetch, SWI, 𝑋𝐼𝑅𝑄
A maskable interrupt is one that may be ignored by setting the I-flag in the CCR, clearing
this flag enables such interrupts.
The CLI / SEI instructions are used to enable/disable maskable interrupts respectively.
VI. Interrupt Service Routine Do's & Don'ts
 keep the ISR short (time-wise); "get in, get it done, get out"
 reset hardware that caused interrupt as appropriate
 use the proper return instruction (not RTS)
 beware of side-effects of modifying registers, memory locations, etc.
VII. Application Examples
1. In the traffic light controller lab, consider adding a pedestrian crosswalk request button in
such a fashion to never miss a button press and to not mess up the normal green-yellow-red
sequence. Hint: use the HC11’s “IRQ” input.
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