Design document
<Module Name>
Project Fenix
Customer: BrazilIP
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logo>
or
Project
Version : 1.0
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[Note: The following template is provided for use with the ipPROCESS enclosed in square
brackets and displayed in blue italics (style=ip_comment) is included to provide guidance to
the author and should be deleted before publishing the document.]
Revision History
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Version
Description
Author
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n.m
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Table of Contents
1.
Introduction ................................................ 4
1.1
Document Overview...................................................4
1.2
Definitions, Acronyms and Abbreviations ..........................4
2.
Package diagrams ......................................... 4
2.1
Memory Access Subsystem Package................. 4
2.1.1
Internal Package Diagram (optional) ............................. 4
2.1.2
Capsules Diagram ................................................... 4
2.1.3
Main capsules ........................................................ 5
2.1.4
Protocols ........................................................... 10
3.
<Project Name>
References ............................................... 10
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1. Introduction
[This section must be used for describe the purpose of this document and for whom is it for]
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1.1 Document Overview
This document is composed by the following sections:

Section 2 – Package diagram this section describes and explains the packages
that form the module, its capsules and its protocols.

Section 3 – References: this section provides a complete list of all
documents referenced elsewhere in this document.
1.2 Definitions, Acronyms and Abbreviations
[This subsection provides the definitions of all terms, acronyms, and abbreviations required to
properly interpret this document. This information may be provided by reference to the
project's Glossary.]
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Term
Description
Name
Detail {style=ip_table_text}
2. Package diagrams
Show the UML representation of Package diagrams.
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2.1 Memory Subsystem Package
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2.1.1
Internal Package Diagram (optional)
It shows the internal diagram of packages references to the described package in the last
topic.
2.1.2
Capsules Diagram
It shows and gives the general explanation about the capsules diagram references to the
already described package.
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2.1.3
Main capsules
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[CAP 001] Memory Access Control
This capsule is responsible for controlling the memory access subsystem.
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Operations:

executeCmd: This operation is responsible for translate the entry command
and execute the respctive task. The ports TD, ED, MemoryRW,
DataPacketGetSEt and HccaGetSet give communication respectively with the
Transfer_Descriptor, Endpoint_Descriptor, Memory_Capsule and
Data_Packet_Control capsules according with the respective protocols. The
Mem_Acc_IF port implements the Memory Access Interface and gives
comunication with external subsystems.

Command:
0x00 – while in the wait state, the command entry must have this value.
0x01
0x02
0x03
0x04
0x05
[SD 001]
– WriteDataPacket: receives the address of the packet.
– ReadDataPacket:
– RemoveTD:
– NextTD:
– LoadED: receives the address of the ED.
< Capsule name > structure diagram
Shows and explains the structure diagram references to the last described capsule, if there is
a conjugated port, doesn’t need explanation only a reference.
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[STD 001] < Capsule name > state diagram
Shows and explains the structure diagram references to the last described capsule.
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[CAP 002] Transfer_Descriptor capsule
This capsule represents the register that contains the Transfer Descriptor data.
Operations:
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
getSetField: This operation is responsible for get and set the attributes in
this capsule.

Command:
0x00 - while in the wait state, the command entry must have this value.
0x01 – get: return the specific value.
0x02 – set: set the specific field.

Fields:
0x00 – BufferEnd: contains the value of the physical address of the last byte in the
buffer for this TD. Contains the bits 00 to 31.
0x01 – CondittionCode: contains the bits 28 to 31 of the Transfer Descriptor.
0x02 – CurrentBufferPointer: contains the bits 00 to 31. The physical address of
the next memory location that will be accessed for the transfer to/from the
endpoint. A value of zero indicates a zerolength data packet or that all bytes
have been transferred.
0x03 – DataToggle: get the bits 24 and 25. Is updated after each succsseful
transmission/reception of a data packet.
0x04 – DI: get the bits 21 to 23.
0x05 – EC: get the bits 26 and 27. Is modified in each transmission error, this
value is incremented.
[CAP 003] EndPoint_Descriptor capsule
This capsule represents the register that contains the EndPoint Descriptor data.
 Operations:
getSetField: This operation is responsible for get and set the attributes in this
capsule.
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
Commands:
0x00 - while in the wait state, the command entry must have this value.
0x01 – get: return the specific value.
0x02 – set: set the specific field.

Fields:
0x01 –EN: bits 07 to 10.
0x02 –C: contain the last data toggle value. Bit 01.
0x03 –FA: bits 00 to 06.
0x04 –H: indicate that processing of the TD queue on the endpoint is halted. bit 00.
0x05 –HeadP: points to the next TD to be processed for this endpoint. bits 04 to 31.
0x06 –K: bit 14.
0x07 –MPS: bits 16 to 26.
0x08 –NextED: bits 04 to 31.
0x09 –S: bit 13.
0x0A –TailP: bits 04 to 31.
[CAP 004] Data_Packet capsule
This capsule represents the register that contains the Data_Packet data.
Operations:

getSet: This operation is responsible for get and set the data buffer.
0x00 - while in the wait state, the command entry must have this value.
0x01 – getData_Packet: get the data.
0x02 – setData_Packet: set the data.
[CAP 005] Data_Packet_control capsule
This capsule is responsible for controlling the memory_Data_Packet access subsystem.
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Operations:

ExecuteCmd: This operation is responsible for translate the entry command
and execute the respctive task. The ports DP_HC, and Mem_DP give
communication respectively with the Data_Packet and
Memory_Access_Control capsules according with the respective protocols.
The DP_HC_port implements the Memory Access Interface and gives
comunication with external subsystems.
The signals above can be used in both ports Mem_DP, DP_HC. The result will
be put on the data signal on the respective port.

Command:
0x00 - while in the wait state, the command entry must have this value.
0x01 – get: return the specific value.
0x02 – set: set the specific index.

Index:
0x00 to 0x1F – the index of the data to be manipulated.
[CAP 006] Memory_Capsule capsule
This capsule is responsible to read and write in the memory.
Operations:

readWrite: This operation is responsible for read and write the data in the
memory.
[CAP 007] Hcca capsule
This capsule represents the register that contains the Hcca data.
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Operrations:

getSet: This operation is responsible for get and set the attributes in this
capsule.

Command:
0x00 - while in the wait state, the command entry must have this value.
0x01 – get: return the specific value.
0x02 – set: the specific index.
 Fields:
0x00 – HccaInterruptTable: bits 00 to 31.
0x01 – HccaFrameNumber: Is updated by the HC before it begins
processing the periodic list for the frame.
0x02 – HccaDoneHead: put the value from HccaDoneHead to this location
anda generates an interrupt if interrupts are enable.
2.1.4
Protocols
Explains each protocol that it is obeyed for the described capsules above and shows its UML
Representation, if the protocol already was described previously, it describes it as conjugated
and makes a reference to its description.
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[PROT 001] <Protocol name>
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
<signal name>: <explaining>
3. References
[This section provides a complete list of all documents referenced elsewhere in this document.
Identify each document by title, report number (if applicable), date, and publishing
organization. Specify the sources from which the references can be obtained. This information
may be provided by reference to an appendix or to another document.]
[1] Rational {style= ip_reference}
[2] Document Title; <File name and link >;
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[3] Title; Number (if applicable); Date; Institution, Team responsible for the
document; Document link;
[4] …
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